[mirror_ubuntu-focal-kernel.git] / arch / powerpc / boot / dts / fsl / p2041si-pre.dtsi

/*
 * P2041 Silicon/SoC Device Tree Source (pre include)
 *
 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

/include/ "e500mc_power_isa.dtsi"

/ {
	compatible = "fsl,P2041";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ccsr = &soc;
		dcsr = &dcsr;

		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		usb0 = &usb0;
		usb1 = &usb1;
		dma0 = &dma0;
		dma1 = &dma1;
		sdhc = &sdhc;
		msi0 = &msi0;
		msi1 = &msi1;
		msi2 = &msi2;

		crypto = &crypto;
		sec_jr0 = &sec_jr0;
		sec_jr1 = &sec_jr1;
		sec_jr2 = &sec_jr2;
		sec_jr3 = &sec_jr3;
		rtic_a = &rtic_a;
		rtic_b = &rtic_b;
		rtic_c = &rtic_c;
		rtic_d = &rtic_d;
		sec_mon = &sec_mon;

		fman0 = &fman0;
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		ethernet4 = &enet4;
		ethernet5 = &enet5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: PowerPC,e500mc@0 {
			device_type = "cpu";
			reg = <0>;
			clocks = <&mux0>;
			next-level-cache = <&L2_0>;
			fsl,portid-mapping = <0x80000000>;
			L2_0: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu1: PowerPC,e500mc@1 {
			device_type = "cpu";
			reg = <1>;
			clocks = <&mux1>;
			next-level-cache = <&L2_1>;
			fsl,portid-mapping = <0x40000000>;
			L2_1: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu2: PowerPC,e500mc@2 {
			device_type = "cpu";
			reg = <2>;
			clocks = <&mux2>;
			next-level-cache = <&L2_2>;
			fsl,portid-mapping = <0x20000000>;
			L2_2: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu3: PowerPC,e500mc@3 {
			device_type = "cpu";
			reg = <3>;
			clocks = <&mux3>;
			next-level-cache = <&L2_3>;
			fsl,portid-mapping = <0x10000000>;
			L2_3: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
	};
};
Commit	Line	Data
8b8673b8 KG	1	/*
	2	* P2041 Silicon/SoC Device Tree Source (pre include)
	3	*
da414bb9	4	* Copyright 2011 - 2015 Freescale Semiconductor Inc.
8b8673b8 KG	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/dts-v1/;
2f4acb05 OY	36
	37	/include/ "e500mc_power_isa.dtsi"
	38
8b8673b8 KG	39	/ {
	40	compatible = "fsl,P2041";
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43	interrupt-parent = <&mpic>;
	44
	45	aliases {
	46	ccsr = &soc;
	47	dcsr = &dcsr;
	48
	49	serial0 = &serial0;
	50	serial1 = &serial1;
	51	serial2 = &serial2;
	52	serial3 = &serial3;
	53	pci0 = &pci0;
	54	pci1 = &pci1;
	55	pci2 = &pci2;
	56	usb0 = &usb0;
	57	usb1 = &usb1;
	58	dma0 = &dma0;
	59	dma1 = &dma1;
	60	sdhc = &sdhc;
	61	msi0 = &msi0;
	62	msi1 = &msi1;
	63	msi2 = &msi2;
	64
	65	crypto = &crypto;
	66	sec_jr0 = &sec_jr0;
	67	sec_jr1 = &sec_jr1;
	68	sec_jr2 = &sec_jr2;
	69	sec_jr3 = &sec_jr3;
	70	rtic_a = &rtic_a;
	71	rtic_b = &rtic_b;
	72	rtic_c = &rtic_c;
	73	rtic_d = &rtic_d;
	74	sec_mon = &sec_mon;
da414bb9 IL	75
	76	fman0 = &fman0;
	77	ethernet0 = &enet0;
	78	ethernet1 = &enet1;
	79	ethernet2 = &enet2;
	80	ethernet3 = &enet3;
	81	ethernet4 = &enet4;
	82	ethernet5 = &enet5;
8b8673b8 KG	83	};
	84
	85	cpus {
	86	#address-cells = <1>;
	87	#size-cells = <0>;
	88
	89	cpu0: PowerPC,e500mc@0 {
	90	device_type = "cpu";
	91	reg = <0>;
5d1a566e	92	clocks = <&mux0>;
8b8673b8	93	next-level-cache = <&L2_0>;
e83eb028	94	fsl,portid-mapping = <0x80000000>;
8b8673b8 KG	95	L2_0: l2-cache {
	96	next-level-cache = <&cpc>;
	97	};
	98	};
	99	cpu1: PowerPC,e500mc@1 {
	100	device_type = "cpu";
	101	reg = <1>;
5d1a566e	102	clocks = <&mux1>;
8b8673b8	103	next-level-cache = <&L2_1>;
e83eb028	104	fsl,portid-mapping = <0x40000000>;
8b8673b8 KG	105	L2_1: l2-cache {
	106	next-level-cache = <&cpc>;
	107	};
	108	};
	109	cpu2: PowerPC,e500mc@2 {
	110	device_type = "cpu";
	111	reg = <2>;
5d1a566e	112	clocks = <&mux2>;
8b8673b8	113	next-level-cache = <&L2_2>;
e83eb028	114	fsl,portid-mapping = <0x20000000>;
8b8673b8 KG	115	L2_2: l2-cache {
	116	next-level-cache = <&cpc>;
	117	};
	118	};
	119	cpu3: PowerPC,e500mc@3 {
	120	device_type = "cpu";
	121	reg = <3>;
5d1a566e	122	clocks = <&mux3>;
8b8673b8	123	next-level-cache = <&L2_3>;
e83eb028	124	fsl,portid-mapping = <0x10000000>;
8b8673b8 KG	125	L2_3: l2-cache {
	126	next-level-cache = <&cpc>;
	127	};
	128	};
	129	};
	130	};