[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / boot / dts / gef_sbc310.dts

/*
 * GE SBC310 Device Tree Source
 *
 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Based on: SBS CM6 Device Tree Source
 * Copyright 2007 SBS Technologies GmbH & Co. KG
 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
 * Copyright 2006 Freescale Semiconductor Inc.
 */

/*
 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
 */

/dts-v1/;

/ {
	model = "GEF_SBC310";
	compatible = "gef,sbc310";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8641@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
		PowerPC,8641@1 {
			device_type = "cpu";
			reg = <1>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;	// set by uboot
	};

	localbus@fef05000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8641-localbus", "simple-bus";
		reg = <0xfef05000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
			  1 0 0xe0000000 0x08000000	// Paged Flash 0
			  2 0 0xe8000000 0x08000000	// Paged Flash 1
			  3 0 0xfc100000 0x00020000	// NVRAM
			  4 0 0xfc000000 0x00010000>;	// FPGA

		/* flash@0,0 is a mirror of part of the memory in flash@1,0
		flash@0,0 {
			compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
			reg = <0x0 0x0 0x01000000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "firmware";
				reg = <0x0 0x01000000>;
				read-only;
			};
		};
		*/

		flash@1,0 {
			compatible = "gef,sbc310-paged-flash", "cfi-flash";
			reg = <0x1 0x0 0x8000000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "user";
				reg = <0x0 0x7800000>;
			};
			partition@7800000 {
				label = "firmware";
				reg = <0x7800000 0x800000>;
				read-only;
			};
		};

		nvram@3,0 {
			device_type = "nvram";
			compatible = "simtek,stk14ca8";
			reg = <0x3 0x0 0x20000>;
		};

		fpga@4,0 {
			compatible = "gef,fpga-regs";
			reg = <0x4 0x0 0x40>;
		};

		wdt@4,2000 {
			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x2000 0x8>;
			interrupts = <0x1a 0x4>;
			interrupt-parent = <&gef_pic>;
		};
/*
		wdt@4,2010 {
			compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x2010 0x8>;
			interrupts = <0x1b 0x4>;
			interrupt-parent = <&gef_pic>;
		};
*/
		gef_pic: pic@4,4000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
			reg = <0x4 0x4000 0x20>;
			interrupts = <0x8
				      0x9>;
			interrupt-parent = <&mpic>;

		};
		gef_gpio: gpio@4,8000 {
			#gpio-cells = <2>;
			compatible = "gef,sbc310-gpio";
			reg = <0x4 0x8000 0x24>;
			gpio-controller;
		};
	};

	soc@fef00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8641-soc", "simple-bus";
		ranges = <0x0 0xfef00000 0x00100000>;
		bus-frequency = <33333333>;

		mcm-law@0 {
			compatible = "fsl,mcm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		mcm@1000 {
			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		i2c1: i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			rtc@51 {
				compatible = "epson,rx8581";
				reg = <0x00000051>;
			};
		};

		i2c2: i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			hwmon@48 {
				compatible = "national,lm92";
				reg = <0x48>;
			};

			hwmon@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};

			eti@6b {
				compatible = "dallas,ds1682";
				reg = <0x6b>;
			};
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8641-dma-channel",
					   "fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30  2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "gmii";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&gef_pic>;
					interrupts = <0x9 0x4>;
					reg = <1>;
					device_type = "ethernet-phy";
				};
				phy2: ethernet-phy@2 {
					interrupt-parent = <&gef_pic>;
					interrupts = <0x8 0x4>;
					reg = <3>;
					device_type = "ethernet-phy";
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;
			phy-connection-type = "gmii";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <0x2a 0x2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <0x1c 0x2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8641-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@fef08000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xfef08000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
		interrupt-map = <
			0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
			0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
			0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
			0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x40000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00400000>;
		};
	};

	pci1: pcie@fef09000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xfef09000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <0x19 0x2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
			0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
			0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
			0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
			>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xc0000000
				  0x02000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00400000>;
		};
	};
};
Commit	Line	Data
bb2b66dc	1	/*
948e78c3	2	* GE SBC310 Device Tree Source
bb2b66dc	3	*
948e78c3	4	* Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
bb2b66dc MW	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*
	11	* Based on: SBS CM6 Device Tree Source
	12	* Copyright 2007 SBS Technologies GmbH & Co. KG
	13	* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
	14	* Copyright 2006 Freescale Semiconductor Inc.
	15	*/
	16
	17	/*
	18	* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
	19	*/
	20
	21	/dts-v1/;
	22
	23	/ {
	24	model = "GEF_SBC310";
	25	compatible = "gef,sbc310";
	26	#address-cells = <1>;
	27	#size-cells = <1>;
	28
	29	aliases {
	30	ethernet0 = &enet0;
	31	ethernet1 = &enet1;
	32	serial0 = &serial0;
	33	serial1 = &serial1;
	34	pci0 = &pci0;
9b952a39	35	pci1 = &pci1;
bb2b66dc MW	36	};
	37
	38	cpus {
	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
	42	PowerPC,8641@0 {
	43	device_type = "cpu";
	44	reg = <0>;
	45	d-cache-line-size = <32>; // 32 bytes
	46	i-cache-line-size = <32>; // 32 bytes
	47	d-cache-size = <32768>; // L1, 32K
	48	i-cache-size = <32768>; // L1, 32K
	49	timebase-frequency = <0>; // From uboot
	50	bus-frequency = <0>; // From uboot
	51	clock-frequency = <0>; // From uboot
	52	};
	53	PowerPC,8641@1 {
	54	device_type = "cpu";
	55	reg = <1>;
	56	d-cache-line-size = <32>; // 32 bytes
	57	i-cache-line-size = <32>; // 32 bytes
	58	d-cache-size = <32768>; // L1, 32K
	59	i-cache-size = <32768>; // L1, 32K
	60	timebase-frequency = <0>; // From uboot
	61	bus-frequency = <0>; // From uboot
	62	clock-frequency = <0>; // From uboot
	63	};
	64	};
	65
	66	memory {
	67	device_type = "memory";
	68	reg = <0x0 0x40000000>; // set by uboot
	69	};
	70
	71	localbus@fef05000 {
	72	#address-cells = <2>;
	73	#size-cells = <1>;
	74	compatible = "fsl,mpc8641-localbus", "simple-bus";
	75	reg = <0xfef05000 0x1000>;
	76	interrupts = <19 2>;
	77	interrupt-parent = <&mpic>;
	78
	79	ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
	80	1 0 0xe0000000 0x08000000 // Paged Flash 0
	81	2 0 0xe8000000 0x08000000 // Paged Flash 1
	82	3 0 0xfc100000 0x00020000 // NVRAM
	83	4 0 0xfc000000 0x00010000>; // FPGA
	84
	85	/* flash@0,0 is a mirror of part of the memory in flash@1,0
	86	flash@0,0 {
433abcdf MW	87	compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
433abcdf MW	88	reg = <0x0 0x0 0x01000000>;
bb2b66dc MW	89	bank-width = <2>;
	90	device-width = <2>;
	91	#address-cells = <1>;
	92	#size-cells = <1>;
	93	partition@0 {
	94	label = "firmware";
433abcdf	95	reg = <0x0 0x01000000>;
bb2b66dc MW	96	read-only;
	97	};
	98	};
	99	*/
	100
	101	flash@1,0 {
433abcdf MW	102	compatible = "gef,sbc310-paged-flash", "cfi-flash";
433abcdf MW	103	reg = <0x1 0x0 0x8000000>;
bb2b66dc MW	104	bank-width = <2>;
	105	device-width = <2>;
	106	#address-cells = <1>;
	107	#size-cells = <1>;
	108	partition@0 {
	109	label = "user";
433abcdf	110	reg = <0x0 0x7800000>;
bb2b66dc MW	111	};
	112	partition@7800000 {
	113	label = "firmware";
433abcdf	114	reg = <0x7800000 0x800000>;
bb2b66dc MW	115	read-only;
	116	};
	117	};
	118
9093067a MW	119	nvram@3,0 {
	120	device_type = "nvram";
	121	compatible = "simtek,stk14ca8";
	122	reg = <0x3 0x0 0x20000>;
	123	};
	124
bb2b66dc MW	125	fpga@4,0 {
	126	compatible = "gef,fpga-regs";
	127	reg = <0x4 0x0 0x40>;
	128	};
	129
	130	wdt@4,2000 {
433abcdf MW	131	compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
433abcdf MW	132	"gef,fpga-wdt";
bb2b66dc MW	133	reg = <0x4 0x2000 0x8>;
	134	interrupts = <0x1a 0x4>;
	135	interrupt-parent = <&gef_pic>;
	136	};
	137	/*
	138	wdt@4,2010 {
433abcdf MW	139	compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
433abcdf MW	140	"gef,fpga-wdt";
bb2b66dc MW	141	reg = <0x4 0x2010 0x8>;
	142	interrupts = <0x1b 0x4>;
	143	interrupt-parent = <&gef_pic>;
	144	};
	145	*/
	146	gef_pic: pic@4,4000 {
	147	#interrupt-cells = <1>;
	148	interrupt-controller;
433abcdf	149	compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
bb2b66dc MW	150	reg = <0x4 0x4000 0x20>;
	151	interrupts = <0x8
	152	0x9>;
	153	interrupt-parent = <&mpic>;
	154
	155	};
	156	gef_gpio: gpio@4,8000 {
	157	#gpio-cells = <2>;
	158	compatible = "gef,sbc310-gpio";
	159	reg = <0x4 0x8000 0x24>;
	160	gpio-controller;
	161	};
	162	};
	163
	164	soc@fef00000 {
	165	#address-cells = <1>;
	166	#size-cells = <1>;
	167	#interrupt-cells = <2>;
	168	device_type = "soc";
433abcdf	169	compatible = "fsl,mpc8641-soc", "simple-bus";
bb2b66dc	170	ranges = <0x0 0xfef00000 0x00100000>;
bb2b66dc MW	171	bus-frequency = <33333333>;
bb2b66dc MW	172
da385780 KG	173	mcm-law@0 {
	174	compatible = "fsl,mcm-law";
	175	reg = <0x0 0x1000>;
	176	fsl,num-laws = <10>;
	177	};
	178
	179	mcm@1000 {
	180	compatible = "fsl,mpc8641-mcm", "fsl,mcm";
	181	reg = <0x1000 0x1000>;
	182	interrupts = <17 2>;
	183	interrupt-parent = <&mpic>;
	184	};
	185
bb2b66dc MW	186	i2c1: i2c@3000 {
	187	#address-cells = <1>;
	188	#size-cells = <0>;
	189	compatible = "fsl-i2c";
	190	reg = <0x3000 0x100>;
	191	interrupts = <0x2b 0x2>;
	192	interrupt-parent = <&mpic>;
	193	dfsrr;
	194
	195	rtc@51 {
	196	compatible = "epson,rx8581";
	197	reg = <0x00000051>;
	198	};
	199	};
	200
	201	i2c2: i2c@3100 {
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	compatible = "fsl-i2c";
	205	reg = <0x3100 0x100>;
	206	interrupts = <0x2b 0x2>;
	207	interrupt-parent = <&mpic>;
	208	dfsrr;
	209
	210	hwmon@48 {
	211	compatible = "national,lm92";
	212	reg = <0x48>;
	213	};
	214
	215	hwmon@4c {
	216	compatible = "adi,adt7461";
	217	reg = <0x4c>;
	218	};
	219
	220	eti@6b {
	221	compatible = "dallas,ds1682";
	222	reg = <0x6b>;
	223	};
	224	};
	225
	226	dma@21300 {
	227	#address-cells = <1>;
	228	#size-cells = <1>;
	229	compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
	230	reg = <0x21300 0x4>;
	231	ranges = <0x0 0x21100 0x200>;
	232	cell-index = <0>;
	233	dma-channel@0 {
	234	compatible = "fsl,mpc8641-dma-channel",
	235	"fsl,eloplus-dma-channel";
	236	reg = <0x0 0x80>;
	237	cell-index = <0>;
	238	interrupt-parent = <&mpic>;
	239	interrupts = <20 2>;
	240	};
	241	dma-channel@80 {
	242	compatible = "fsl,mpc8641-dma-channel",
	243	"fsl,eloplus-dma-channel";
	244	reg = <0x80 0x80>;
	245	cell-index = <1>;
	246	interrupt-parent = <&mpic>;
	247	interrupts = <21 2>;
	248	};
	249	dma-channel@100 {
250	compatible = "fsl,mpc8641-dma-channel",
251	"fsl,eloplus-dma-channel";
252	reg = <0x100 0x80>;
253	cell-index = <2>;
254	interrupt-parent = <&mpic>;
255	interrupts = <22 2>;
256	};
257	dma-channel@180 {
258	compatible = "fsl,mpc8641-dma-channel",
259	"fsl,eloplus-dma-channel";
260	reg = <0x180 0x80>;
261	cell-index = <3>;
262	interrupt-parent = <&mpic>;
263	interrupts = <23 2>;
264	};
265	};
266
bb2b66dc	267	enet0: ethernet@24000 {
d8bc55fb AV	268	#address-cells = <1>;
d8bc55fb AV	269	#size-cells = <1>;
62f3de91	270	cell-index = <0>;
bb2b66dc	271	device_type = "network";
62f3de91	272	model = "TSEC";
bb2b66dc MW	273	compatible = "gianfar";
bb2b66dc MW	274	reg = <0x24000 0x1000>;
d8bc55fb	275	ranges = <0x0 0x24000 0x1000>;
bb2b66dc	276	local-mac-address = [ 00 00 00 00 00 00 ];
62f3de91	277	interrupts = <29 2 30 2 34 2>;
bb2b66dc	278	interrupt-parent = <&mpic>;
62f3de91	279	tbi-handle = <&tbi0>;
bb2b66dc MW	280	phy-handle = <&phy0>;
bb2b66dc MW	281	phy-connection-type = "gmii";
d8bc55fb AV	282
	283	mdio@520 {
	284	#address-cells = <1>;
	285	#size-cells = <0>;
	286	compatible = "fsl,gianfar-mdio";
	287	reg = <0x520 0x20>;
	288
	289	phy0: ethernet-phy@0 {
	290	interrupt-parent = <&gef_pic>;
	291	interrupts = <0x9 0x4>;
	292	reg = <1>;
62f3de91	293	device_type = "ethernet-phy";
d8bc55fb AV	294	};
	295	phy2: ethernet-phy@2 {
	296	interrupt-parent = <&gef_pic>;
	297	interrupts = <0x8 0x4>;
	298	reg = <3>;
62f3de91 MW	299	device_type = "ethernet-phy";
	300	};
	301	tbi0: tbi-phy@11 {
	302	reg = <0x11>;
	303	device_type = "tbi-phy";
d8bc55fb AV	304	};
d8bc55fb AV	305	};
bb2b66dc MW	306	};
	307
	308	enet1: ethernet@26000 {
62f3de91 MW	309	#address-cells = <1>;
	310	#size-cells = <1>;
	311	cell-index = <2>;
bb2b66dc	312	device_type = "network";
62f3de91	313	model = "TSEC";
bb2b66dc MW	314	compatible = "gianfar";
bb2b66dc MW	315	reg = <0x26000 0x1000>;
62f3de91	316	ranges = <0x0 0x26000 0x1000>;
bb2b66dc	317	local-mac-address = [ 00 00 00 00 00 00 ];
62f3de91	318	interrupts = <31 2 32 2 33 2>;
bb2b66dc	319	interrupt-parent = <&mpic>;
62f3de91	320	tbi-handle = <&tbi2>;
bb2b66dc MW	321	phy-handle = <&phy2>;
bb2b66dc MW	322	phy-connection-type = "gmii";
62f3de91 MW	323
	324	mdio@520 {
	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327	compatible = "fsl,gianfar-tbi";
	328	reg = <0x520 0x20>;
	329
	330	tbi2: tbi-phy@11 {
	331	reg = <0x11>;
	332	device_type = "tbi-phy";
	333	};
	334	};
bb2b66dc MW	335	};
	336
	337	serial0: serial@4500 {
	338	cell-index = <0>;
	339	device_type = "serial";
	340	compatible = "ns16550";
	341	reg = <0x4500 0x100>;
	342	clock-frequency = <0>;
	343	interrupts = <0x2a 0x2>;
	344	interrupt-parent = <&mpic>;
	345	};
	346
	347	serial1: serial@4600 {
	348	cell-index = <1>;
	349	device_type = "serial";
	350	compatible = "ns16550";
	351	reg = <0x4600 0x100>;
	352	clock-frequency = <0>;
	353	interrupts = <0x1c 0x2>;
	354	interrupt-parent = <&mpic>;
	355	};
	356
	357	mpic: pic@40000 {
	358	clock-frequency = <0>;
	359	interrupt-controller;
	360	#address-cells = <0>;
	361	#interrupt-cells = <2>;
	362	reg = <0x40000 0x40000>;
	363	compatible = "chrp,open-pic";
	364	device_type = "open-pic";
	365	};
	366
f5d570d3 MW	367	msi@41600 {
	368	compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
	369	reg = <0x41600 0x80>;
	370	msi-available-ranges = <0 0x100>;
	371	interrupts = <
	372	0xe0 0
	373	0xe1 0
	374	0xe2 0
	375	0xe3 0
	376	0xe4 0
	377	0xe5 0
	378	0xe6 0
	379	0xe7 0>;
	380	interrupt-parent = <&mpic>;
	381	};
	382
bb2b66dc MW	383	global-utilities@e0000 {
	384	compatible = "fsl,mpc8641-guts";
	385	reg = <0xe0000 0x1000>;
	386	fsl,has-rstcr;
	387	};
	388	};
	389
	390	pci0: pcie@fef08000 {
	391	compatible = "fsl,mpc8641-pcie";
	392	device_type = "pci";
	393	#interrupt-cells = <1>;
	394	#size-cells = <2>;
	395	#address-cells = <3>;
	396	reg = <0xfef08000 0x1000>;
	397	bus-range = <0x0 0xff>;
	398	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
	399	0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
	400	clock-frequency = <33333333>;
	401	interrupt-parent = <&mpic>;
	402	interrupts = <0x18 0x2>;
9b952a39	403	interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
bb2b66dc MW	404	interrupt-map = <
	405	0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
	406	0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
	407	0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
	408	0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
	409	>;
	410
	411	pcie@0 {
	412	reg = <0 0 0 0 0>;
	413	#size-cells = <2>;
	414	#address-cells = <3>;
	415	device_type = "pci";
	416	ranges = <0x02000000 0x0 0x80000000
	417	0x02000000 0x0 0x80000000
	418	0x0 0x40000000
	419
	420	0x01000000 0x0 0x00000000
	421	0x01000000 0x0 0x00000000
	422	0x0 0x00400000>;
	423	};
	424	};
8798b9df MW	425
	426	pci1: pcie@fef09000 {
	427	compatible = "fsl,mpc8641-pcie";
	428	device_type = "pci";
	429	#interrupt-cells = <1>;
	430	#size-cells = <2>;
	431	#address-cells = <3>;
	432	reg = <0xfef09000 0x1000>;
	433	bus-range = <0x0 0xff>;
	434	ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
	435	0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
	436	clock-frequency = <33333333>;
	437	interrupt-parent = <&mpic>;
	438	interrupts = <0x19 0x2>;
	439	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	440	interrupt-map = <
	441	0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
	442	0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
	443	0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
	444	0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
	445	>;
	446
	447	pcie@0 {
	448	reg = <0 0 0 0 0>;
	449	#size-cells = <2>;
	450	#address-cells = <3>;
	451	device_type = "pci";
	452	ranges = <0x02000000 0x0 0xc0000000
	453	0x02000000 0x0 0xc0000000
	454	0x0 0x20000000
	455
	456	0x01000000 0x0 0x00000000
	457	0x01000000 0x0 0x00000000
	458	0x0 0x00400000>;
	459	};
	460	};
bb2b66dc	461	};