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8159df72 HS |
1 | /* |
2 | * Keymile KMETER1 Device Tree Source | |
3 | * | |
93e2b95c | 4 | * 2008-2011 DENX Software Engineering GmbH |
8159df72 HS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | ||
14 | / { | |
15 | model = "KMETER1"; | |
16 | compatible = "keymile,KMETER1"; | |
17 | #address-cells = <1>; | |
18 | #size-cells = <1>; | |
19 | ||
20 | aliases { | |
21 | ethernet0 = &enet_piggy2; | |
22 | ethernet1 = &enet_estar1; | |
23 | ethernet2 = &enet_estar2; | |
24 | ethernet3 = &enet_eth1; | |
25 | ethernet4 = &enet_eth2; | |
26 | ethernet5 = &enet_eth3; | |
27 | ethernet6 = &enet_eth4; | |
28 | serial0 = &serial0; | |
29 | }; | |
30 | ||
31 | cpus { | |
32 | #address-cells = <1>; | |
33 | #size-cells = <0>; | |
34 | ||
35 | PowerPC,8360@0 { | |
36 | device_type = "cpu"; | |
37 | reg = <0x0>; | |
38 | d-cache-line-size = <32>; // 32 bytes | |
39 | i-cache-line-size = <32>; // 32 bytes | |
40 | d-cache-size = <32768>; // L1, 32K | |
41 | i-cache-size = <32768>; // L1, 32K | |
42 | timebase-frequency = <0>; /* Filled in by U-Boot */ | |
43 | bus-frequency = <0>; /* Filled in by U-Boot */ | |
44 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
45 | }; | |
46 | }; | |
47 | ||
48 | memory { | |
49 | device_type = "memory"; | |
50 | reg = <0 0>; /* Filled in by U-Boot */ | |
51 | }; | |
52 | ||
53 | soc8360@e0000000 { | |
54 | #address-cells = <1>; | |
55 | #size-cells = <1>; | |
56 | device_type = "soc"; | |
57 | compatible = "fsl,mpc8360-immr", "simple-bus"; | |
58 | ranges = <0x0 0xe0000000 0x00200000>; | |
59 | reg = <0xe0000000 0x00000200>; | |
60 | bus-frequency = <0>; /* Filled in by U-Boot */ | |
61 | ||
1f8a25d4 AV |
62 | pmc: power@b00 { |
63 | compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; | |
64 | reg = <0xb00 0x100 0xa00 0x100>; | |
65 | interrupts = <80 0x8>; | |
66 | interrupt-parent = <&ipic>; | |
67 | }; | |
68 | ||
8159df72 HS |
69 | i2c@3000 { |
70 | #address-cells = <1>; | |
71 | #size-cells = <0>; | |
72 | cell-index = <0>; | |
93e2b95c | 73 | compatible = "fsl,mpc8313-i2c","fsl-i2c"; |
8159df72 HS |
74 | reg = <0x3000 0x100>; |
75 | interrupts = <14 0x8>; | |
76 | interrupt-parent = <&ipic>; | |
93e2b95c | 77 | clock-frequency = <400000>; |
8159df72 HS |
78 | }; |
79 | ||
80 | serial0: serial@4500 { | |
81 | cell-index = <0>; | |
82 | device_type = "serial"; | |
f706bed1 | 83 | compatible = "fsl,ns16550", "ns16550"; |
8159df72 HS |
84 | reg = <0x4500 0x100>; |
85 | clock-frequency = <264000000>; | |
86 | interrupts = <9 0x8>; | |
87 | interrupt-parent = <&ipic>; | |
88 | }; | |
89 | ||
90 | dma@82a8 { | |
91 | #address-cells = <1>; | |
92 | #size-cells = <1>; | |
93 | compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; | |
94 | reg = <0x82a8 4>; | |
95 | ranges = <0 0x8100 0x1a8>; | |
96 | interrupt-parent = <&ipic>; | |
97 | interrupts = <71 8>; | |
98 | cell-index = <0>; | |
99 | dma-channel@0 { | |
100 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | |
101 | reg = <0 0x80>; | |
102 | interrupt-parent = <&ipic>; | |
103 | interrupts = <71 8>; | |
104 | }; | |
105 | dma-channel@80 { | |
106 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | |
107 | reg = <0x80 0x80>; | |
108 | interrupt-parent = <&ipic>; | |
109 | interrupts = <71 8>; | |
110 | }; | |
111 | dma-channel@100 { | |
112 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | |
113 | reg = <0x100 0x80>; | |
114 | interrupt-parent = <&ipic>; | |
115 | interrupts = <71 8>; | |
116 | }; | |
117 | dma-channel@180 { | |
118 | compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; | |
119 | reg = <0x180 0x28>; | |
120 | interrupt-parent = <&ipic>; | |
121 | interrupts = <71 8>; | |
122 | }; | |
123 | }; | |
124 | ||
125 | ipic: pic@700 { | |
126 | #address-cells = <0>; | |
127 | #interrupt-cells = <2>; | |
128 | compatible = "fsl,pq2pro-pic", "fsl,ipic"; | |
129 | interrupt-controller; | |
130 | reg = <0x700 0x100>; | |
131 | }; | |
132 | ||
133 | par_io@1400 { | |
134 | #address-cells = <1>; | |
135 | #size-cells = <0>; | |
136 | reg = <0x1400 0x100>; | |
137 | compatible = "fsl,mpc8360-par_io"; | |
138 | num-ports = <7>; | |
139 | ||
93e2b95c HB |
140 | qe_pio_c: gpio-controller@30 { |
141 | #gpio-cells = <2>; | |
142 | compatible = "fsl,mpc8360-qe-pario-bank", | |
143 | "fsl,mpc8323-qe-pario-bank"; | |
144 | reg = <0x1430 0x18>; | |
145 | gpio-controller; | |
146 | }; | |
8159df72 HS |
147 | pio_ucc1: ucc_pin@0 { |
148 | reg = <0>; | |
149 | ||
150 | pio-map = < | |
151 | /* port pin dir open_drain assignment has_irq */ | |
152 | 0 1 3 0 2 0 /* MDIO */ | |
153 | 0 2 1 0 1 0 /* MDC */ | |
154 | ||
155 | 0 3 1 0 1 0 /* TxD0 */ | |
156 | 0 4 1 0 1 0 /* TxD1 */ | |
157 | 0 5 1 0 1 0 /* TxD2 */ | |
158 | 0 6 1 0 1 0 /* TxD3 */ | |
159 | 0 9 2 0 1 0 /* RxD0 */ | |
160 | 0 10 2 0 1 0 /* RxD1 */ | |
161 | 0 11 2 0 1 0 /* RxD2 */ | |
162 | 0 12 2 0 1 0 /* RxD3 */ | |
163 | 0 7 1 0 1 0 /* TX_EN */ | |
164 | 0 8 1 0 1 0 /* TX_ER */ | |
165 | 0 15 2 0 1 0 /* RX_DV */ | |
166 | 0 16 2 0 1 0 /* RX_ER */ | |
167 | 0 0 2 0 1 0 /* RX_CLK */ | |
168 | 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ | |
169 | 2 8 2 0 1 0 /* GTX125 - CLK9 */ | |
170 | >; | |
171 | }; | |
172 | ||
173 | pio_ucc2: ucc_pin@1 { | |
174 | reg = <1>; | |
175 | ||
176 | pio-map = < | |
177 | /* port pin dir open_drain assignment has_irq */ | |
178 | 0 1 3 0 2 0 /* MDIO */ | |
179 | 0 2 1 0 1 0 /* MDC */ | |
180 | ||
181 | 0 17 1 0 1 0 /* TxD0 */ | |
182 | 0 18 1 0 1 0 /* TxD1 */ | |
183 | 0 19 1 0 1 0 /* TxD2 */ | |
184 | 0 20 1 0 1 0 /* TxD3 */ | |
185 | 0 23 2 0 1 0 /* RxD0 */ | |
186 | 0 24 2 0 1 0 /* RxD1 */ | |
187 | 0 25 2 0 1 0 /* RxD2 */ | |
188 | 0 26 2 0 1 0 /* RxD3 */ | |
189 | 0 21 1 0 1 0 /* TX_EN */ | |
190 | 0 22 1 0 1 0 /* TX_ER */ | |
191 | 0 29 2 0 1 0 /* RX_DV */ | |
192 | 0 30 2 0 1 0 /* RX_ER */ | |
193 | 0 31 2 0 1 0 /* RX_CLK */ | |
194 | 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ | |
195 | 2 3 2 0 1 0 /* GTX125 - CLK4 */ | |
196 | >; | |
197 | }; | |
198 | ||
199 | pio_ucc4: ucc_pin@3 { | |
200 | reg = <3>; | |
201 | ||
202 | pio-map = < | |
203 | /* port pin dir open_drain assignment has_irq */ | |
204 | 0 1 3 0 2 0 /* MDIO */ | |
205 | 0 2 1 0 1 0 /* MDC */ | |
206 | ||
207 | 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ | |
208 | 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ | |
209 | 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ | |
210 | 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ | |
211 | 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ | |
212 | 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ | |
213 | 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ | |
214 | ||
215 | 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ | |
216 | >; | |
217 | }; | |
218 | ||
219 | pio_ucc5: ucc_pin@4 { | |
220 | reg = <4>; | |
221 | ||
222 | pio-map = < | |
223 | /* port pin dir open_drain assignment has_irq */ | |
224 | 0 1 3 0 2 0 /* MDIO */ | |
225 | 0 2 1 0 1 0 /* MDC */ | |
226 | ||
227 | 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ | |
228 | 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ | |
229 | 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ | |
230 | 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ | |
231 | 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ | |
232 | 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ | |
233 | 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ | |
234 | >; | |
235 | }; | |
236 | ||
237 | pio_ucc6: ucc_pin@5 { | |
238 | reg = <5>; | |
239 | ||
240 | pio-map = < | |
241 | /* port pin dir open_drain assignment has_irq */ | |
242 | 0 1 3 0 2 0 /* MDIO */ | |
243 | 0 2 1 0 1 0 /* MDC */ | |
244 | ||
245 | 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ | |
246 | 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ | |
247 | 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ | |
248 | 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ | |
249 | 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ | |
250 | 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ | |
251 | 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ | |
252 | >; | |
253 | }; | |
254 | ||
255 | pio_ucc7: ucc_pin@6 { | |
256 | reg = <6>; | |
257 | ||
258 | pio-map = < | |
259 | /* port pin dir open_drain assignment has_irq */ | |
260 | 0 1 3 0 2 0 /* MDIO */ | |
261 | 0 2 1 0 1 0 /* MDC */ | |
262 | ||
263 | 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ | |
264 | 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ | |
265 | 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ | |
266 | 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ | |
267 | 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ | |
268 | 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ | |
269 | 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ | |
270 | >; | |
271 | }; | |
272 | ||
273 | pio_ucc8: ucc_pin@7 { | |
274 | reg = <7>; | |
275 | ||
276 | pio-map = < | |
277 | /* port pin dir open_drain assignment has_irq */ | |
278 | 0 1 3 0 2 0 /* MDIO */ | |
279 | 0 2 1 0 1 0 /* MDC */ | |
280 | ||
281 | 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ | |
282 | 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ | |
283 | 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ | |
284 | 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ | |
285 | 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ | |
286 | 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ | |
287 | 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ | |
288 | ||
289 | 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ | |
290 | >; | |
291 | }; | |
292 | ||
293 | }; | |
294 | ||
295 | qe@100000 { | |
296 | #address-cells = <1>; | |
297 | #size-cells = <1>; | |
298 | compatible = "fsl,qe"; | |
299 | ranges = <0x0 0x100000 0x100000>; | |
300 | reg = <0x100000 0x480>; | |
301 | clock-frequency = <0>; /* Filled in by U-Boot */ | |
302 | brg-frequency = <0>; /* Filled in by U-Boot */ | |
303 | bus-frequency = <0>; /* Filled in by U-Boot */ | |
304 | ||
305 | muram@10000 { | |
306 | #address-cells = <1>; | |
307 | #size-cells = <1>; | |
308 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; | |
309 | ranges = <0x0 0x00010000 0x0000c000>; | |
310 | ||
311 | data-only@0 { | |
312 | compatible = "fsl,qe-muram-data", | |
313 | "fsl,cpm-muram-data"; | |
314 | reg = <0x0 0xc000>; | |
315 | }; | |
316 | }; | |
317 | ||
318 | /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ | |
319 | enet_estar1: ucc@2000 { | |
320 | device_type = "network"; | |
321 | compatible = "ucc_geth"; | |
322 | cell-index = <1>; | |
323 | reg = <0x2000 0x200>; | |
324 | interrupts = <32>; | |
325 | interrupt-parent = <&qeic>; | |
326 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
327 | rx-clock-name = "none"; | |
328 | tx-clock-name = "clk9"; | |
329 | phy-handle = <&phy_estar1>; | |
330 | phy-connection-type = "rgmii-id"; | |
331 | pio-handle = <&pio_ucc1>; | |
332 | }; | |
333 | ||
334 | /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ | |
335 | enet_estar2: ucc@3000 { | |
336 | device_type = "network"; | |
337 | compatible = "ucc_geth"; | |
338 | cell-index = <2>; | |
339 | reg = <0x3000 0x200>; | |
340 | interrupts = <33>; | |
341 | interrupt-parent = <&qeic>; | |
342 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
343 | rx-clock-name = "none"; | |
344 | tx-clock-name = "clk4"; | |
345 | phy-handle = <&phy_estar2>; | |
346 | phy-connection-type = "rgmii-id"; | |
347 | pio-handle = <&pio_ucc2>; | |
348 | }; | |
349 | ||
350 | /* Piggy2 (UCC4, MDIO 0x00, RMII) */ | |
351 | enet_piggy2: ucc@3200 { | |
352 | device_type = "network"; | |
353 | compatible = "ucc_geth"; | |
354 | cell-index = <4>; | |
355 | reg = <0x3200 0x200>; | |
356 | interrupts = <35>; | |
357 | interrupt-parent = <&qeic>; | |
358 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
359 | rx-clock-name = "none"; | |
360 | tx-clock-name = "clk17"; | |
361 | phy-handle = <&phy_piggy2>; | |
362 | phy-connection-type = "rmii"; | |
363 | pio-handle = <&pio_ucc4>; | |
364 | }; | |
365 | ||
366 | /* Eth-1 (UCC5, MDIO 0x08, RMII) */ | |
367 | enet_eth1: ucc@2400 { | |
368 | device_type = "network"; | |
369 | compatible = "ucc_geth"; | |
370 | cell-index = <5>; | |
371 | reg = <0x2400 0x200>; | |
372 | interrupts = <40>; | |
373 | interrupt-parent = <&qeic>; | |
374 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
375 | rx-clock-name = "none"; | |
376 | tx-clock-name = "clk16"; | |
377 | phy-handle = <&phy_eth1>; | |
378 | phy-connection-type = "rmii"; | |
379 | pio-handle = <&pio_ucc5>; | |
380 | }; | |
381 | ||
382 | /* Eth-2 (UCC6, MDIO 0x09, RMII) */ | |
383 | enet_eth2: ucc@3400 { | |
384 | device_type = "network"; | |
385 | compatible = "ucc_geth"; | |
386 | cell-index = <6>; | |
387 | reg = <0x3400 0x200>; | |
388 | interrupts = <41>; | |
389 | interrupt-parent = <&qeic>; | |
390 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
391 | rx-clock-name = "none"; | |
392 | tx-clock-name = "clk16"; | |
393 | phy-handle = <&phy_eth2>; | |
394 | phy-connection-type = "rmii"; | |
395 | pio-handle = <&pio_ucc6>; | |
396 | }; | |
397 | ||
398 | /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ | |
399 | enet_eth3: ucc@2600 { | |
400 | device_type = "network"; | |
401 | compatible = "ucc_geth"; | |
402 | cell-index = <7>; | |
403 | reg = <0x2600 0x200>; | |
404 | interrupts = <42>; | |
405 | interrupt-parent = <&qeic>; | |
406 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
407 | rx-clock-name = "none"; | |
408 | tx-clock-name = "clk16"; | |
409 | phy-handle = <&phy_eth3>; | |
410 | phy-connection-type = "rmii"; | |
411 | pio-handle = <&pio_ucc7>; | |
412 | }; | |
413 | ||
414 | /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ | |
415 | enet_eth4: ucc@3600 { | |
416 | device_type = "network"; | |
417 | compatible = "ucc_geth"; | |
418 | cell-index = <8>; | |
419 | reg = <0x3600 0x200>; | |
420 | interrupts = <43>; | |
421 | interrupt-parent = <&qeic>; | |
422 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
423 | rx-clock-name = "none"; | |
424 | tx-clock-name = "clk16"; | |
425 | phy-handle = <&phy_eth4>; | |
426 | phy-connection-type = "rmii"; | |
427 | pio-handle = <&pio_ucc8>; | |
428 | }; | |
429 | ||
430 | mdio@3320 { | |
431 | #address-cells = <1>; | |
432 | #size-cells = <0>; | |
433 | reg = <0x3320 0x18>; | |
434 | compatible = "fsl,ucc-mdio"; | |
435 | ||
436 | /* Piggy2 (UCC4, MDIO 0x00, RMII) */ | |
437 | phy_piggy2: ethernet-phy@00 { | |
438 | reg = <0x0>; | |
439 | }; | |
440 | ||
441 | /* Eth-1 (UCC5, MDIO 0x08, RMII) */ | |
442 | phy_eth1: ethernet-phy@08 { | |
443 | reg = <0x08>; | |
444 | }; | |
445 | ||
446 | /* Eth-2 (UCC6, MDIO 0x09, RMII) */ | |
447 | phy_eth2: ethernet-phy@09 { | |
448 | reg = <0x09>; | |
449 | }; | |
450 | ||
451 | /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ | |
452 | phy_eth3: ethernet-phy@0a { | |
453 | reg = <0x0a>; | |
454 | }; | |
455 | ||
456 | /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ | |
457 | phy_eth4: ethernet-phy@0b { | |
458 | reg = <0x0b>; | |
459 | }; | |
460 | ||
461 | /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ | |
462 | phy_estar1: ethernet-phy@10 { | |
463 | interrupt-parent = <&ipic>; | |
464 | interrupts = <17 0x8>; | |
465 | reg = <0x10>; | |
466 | }; | |
467 | ||
468 | /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ | |
469 | phy_estar2: ethernet-phy@11 { | |
470 | interrupt-parent = <&ipic>; | |
471 | interrupts = <18 0x8>; | |
472 | reg = <0x11>; | |
473 | }; | |
474 | }; | |
475 | ||
476 | qeic: interrupt-controller@80 { | |
477 | interrupt-controller; | |
478 | compatible = "fsl,qe-ic"; | |
479 | #address-cells = <0>; | |
480 | #interrupt-cells = <1>; | |
481 | reg = <0x80 0x80>; | |
93e2b95c HB |
482 | big-endian; |
483 | interrupts = < | |
484 | 32 0x8 | |
485 | 33 0x8 | |
486 | 34 0x8 | |
487 | 35 0x8 | |
488 | 40 0x8 | |
489 | 41 0x8 | |
490 | 42 0x8 | |
491 | 43 0x8 | |
492 | >; | |
8159df72 HS |
493 | interrupt-parent = <&ipic>; |
494 | }; | |
495 | }; | |
496 | }; | |
497 | ||
498 | localbus@e0005000 { | |
499 | #address-cells = <2>; | |
500 | #size-cells = <1>; | |
501 | compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", | |
502 | "simple-bus"; | |
503 | reg = <0xe0005000 0xd8>; | |
93e2b95c HB |
504 | ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ |
505 | 1 0 0xe8000000 0x01000000 /* LB 1 */ | |
506 | 3 0 0xa0000000 0x10000000>; /* LB 3 */ | |
8159df72 | 507 | |
93e2b95c | 508 | flash@0,0 { |
8159df72 | 509 | compatible = "cfi-flash"; |
93e2b95c | 510 | reg = <0 0 0x04000000>; |
8159df72 HS |
511 | #address-cells = <1>; |
512 | #size-cells = <1>; | |
93e2b95c HB |
513 | bank-width = <2>; |
514 | partition@0 { /* 768KB */ | |
8159df72 | 515 | label = "u-boot"; |
93e2b95c | 516 | reg = <0 0xC0000>; |
8159df72 | 517 | }; |
93e2b95c | 518 | partition@c0000 { /* 128KB */ |
8159df72 | 519 | label = "env"; |
93e2b95c | 520 | reg = <0xC0000 0x20000>; |
8159df72 | 521 | }; |
93e2b95c HB |
522 | partition@e0000 { /* 128KB */ |
523 | label = "envred"; | |
524 | reg = <0xE0000 0x20000>; | |
8159df72 | 525 | }; |
93e2b95c HB |
526 | partition@100000 { /* 64512KB */ |
527 | label = "ubi0"; | |
528 | reg = <0x100000 0x3F00000>; | |
8159df72 HS |
529 | }; |
530 | }; | |
531 | }; | |
532 | }; |