[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / boot / dts / mpc836x_mds.dts

/*
 * MPC8360E EMDS Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/*
/memreserve/	00000000 1000000;
*/

/dts-v1/;

/ {
	model = "MPC8360MDS";
	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8360@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <66000000>;
			bus-frequency = <264000000>;
			clock-frequency = <528000000>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
			     "simple-bus";
		reg = <0xe0005000 0xd8>;
		ranges = <0 0 0xfe000000 0x02000000
		          1 0 0xf8000000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		bcsr@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
 			compatible = "fsl,mpc8360mds-bcsr";
			reg = <1 0 0x8000>;
			ranges = <0 1 0 0x8000>;

			bcsr13: gpio-controller@d {
				#gpio-cells = <2>;
				compatible = "fsl,mpc8360mds-bcsr-gpio";
				reg = <0xd 1>;
				gpio-controller;
			};
		};
	};

	soc8360@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <264000000>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <264000000>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <264000000>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
			sleep = <&pmc 0x03000000>;
		};

		ipic: pic@700 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		par_io@1400 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1400 0x100>;
			ranges = <0 0x1400 0x100>;
			device_type = "par_io";
			num-ports = <7>;

			qe_pio_b: gpio-controller@18 {
				#gpio-cells = <2>;
				compatible = "fsl,mpc8360-qe-pario-bank",
					     "fsl,mpc8323-qe-pario-bank";
				reg = <0x18 0x18>;
				gpio-controller;
			};

			pio1: ucc_pin@01 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  3  1  0  1  0 	/* TxD0 */
					0  4  1  0  1  0 	/* TxD1 */
					0  5  1  0  1  0 	/* TxD2 */
					0  6  1  0  1  0 	/* TxD3 */
					1  6  1  0  3  0 	/* TxD4 */
					1  7  1  0  1  0 	/* TxD5 */
					1  9  1  0  2  0 	/* TxD6 */
					1  10 1  0  2  0 	/* TxD7 */
					0  9  2  0  1  0 	/* RxD0 */
					0  10 2  0  1  0 	/* RxD1 */
					0  11 2  0  1  0 	/* RxD2 */
					0  12 2  0  1  0 	/* RxD3 */
					0  13 2  0  1  0 	/* RxD4 */
					1  1  2  0  2  0 	/* RxD5 */
					1  0  2  0  2  0 	/* RxD6 */
					1  4  2  0  2  0 	/* RxD7 */
					0  7  1  0  1  0 	/* TX_EN */
					0  8  1  0  1  0 	/* TX_ER */
					0  15 2  0  1  0 	/* RX_DV */
					0  16 2  0  1  0 	/* RX_ER */
					0  0  2  0  1  0 	/* RX_CLK */
					2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
					2  8  2  0  1  0>;	/* GTX125 - CLK9 */
			};
			pio2: ucc_pin@02 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  17 1  0  1  0   /* TxD0 */
					0  18 1  0  1  0   /* TxD1 */
					0  19 1  0  1  0   /* TxD2 */
					0  20 1  0  1  0   /* TxD3 */
					1  2  1  0  1  0   /* TxD4 */
					1  3  1  0  2  0   /* TxD5 */
					1  5  1  0  3  0   /* TxD6 */
					1  8  1  0  3  0   /* TxD7 */
					0  23 2  0  1  0   /* RxD0 */
					0  24 2  0  1  0   /* RxD1 */
					0  25 2  0  1  0   /* RxD2 */
					0  26 2  0  1  0   /* RxD3 */
					0  27 2  0  1  0   /* RxD4 */
					1  12 2  0  2  0   /* RxD5 */
					1  13 2  0  3  0   /* RxD6 */
					1  11 2  0  2  0   /* RxD7 */
					0  21 1  0  1  0   /* TX_EN */
					0  22 1  0  1  0   /* TX_ER */
					0  29 2  0  1  0   /* RX_DV */
					0  30 2  0  1  0   /* RX_ER */
					0  31 2  0  1  0   /* RX_CLK */
					2  2  1  0  2  0   /* GTX_CLK - CLK10 */
					2  3  2  0  1  0   /* GTX125 - CLK4 */
					0  1  3  0  2  0   /* MDIO */
					0  2  1  0  1  0>; /* MDC */
			};

		};
	};

	qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <396000000>;
		fsl,qe-num-riscs = <2>;
		fsl,qe-num-snums = <28>;

		muram@10000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x0000c000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0xc000>;
			};
		};

		timer@440 {
			compatible = "fsl,mpc8360-qe-gtm",
				     "fsl,qe-gtm", "fsl,gtm";
			reg = <0x440 0x40>;
			clock-frequency = <132000000>;
			interrupts = <12 13 14 15>;
			interrupt-parent = <&qeic>;
		};

		spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		spi@500 {
			cell-index = <1>;
			compatible = "fsl,spi";
			reg = <0x500 0x40>;
			interrupts = <1>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		usb@6c0 {
			compatible = "fsl,mpc8360-qe-usb",
				     "fsl,mpc8323-qe-usb";
			reg = <0x6c0 0x40 0x8b00 0x100>;
			interrupts = <11>;
			interrupt-parent = <&qeic>;
			fsl,fullspeed-clock = "clk21";
			fsl,lowspeed-clock = "brg9";
			gpios = <&qe_pio_b  2 0   /* USBOE */
				 &qe_pio_b  3 0   /* USBTP */
				 &qe_pio_b  8 0   /* USBTN */
				 &qe_pio_b  9 0   /* USBRP */
				 &qe_pio_b 11 0   /* USBRN */
				 &bcsr13    5 0   /* SPEED */
				 &bcsr13    4 1>; /* POWER */
		};

		enet0: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <1>;
			reg = <0x2000 0x200>;
			interrupts = <32>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk9";
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio1>;
		};

		enet1: ucc@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <2>;
			reg = <0x3000 0x200>;
			interrupts = <33>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk4";
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio2>;
		};

		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2120 0x18>;
			compatible = "fsl,ucc-mdio";

			phy0: ethernet-phy@00 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@01 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x1>;
			};
			tbi-phy@2 {
				device_type = "tbi-phy";
				reg = <0x2>;
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 0x8 33 0x8>; // high:32 low:33
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 AD17 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 AD18 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 AD19 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 AD21*/
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 AD22*/
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 AD23*/
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 AD24*/
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
		sleep = <&pmc 0x00010000>;
	};
};
Commit	Line	Data
7a234d03 LY	1	/*
	2	* MPC8360E EMDS Device Tree Source
	3	*
	4	* Copyright 2006 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12
	13	/*
	14	/memreserve/ 00000000 1000000;
	15	*/
	16
cda13dd1 PG	17	/dts-v1/;
cda13dd1 PG	18
7a234d03	19	/ {
d71a1dc6 KG	20	model = "MPC8360MDS";
d71a1dc6 KG	21	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
7a234d03 LY	22	#address-cells = <1>;
7a234d03 LY	23	#size-cells = <1>;
7a234d03	24
ea082fa9 KG	25	aliases {
	26	ethernet0 = &enet0;
	27	ethernet1 = &enet1;
	28	serial0 = &serial0;
	29	serial1 = &serial1;
	30	pci0 = &pci0;
	31	};
	32
7a234d03	33	cpus {
7a234d03 LY	34	#address-cells = <1>;
7a234d03 LY	35	#size-cells = <0>;
7a234d03 LY	36
	37	PowerPC,8360@0 {
	38	device_type = "cpu";
cda13dd1 PG	39	reg = <0x0>;
	40	d-cache-line-size = <32>; // 32 bytes
	41	i-cache-line-size = <32>; // 32 bytes
	42	d-cache-size = <32768>; // L1, 32K
	43	i-cache-size = <32768>; // L1, 32K
	44	timebase-frequency = <66000000>;
	45	bus-frequency = <264000000>;
	46	clock-frequency = <528000000>;
7a234d03 LY	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
cda13dd1	52	reg = <0x00000000 0x10000000>;
7a234d03 LY	53	};
7a234d03 LY	54
307db958 AV	55	localbus@e0005000 {
	56	#address-cells = <2>;
	57	#size-cells = <1>;
	58	compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
	59	"simple-bus";
	60	reg = <0xe0005000 0xd8>;
	61	ranges = <0 0 0xfe000000 0x02000000
	62	1 0 0xf8000000 0x00008000>;
	63
	64	flash@0,0 {
	65	compatible = "cfi-flash";
	66	reg = <0 0 0x2000000>;
	67	bank-width = <2>;
	68	device-width = <1>;
	69	};
	70
	71	bcsr@1,0 {
c9c5e52d AV	72	#address-cells = <1>;
c9c5e52d AV	73	#size-cells = <1>;
fd657efc	74	compatible = "fsl,mpc8360mds-bcsr";
307db958	75	reg = <1 0 0x8000>;
c9c5e52d AV	76	ranges = <0 1 0 0x8000>;
	77
	78	bcsr13: gpio-controller@d {
	79	#gpio-cells = <2>;
	80	compatible = "fsl,mpc8360mds-bcsr-gpio";
	81	reg = <0xd 1>;
	82	gpio-controller;
	83	};
307db958	84	};
7a234d03 LY	85	};
	86
	87	soc8360@e0000000 {
	88	#address-cells = <1>;
	89	#size-cells = <1>;
7a234d03	90	device_type = "soc";
cf0d19fb	91	compatible = "simple-bus";
cda13dd1 PG	92	ranges = <0x0 0xe0000000 0x00100000>;
	93	reg = <0xe0000000 0x00000200>;
	94	bus-frequency = <264000000>;
7a234d03 LY	95
	96	wdt@200 {
	97	device_type = "watchdog";
	98	compatible = "mpc83xx_wdt";
cda13dd1	99	reg = <0x200 0x100>;
7a234d03 LY	100	};
7a234d03 LY	101
1f8a25d4 AV	102	pmc: power@b00 {
	103	compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
	104	reg = <0xb00 0x100 0xa00 0x100>;
	105	interrupts = <80 0x8>;
	106	interrupt-parent = <&ipic>;
	107	};
	108
7a234d03	109	i2c@3000 {
27f49807 KP	110	#address-cells = <1>;
27f49807 KP	111	#size-cells = <0>;
ec9686c4	112	cell-index = <0>;
7a234d03	113	compatible = "fsl-i2c";
cda13dd1 PG	114	reg = <0x3000 0x100>;
	115	interrupts = <14 0x8>;
	116	interrupt-parent = <&ipic>;
7a234d03	117	dfsrr;
27f49807 KP	118
	119	rtc@68 {
	120	compatible = "dallas,ds1374";
cda13dd1	121	reg = <0x68>;
27f49807	122	};
7a234d03 LY	123	};
	124
	125	i2c@3100 {
27f49807 KP	126	#address-cells = <1>;
27f49807 KP	127	#size-cells = <0>;
ec9686c4	128	cell-index = <1>;
7a234d03	129	compatible = "fsl-i2c";
cda13dd1 PG	130	reg = <0x3100 0x100>;
	131	interrupts = <15 0x8>;
	132	interrupt-parent = <&ipic>;
7a234d03 LY	133	dfsrr;
	134	};
	135
ea082fa9 KG	136	serial0: serial@4500 {
ea082fa9 KG	137	cell-index = <0>;
7a234d03	138	device_type = "serial";
f706bed1	139	compatible = "fsl,ns16550", "ns16550";
cda13dd1 PG	140	reg = <0x4500 0x100>;
	141	clock-frequency = <264000000>;
	142	interrupts = <9 0x8>;
	143	interrupt-parent = <&ipic>;
7a234d03 LY	144	};
7a234d03 LY	145
ea082fa9 KG	146	serial1: serial@4600 {
ea082fa9 KG	147	cell-index = <1>;
7a234d03	148	device_type = "serial";
f706bed1	149	compatible = "fsl,ns16550", "ns16550";
cda13dd1 PG	150	reg = <0x4600 0x100>;
	151	clock-frequency = <264000000>;
	152	interrupts = <10 0x8>;
	153	interrupt-parent = <&ipic>;
7a234d03 LY	154	};
7a234d03 LY	155
dee80553 KG	156	dma@82a8 {
	157	#address-cells = <1>;
	158	#size-cells = <1>;
	159	compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
	160	reg = <0x82a8 4>;
	161	ranges = <0 0x8100 0x1a8>;
	162	interrupt-parent = <&ipic>;
	163	interrupts = <71 8>;
	164	cell-index = <0>;
	165	dma-channel@0 {
	166	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	167	reg = <0 0x80>;
aeb42762	168	cell-index = <0>;
dee80553 KG	169	interrupt-parent = <&ipic>;
	170	interrupts = <71 8>;
	171	};
	172	dma-channel@80 {
	173	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	174	reg = <0x80 0x80>;
aeb42762	175	cell-index = <1>;
dee80553 KG	176	interrupt-parent = <&ipic>;
	177	interrupts = <71 8>;
	178	};
	179	dma-channel@100 {
	180	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	181	reg = <0x100 0x80>;
aeb42762	182	cell-index = <2>;
dee80553 KG	183	interrupt-parent = <&ipic>;
	184	interrupts = <71 8>;
	185	};
	186	dma-channel@180 {
	187	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	188	reg = <0x180 0x28>;
aeb42762	189	cell-index = <3>;
dee80553 KG	190	interrupt-parent = <&ipic>;
	191	interrupts = <71 8>;
	192	};
	193	};
	194
7a234d03	195	crypto@30000 {
3fd44736	196	compatible = "fsl,sec2.0";
cda13dd1 PG	197	reg = <0x30000 0x10000>;
	198	interrupts = <11 0x8>;
	199	interrupt-parent = <&ipic>;
3fd44736 KP	200	fsl,num-channels = <4>;
	201	fsl,channel-fifo-len = <24>;
	202	fsl,exec-units-mask = <0x7e>;
	203	fsl,descriptor-types-mask = <0x01010ebf>;
1f8a25d4	204	sleep = <&pmc 0x03000000>;
7a234d03 LY	205	};
7a234d03 LY	206
d71a1dc6	207	ipic: pic@700 {
7a234d03 LY	208	interrupt-controller;
	209	#address-cells = <0>;
	210	#interrupt-cells = <2>;
cda13dd1	211	reg = <0x700 0x100>;
7a234d03 LY	212	device_type = "ipic";
	213	};
	214
	215	par_io@1400 {
c9c5e52d AV	216	#address-cells = <1>;
c9c5e52d AV	217	#size-cells = <1>;
cda13dd1	218	reg = <0x1400 0x100>;
c9c5e52d	219	ranges = <0 0x1400 0x100>;
7a234d03 LY	220	device_type = "par_io";
	221	num-ports = <7>;
	222
c9c5e52d AV	223	qe_pio_b: gpio-controller@18 {
	224	#gpio-cells = <2>;
	225	compatible = "fsl,mpc8360-qe-pario-bank",
	226	"fsl,mpc8323-qe-pario-bank";
	227	reg = <0x18 0x18>;
	228	gpio-controller;
	229	};
	230
d71a1dc6	231	pio1: ucc_pin@01 {
7a234d03 LY	232	pio-map = <
	233	/* port pin dir open_drain assignment has_irq */
	234	0 3 1 0 1 0 /* TxD0 */
	235	0 4 1 0 1 0 /* TxD1 */
	236	0 5 1 0 1 0 /* TxD2 */
	237	0 6 1 0 1 0 /* TxD3 */
	238	1 6 1 0 3 0 /* TxD4 */
	239	1 7 1 0 1 0 /* TxD5 */
	240	1 9 1 0 2 0 /* TxD6 */
cda13dd1	241	1 10 1 0 2 0 /* TxD7 */
7a234d03	242	0 9 2 0 1 0 /* RxD0 */
cda13dd1 PG	243	0 10 2 0 1 0 /* RxD1 */
	244	0 11 2 0 1 0 /* RxD2 */
	245	0 12 2 0 1 0 /* RxD3 */
	246	0 13 2 0 1 0 /* RxD4 */
7a234d03 LY	247	1 1 2 0 2 0 /* RxD5 */
	248	1 0 2 0 2 0 /* RxD6 */
	249	1 4 2 0 2 0 /* RxD7 */
	250	0 7 1 0 1 0 /* TX_EN */
	251	0 8 1 0 1 0 /* TX_ER */
cda13dd1 PG	252	0 15 2 0 1 0 /* RX_DV */
cda13dd1 PG	253	0 16 2 0 1 0 /* RX_ER */
7a234d03 LY	254	0 0 2 0 1 0 /* RX_CLK */
	255	2 9 1 0 3 0 /* GTX_CLK - CLK10 */
	256	2 8 2 0 1 0>; /* GTX125 - CLK9 */
	257	};
d71a1dc6	258	pio2: ucc_pin@02 {
7a234d03 LY	259	pio-map = <
7a234d03 LY	260	/* port pin dir open_drain assignment has_irq */
cda13dd1 PG	261	0 17 1 0 1 0 /* TxD0 */
	262	0 18 1 0 1 0 /* TxD1 */
	263	0 19 1 0 1 0 /* TxD2 */
	264	0 20 1 0 1 0 /* TxD3 */
7a234d03 LY	265	1 2 1 0 1 0 /* TxD4 */
	266	1 3 1 0 2 0 /* TxD5 */
	267	1 5 1 0 3 0 /* TxD6 */
	268	1 8 1 0 3 0 /* TxD7 */
cda13dd1 PG	269	0 23 2 0 1 0 /* RxD0 */
	270	0 24 2 0 1 0 /* RxD1 */
	271	0 25 2 0 1 0 /* RxD2 */
	272	0 26 2 0 1 0 /* RxD3 */
	273	0 27 2 0 1 0 /* RxD4 */
	274	1 12 2 0 2 0 /* RxD5 */
	275	1 13 2 0 3 0 /* RxD6 */
	276	1 11 2 0 2 0 /* RxD7 */
	277	0 21 1 0 1 0 /* TX_EN */
	278	0 22 1 0 1 0 /* TX_ER */
	279	0 29 2 0 1 0 /* RX_DV */
	280	0 30 2 0 1 0 /* RX_ER */
	281	0 31 2 0 1 0 /* RX_CLK */
7a234d03 LY	282	2 2 1 0 2 0 /* GTX_CLK - CLK10 */
	283	2 3 2 0 1 0 /* GTX125 - CLK4 */
	284	0 1 3 0 2 0 /* MDIO */
	285	0 2 1 0 1 0>; /* MDC */
	286	};
	287
	288	};
	289	};
	290
	291	qe@e0100000 {
	292	#address-cells = <1>;
	293	#size-cells = <1>;
	294	device_type = "qe";
a2dd70a1	295	compatible = "fsl,qe";
cda13dd1 PG	296	ranges = <0x0 0xe0100000 0x00100000>;
cda13dd1 PG	297	reg = <0xe0100000 0x480>;
7a234d03	298	brg-frequency = <0>;
cda13dd1	299	bus-frequency = <396000000>;
01b14a90 HW	300	fsl,qe-num-riscs = <2>;
01b14a90 HW	301	fsl,qe-num-snums = <28>;
7a234d03 LY	302
7a234d03 LY	303	muram@10000 {
390167ef PG	304	#address-cells = <1>;
390167ef PG	305	#size-cells = <1>;
a2dd70a1	306	compatible = "fsl,qe-muram", "fsl,cpm-muram";
cda13dd1	307	ranges = <0x0 0x00010000 0x0000c000>;
7a234d03	308
390167ef	309	data-only@0 {
a2dd70a1 AV	310	compatible = "fsl,qe-muram-data",
a2dd70a1 AV	311	"fsl,cpm-muram-data";
cda13dd1	312	reg = <0x0 0xc000>;
7a234d03 LY	313	};
	314	};
	315
c9c5e52d AV	316	timer@440 {
	317	compatible = "fsl,mpc8360-qe-gtm",
	318	"fsl,qe-gtm", "fsl,gtm";
	319	reg = <0x440 0x40>;
	320	clock-frequency = <132000000>;
	321	interrupts = <12 13 14 15>;
	322	interrupt-parent = <&qeic>;
	323	};
	324
7a234d03	325	spi@4c0 {
f3a2b29d AV	326	cell-index = <0>;
f3a2b29d AV	327	compatible = "fsl,spi";
cda13dd1	328	reg = <0x4c0 0x40>;
7a234d03	329	interrupts = <2>;
cda13dd1	330	interrupt-parent = <&qeic>;
7a234d03 LY	331	mode = "cpu";
	332	};
	333
	334	spi@500 {
f3a2b29d AV	335	cell-index = <1>;
f3a2b29d AV	336	compatible = "fsl,spi";
cda13dd1	337	reg = <0x500 0x40>;
7a234d03	338	interrupts = <1>;
cda13dd1	339	interrupt-parent = <&qeic>;
7a234d03 LY	340	mode = "cpu";
	341	};
	342
	343	usb@6c0 {
c9c5e52d AV	344	compatible = "fsl,mpc8360-qe-usb",
c9c5e52d AV	345	"fsl,mpc8323-qe-usb";
cda13dd1 PG	346	reg = <0x6c0 0x40 0x8b00 0x100>;
	347	interrupts = <11>;
	348	interrupt-parent = <&qeic>;
c9c5e52d AV	349	fsl,fullspeed-clock = "clk21";
	350	fsl,lowspeed-clock = "brg9";
	351	gpios = <&qe_pio_b 2 0 /* USBOE */
	352	&qe_pio_b 3 0 /* USBTP */
	353	&qe_pio_b 8 0 /* USBTN */
	354	&qe_pio_b 9 0 /* USBRP */
	355	&qe_pio_b 11 0 /* USBRN */
	356	&bcsr13 5 0 /* SPEED */
	357	&bcsr13 4 1>; /* POWER */
7a234d03 LY	358	};
7a234d03 LY	359
e77b28eb	360	enet0: ucc@2000 {
7a234d03 LY	361	device_type = "network";
7a234d03 LY	362	compatible = "ucc_geth";
e77b28eb	363	cell-index = <1>;
cda13dd1 PG	364	reg = <0x2000 0x200>;
	365	interrupts = <32>;
	366	interrupt-parent = <&qeic>;
eae98266	367	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	368	rx-clock-name = "none";
9fb1e350 TT	369	tx-clock-name = "clk9";
cda13dd1	370	phy-handle = <&phy0>;
0fd8c47c	371	phy-connection-type = "rgmii-id";
cda13dd1	372	pio-handle = <&pio1>;
7a234d03 LY	373	};
7a234d03 LY	374
e77b28eb	375	enet1: ucc@3000 {
7a234d03 LY	376	device_type = "network";
7a234d03 LY	377	compatible = "ucc_geth";
e77b28eb	378	cell-index = <2>;
cda13dd1 PG	379	reg = <0x3000 0x200>;
	380	interrupts = <33>;
	381	interrupt-parent = <&qeic>;
eae98266	382	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	383	rx-clock-name = "none";
9fb1e350 TT	384	tx-clock-name = "clk4";
cda13dd1	385	phy-handle = <&phy1>;
0fd8c47c	386	phy-connection-type = "rgmii-id";
cda13dd1	387	pio-handle = <&pio2>;
7a234d03 LY	388	};
	389
	390	mdio@2120 {
	391	#address-cells = <1>;
	392	#size-cells = <0>;
cda13dd1	393	reg = <0x2120 0x18>;
d0a2f82d	394	compatible = "fsl,ucc-mdio";
7a234d03	395
d71a1dc6	396	phy0: ethernet-phy@00 {
cda13dd1 PG	397	interrupt-parent = <&ipic>;
	398	interrupts = <17 0x8>;
	399	reg = <0x0>;
7a234d03	400	};
d71a1dc6	401	phy1: ethernet-phy@01 {
cda13dd1 PG	402	interrupt-parent = <&ipic>;
	403	interrupts = <18 0x8>;
	404	reg = <0x1>;
7a234d03	405	};
1ee4af86 PG	406	tbi-phy@2 {
	407	device_type = "tbi-phy";
	408	reg = <0x2>;
	409	};
7a234d03 LY	410	};
7a234d03 LY	411
a2dd70a1	412	qeic: interrupt-controller@80 {
7a234d03	413	interrupt-controller;
a2dd70a1	414	compatible = "fsl,qe-ic";
7a234d03 LY	415	#address-cells = <0>;
7a234d03 LY	416	#interrupt-cells = <1>;
cda13dd1	417	reg = <0x80 0x80>;
7a234d03	418	big-endian;
cda13dd1 PG	419	interrupts = <32 0x8 33 0x8>; // high:32 low:33
cda13dd1 PG	420	interrupt-parent = <&ipic>;
7a234d03	421	};
1b3c5cda	422	};
7a234d03	423
ea082fa9	424	pci0: pci@e0008500 {
cda13dd1	425	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	426	interrupt-map = <
	427
	428	/* IDSEL 0x11 AD17 */
cda13dd1 PG	429	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	430	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	431	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	432	0x8800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	433
1b3c5cda KG	434	/* IDSEL 0x12 AD18 */
cda13dd1 PG	435	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	436	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	437	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	438	0x9000 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	439
1b3c5cda KG	440	/* IDSEL 0x13 AD19 */
cda13dd1 PG	441	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	442	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	443	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	444	0x9800 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	445
1b3c5cda KG	446	/* IDSEL 0x15 AD21*/
cda13dd1 PG	447	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	448	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	449	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	450	0xa800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	451
1b3c5cda KG	452	/* IDSEL 0x16 AD22*/
cda13dd1 PG	453	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	454	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	455	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	456	0xb000 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	457
1b3c5cda KG	458	/* IDSEL 0x17 AD23*/
cda13dd1 PG	459	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	460	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	461	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	462	0xb800 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	463
1b3c5cda KG	464	/* IDSEL 0x18 AD24*/
cda13dd1 PG	465	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	466	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	467	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	468	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	469	interrupt-parent = <&ipic>;
	470	interrupts = <66 0x8>;
1b3c5cda	471	bus-range = <0 0>;
cda13dd1 PG	472	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	473	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	474	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	475	clock-frequency = <66666666>;
1b3c5cda KG	476	#interrupt-cells = <1>;
	477	#size-cells = <2>;
	478	#address-cells = <3>;
5b70a097 JR	479	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	480	0xe0008300 0x8>; /* config space access registers */
1b3c5cda KG	481	compatible = "fsl,mpc8349-pci";
1b3c5cda KG	482	device_type = "pci";
1f8a25d4	483	sleep = <&pmc 0x00010000>;
7a234d03 LY	484	};
7a234d03 LY	485	};