[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / boot / dts / mpc836x_mds.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8360E EMDS Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 */


/*
/memreserve/	00000000 1000000;
*/

/dts-v1/;

/ {
	model = "MPC8360MDS";
	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8360@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <66000000>;
			bus-frequency = <264000000>;
			clock-frequency = <528000000>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
			     "simple-bus";
		reg = <0xe0005000 0xd8>;
		ranges = <0 0 0xfe000000 0x02000000
		          1 0 0xf8000000 0x00008000>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		bcsr@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
 			compatible = "fsl,mpc8360mds-bcsr";
			reg = <1 0 0x8000>;
			ranges = <0 1 0 0x8000>;

			bcsr13: gpio-controller@d {
				#gpio-cells = <2>;
				compatible = "fsl,mpc8360mds-bcsr-gpio";
				reg = <0xd 1>;
				gpio-controller;
			};
		};
	};

	soc8360@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <264000000>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <264000000>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <264000000>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
			sleep = <&pmc 0x03000000>;
		};

		ipic: pic@700 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		par_io@1400 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1400 0x100>;
			ranges = <0 0x1400 0x100>;
			device_type = "par_io";
			num-ports = <7>;

			qe_pio_b: gpio-controller@18 {
				#gpio-cells = <2>;
				compatible = "fsl,mpc8360-qe-pario-bank",
					     "fsl,mpc8323-qe-pario-bank";
				reg = <0x18 0x18>;
				gpio-controller;
			};

			pio1: ucc_pin@1 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  3  1  0  1  0 	/* TxD0 */
					0  4  1  0  1  0 	/* TxD1 */
					0  5  1  0  1  0 	/* TxD2 */
					0  6  1  0  1  0 	/* TxD3 */
					1  6  1  0  3  0 	/* TxD4 */
					1  7  1  0  1  0 	/* TxD5 */
					1  9  1  0  2  0 	/* TxD6 */
					1  10 1  0  2  0 	/* TxD7 */
					0  9  2  0  1  0 	/* RxD0 */
					0  10 2  0  1  0 	/* RxD1 */
					0  11 2  0  1  0 	/* RxD2 */
					0  12 2  0  1  0 	/* RxD3 */
					0  13 2  0  1  0 	/* RxD4 */
					1  1  2  0  2  0 	/* RxD5 */
					1  0  2  0  2  0 	/* RxD6 */
					1  4  2  0  2  0 	/* RxD7 */
					0  7  1  0  1  0 	/* TX_EN */
					0  8  1  0  1  0 	/* TX_ER */
					0  15 2  0  1  0 	/* RX_DV */
					0  16 2  0  1  0 	/* RX_ER */
					0  0  2  0  1  0 	/* RX_CLK */
					2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
					2  8  2  0  1  0>;	/* GTX125 - CLK9 */
			};
			pio2: ucc_pin@2 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  17 1  0  1  0   /* TxD0 */
					0  18 1  0  1  0   /* TxD1 */
					0  19 1  0  1  0   /* TxD2 */
					0  20 1  0  1  0   /* TxD3 */
					1  2  1  0  1  0   /* TxD4 */
					1  3  1  0  2  0   /* TxD5 */
					1  5  1  0  3  0   /* TxD6 */
					1  8  1  0  3  0   /* TxD7 */
					0  23 2  0  1  0   /* RxD0 */
					0  24 2  0  1  0   /* RxD1 */
					0  25 2  0  1  0   /* RxD2 */
					0  26 2  0  1  0   /* RxD3 */
					0  27 2  0  1  0   /* RxD4 */
					1  12 2  0  2  0   /* RxD5 */
					1  13 2  0  3  0   /* RxD6 */
					1  11 2  0  2  0   /* RxD7 */
					0  21 1  0  1  0   /* TX_EN */
					0  22 1  0  1  0   /* TX_ER */
					0  29 2  0  1  0   /* RX_DV */
					0  30 2  0  1  0   /* RX_ER */
					0  31 2  0  1  0   /* RX_CLK */
					2  2  1  0  2  0   /* GTX_CLK - CLK10 */
					2  3  2  0  1  0   /* GTX125 - CLK4 */
					0  1  3  0  2  0   /* MDIO */
					0  2  1  0  1  0>; /* MDC */
			};

		};
	};

	qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <396000000>;
		fsl,qe-num-riscs = <2>;
		fsl,qe-num-snums = <28>;

		muram@10000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x0000c000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0xc000>;
			};
		};

		timer@440 {
			compatible = "fsl,mpc8360-qe-gtm",
				     "fsl,qe-gtm", "fsl,gtm";
			reg = <0x440 0x40>;
			clock-frequency = <132000000>;
			interrupts = <12 13 14 15>;
			interrupt-parent = <&qeic>;
		};

		spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		spi@500 {
			cell-index = <1>;
			compatible = "fsl,spi";
			reg = <0x500 0x40>;
			interrupts = <1>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		usb@6c0 {
			compatible = "fsl,mpc8360-qe-usb",
				     "fsl,mpc8323-qe-usb";
			reg = <0x6c0 0x40 0x8b00 0x100>;
			interrupts = <11>;
			interrupt-parent = <&qeic>;
			fsl,fullspeed-clock = "clk21";
			fsl,lowspeed-clock = "brg9";
			gpios = <&qe_pio_b  2 0   /* USBOE */
				 &qe_pio_b  3 0   /* USBTP */
				 &qe_pio_b  8 0   /* USBTN */
				 &qe_pio_b  9 0   /* USBRP */
				 &qe_pio_b 11 0   /* USBRN */
				 &bcsr13    5 0   /* SPEED */
				 &bcsr13    4 1>; /* POWER */
		};

		enet0: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <1>;
			reg = <0x2000 0x200>;
			interrupts = <32>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk9";
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio1>;
		};

		enet1: ucc@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <2>;
			reg = <0x3000 0x200>;
			interrupts = <33>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk4";
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio2>;
		};

		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2120 0x18>;
			compatible = "fsl,ucc-mdio";

			phy0: ethernet-phy@0 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x1>;
			};
			tbi-phy@2 {
				device_type = "tbi-phy";
				reg = <0x2>;
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 0x8 33 0x8>; // high:32 low:33
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 AD17 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 AD18 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 AD19 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 AD21*/
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 AD22*/
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 AD23*/
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 AD24*/
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
		sleep = <&pmc 0x00010000>;
	};
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
7a234d03 LY	2	/*
	3	* MPC8360E EMDS Device Tree Source
	4	*
	5	* Copyright 2006 Freescale Semiconductor Inc.
7a234d03 LY	6	*/
	7
	8
	9	/*
	10	/memreserve/ 00000000 1000000;
	11	*/
	12
cda13dd1 PG	13	/dts-v1/;
cda13dd1 PG	14
7a234d03	15	/ {
d71a1dc6 KG	16	model = "MPC8360MDS";
d71a1dc6 KG	17	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
7a234d03 LY	18	#address-cells = <1>;
7a234d03 LY	19	#size-cells = <1>;
7a234d03	20
ea082fa9 KG	21	aliases {
	22	ethernet0 = &enet0;
	23	ethernet1 = &enet1;
	24	serial0 = &serial0;
	25	serial1 = &serial1;
	26	pci0 = &pci0;
	27	};
	28
7a234d03	29	cpus {
7a234d03 LY	30	#address-cells = <1>;
7a234d03 LY	31	#size-cells = <0>;
7a234d03 LY	32
	33	PowerPC,8360@0 {
	34	device_type = "cpu";
cda13dd1 PG	35	reg = <0x0>;
	36	d-cache-line-size = <32>; // 32 bytes
	37	i-cache-line-size = <32>; // 32 bytes
	38	d-cache-size = <32768>; // L1, 32K
	39	i-cache-size = <32768>; // L1, 32K
	40	timebase-frequency = <66000000>;
	41	bus-frequency = <264000000>;
	42	clock-frequency = <528000000>;
7a234d03 LY	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
cda13dd1	48	reg = <0x00000000 0x10000000>;
7a234d03 LY	49	};
7a234d03 LY	50
307db958 AV	51	localbus@e0005000 {
	52	#address-cells = <2>;
	53	#size-cells = <1>;
	54	compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
	55	"simple-bus";
	56	reg = <0xe0005000 0xd8>;
	57	ranges = <0 0 0xfe000000 0x02000000
	58	1 0 0xf8000000 0x00008000>;
	59
	60	flash@0,0 {
	61	compatible = "cfi-flash";
	62	reg = <0 0 0x2000000>;
	63	bank-width = <2>;
	64	device-width = <1>;
	65	};
	66
	67	bcsr@1,0 {
c9c5e52d AV	68	#address-cells = <1>;
c9c5e52d AV	69	#size-cells = <1>;
fd657efc	70	compatible = "fsl,mpc8360mds-bcsr";
307db958	71	reg = <1 0 0x8000>;
c9c5e52d AV	72	ranges = <0 1 0 0x8000>;
	73
	74	bcsr13: gpio-controller@d {
	75	#gpio-cells = <2>;
	76	compatible = "fsl,mpc8360mds-bcsr-gpio";
	77	reg = <0xd 1>;
	78	gpio-controller;
	79	};
307db958	80	};
7a234d03 LY	81	};
	82
	83	soc8360@e0000000 {
	84	#address-cells = <1>;
	85	#size-cells = <1>;
7a234d03	86	device_type = "soc";
cf0d19fb	87	compatible = "simple-bus";
cda13dd1 PG	88	ranges = <0x0 0xe0000000 0x00100000>;
	89	reg = <0xe0000000 0x00000200>;
	90	bus-frequency = <264000000>;
7a234d03 LY	91
	92	wdt@200 {
	93	device_type = "watchdog";
	94	compatible = "mpc83xx_wdt";
cda13dd1	95	reg = <0x200 0x100>;
7a234d03 LY	96	};
7a234d03 LY	97
1f8a25d4 AV	98	pmc: power@b00 {
	99	compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
	100	reg = <0xb00 0x100 0xa00 0x100>;
	101	interrupts = <80 0x8>;
	102	interrupt-parent = <&ipic>;
	103	};
	104
7a234d03	105	i2c@3000 {
27f49807 KP	106	#address-cells = <1>;
27f49807 KP	107	#size-cells = <0>;
ec9686c4	108	cell-index = <0>;
7a234d03	109	compatible = "fsl-i2c";
cda13dd1 PG	110	reg = <0x3000 0x100>;
	111	interrupts = <14 0x8>;
	112	interrupt-parent = <&ipic>;
7a234d03	113	dfsrr;
27f49807 KP	114
	115	rtc@68 {
	116	compatible = "dallas,ds1374";
cda13dd1	117	reg = <0x68>;
27f49807	118	};
7a234d03 LY	119	};
	120
	121	i2c@3100 {
27f49807 KP	122	#address-cells = <1>;
27f49807 KP	123	#size-cells = <0>;
ec9686c4	124	cell-index = <1>;
7a234d03	125	compatible = "fsl-i2c";
cda13dd1 PG	126	reg = <0x3100 0x100>;
	127	interrupts = <15 0x8>;
	128	interrupt-parent = <&ipic>;
7a234d03 LY	129	dfsrr;
	130	};
	131
ea082fa9 KG	132	serial0: serial@4500 {
ea082fa9 KG	133	cell-index = <0>;
7a234d03	134	device_type = "serial";
f706bed1	135	compatible = "fsl,ns16550", "ns16550";
cda13dd1 PG	136	reg = <0x4500 0x100>;
	137	clock-frequency = <264000000>;
	138	interrupts = <9 0x8>;
	139	interrupt-parent = <&ipic>;
7a234d03 LY	140	};
7a234d03 LY	141
ea082fa9 KG	142	serial1: serial@4600 {
ea082fa9 KG	143	cell-index = <1>;
7a234d03	144	device_type = "serial";
f706bed1	145	compatible = "fsl,ns16550", "ns16550";
cda13dd1 PG	146	reg = <0x4600 0x100>;
	147	clock-frequency = <264000000>;
	148	interrupts = <10 0x8>;
	149	interrupt-parent = <&ipic>;
7a234d03 LY	150	};
7a234d03 LY	151
dee80553 KG	152	dma@82a8 {
	153	#address-cells = <1>;
	154	#size-cells = <1>;
	155	compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
	156	reg = <0x82a8 4>;
	157	ranges = <0 0x8100 0x1a8>;
	158	interrupt-parent = <&ipic>;
	159	interrupts = <71 8>;
	160	cell-index = <0>;
	161	dma-channel@0 {
	162	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	163	reg = <0 0x80>;
aeb42762	164	cell-index = <0>;
dee80553 KG	165	interrupt-parent = <&ipic>;
	166	interrupts = <71 8>;
	167	};
	168	dma-channel@80 {
	169	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	170	reg = <0x80 0x80>;
aeb42762	171	cell-index = <1>;
dee80553 KG	172	interrupt-parent = <&ipic>;
	173	interrupts = <71 8>;
	174	};
	175	dma-channel@100 {
	176	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	177	reg = <0x100 0x80>;
aeb42762	178	cell-index = <2>;
dee80553 KG	179	interrupt-parent = <&ipic>;
	180	interrupts = <71 8>;
	181	};
	182	dma-channel@180 {
	183	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	184	reg = <0x180 0x28>;
aeb42762	185	cell-index = <3>;
dee80553 KG	186	interrupt-parent = <&ipic>;
	187	interrupts = <71 8>;
	188	};
	189	};
	190
7a234d03	191	crypto@30000 {
3fd44736	192	compatible = "fsl,sec2.0";
cda13dd1 PG	193	reg = <0x30000 0x10000>;
	194	interrupts = <11 0x8>;
	195	interrupt-parent = <&ipic>;
3fd44736 KP	196	fsl,num-channels = <4>;
	197	fsl,channel-fifo-len = <24>;
	198	fsl,exec-units-mask = <0x7e>;
	199	fsl,descriptor-types-mask = <0x01010ebf>;
1f8a25d4	200	sleep = <&pmc 0x03000000>;
7a234d03 LY	201	};
7a234d03 LY	202
d71a1dc6	203	ipic: pic@700 {
7a234d03 LY	204	interrupt-controller;
	205	#address-cells = <0>;
	206	#interrupt-cells = <2>;
cda13dd1	207	reg = <0x700 0x100>;
7a234d03 LY	208	device_type = "ipic";
	209	};
	210
	211	par_io@1400 {
c9c5e52d AV	212	#address-cells = <1>;
c9c5e52d AV	213	#size-cells = <1>;
cda13dd1	214	reg = <0x1400 0x100>;
c9c5e52d	215	ranges = <0 0x1400 0x100>;
7a234d03 LY	216	device_type = "par_io";
	217	num-ports = <7>;
	218
c9c5e52d AV	219	qe_pio_b: gpio-controller@18 {
	220	#gpio-cells = <2>;
	221	compatible = "fsl,mpc8360-qe-pario-bank",
	222	"fsl,mpc8323-qe-pario-bank";
	223	reg = <0x18 0x18>;
	224	gpio-controller;
	225	};
	226
600ecc19	227	pio1: ucc_pin@1 {
7a234d03 LY	228	pio-map = <
	229	/* port pin dir open_drain assignment has_irq */
	230	0 3 1 0 1 0 /* TxD0 */
	231	0 4 1 0 1 0 /* TxD1 */
	232	0 5 1 0 1 0 /* TxD2 */
	233	0 6 1 0 1 0 /* TxD3 */
	234	1 6 1 0 3 0 /* TxD4 */
	235	1 7 1 0 1 0 /* TxD5 */
	236	1 9 1 0 2 0 /* TxD6 */
cda13dd1	237	1 10 1 0 2 0 /* TxD7 */
7a234d03	238	0 9 2 0 1 0 /* RxD0 */
cda13dd1 PG	239	0 10 2 0 1 0 /* RxD1 */
	240	0 11 2 0 1 0 /* RxD2 */
	241	0 12 2 0 1 0 /* RxD3 */
	242	0 13 2 0 1 0 /* RxD4 */
7a234d03 LY	243	1 1 2 0 2 0 /* RxD5 */
	244	1 0 2 0 2 0 /* RxD6 */
	245	1 4 2 0 2 0 /* RxD7 */
	246	0 7 1 0 1 0 /* TX_EN */
	247	0 8 1 0 1 0 /* TX_ER */
cda13dd1 PG	248	0 15 2 0 1 0 /* RX_DV */
cda13dd1 PG	249	0 16 2 0 1 0 /* RX_ER */
7a234d03 LY	250	0 0 2 0 1 0 /* RX_CLK */
	251	2 9 1 0 3 0 /* GTX_CLK - CLK10 */
	252	2 8 2 0 1 0>; /* GTX125 - CLK9 */
	253	};
600ecc19	254	pio2: ucc_pin@2 {
7a234d03 LY	255	pio-map = <
7a234d03 LY	256	/* port pin dir open_drain assignment has_irq */
cda13dd1 PG	257	0 17 1 0 1 0 /* TxD0 */
	258	0 18 1 0 1 0 /* TxD1 */
	259	0 19 1 0 1 0 /* TxD2 */
	260	0 20 1 0 1 0 /* TxD3 */
7a234d03 LY	261	1 2 1 0 1 0 /* TxD4 */
	262	1 3 1 0 2 0 /* TxD5 */
	263	1 5 1 0 3 0 /* TxD6 */
	264	1 8 1 0 3 0 /* TxD7 */
cda13dd1 PG	265	0 23 2 0 1 0 /* RxD0 */
	266	0 24 2 0 1 0 /* RxD1 */
	267	0 25 2 0 1 0 /* RxD2 */
	268	0 26 2 0 1 0 /* RxD3 */
	269	0 27 2 0 1 0 /* RxD4 */
	270	1 12 2 0 2 0 /* RxD5 */
	271	1 13 2 0 3 0 /* RxD6 */
	272	1 11 2 0 2 0 /* RxD7 */
	273	0 21 1 0 1 0 /* TX_EN */
	274	0 22 1 0 1 0 /* TX_ER */
	275	0 29 2 0 1 0 /* RX_DV */
	276	0 30 2 0 1 0 /* RX_ER */
	277	0 31 2 0 1 0 /* RX_CLK */
7a234d03 LY	278	2 2 1 0 2 0 /* GTX_CLK - CLK10 */
	279	2 3 2 0 1 0 /* GTX125 - CLK4 */
	280	0 1 3 0 2 0 /* MDIO */
	281	0 2 1 0 1 0>; /* MDC */
	282	};
	283
	284	};
	285	};
	286
	287	qe@e0100000 {
	288	#address-cells = <1>;
	289	#size-cells = <1>;
	290	device_type = "qe";
a2dd70a1	291	compatible = "fsl,qe";
cda13dd1 PG	292	ranges = <0x0 0xe0100000 0x00100000>;
cda13dd1 PG	293	reg = <0xe0100000 0x480>;
7a234d03	294	brg-frequency = <0>;
cda13dd1	295	bus-frequency = <396000000>;
01b14a90 HW	296	fsl,qe-num-riscs = <2>;
01b14a90 HW	297	fsl,qe-num-snums = <28>;
7a234d03 LY	298
7a234d03 LY	299	muram@10000 {
390167ef PG	300	#address-cells = <1>;
390167ef PG	301	#size-cells = <1>;
a2dd70a1	302	compatible = "fsl,qe-muram", "fsl,cpm-muram";
cda13dd1	303	ranges = <0x0 0x00010000 0x0000c000>;
7a234d03	304
390167ef	305	data-only@0 {
a2dd70a1 AV	306	compatible = "fsl,qe-muram-data",
a2dd70a1 AV	307	"fsl,cpm-muram-data";
cda13dd1	308	reg = <0x0 0xc000>;
7a234d03 LY	309	};
	310	};
	311
c9c5e52d AV	312	timer@440 {
	313	compatible = "fsl,mpc8360-qe-gtm",
	314	"fsl,qe-gtm", "fsl,gtm";
	315	reg = <0x440 0x40>;
	316	clock-frequency = <132000000>;
	317	interrupts = <12 13 14 15>;
	318	interrupt-parent = <&qeic>;
	319	};
	320
7a234d03	321	spi@4c0 {
f3a2b29d AV	322	cell-index = <0>;
f3a2b29d AV	323	compatible = "fsl,spi";
cda13dd1	324	reg = <0x4c0 0x40>;
7a234d03	325	interrupts = <2>;
cda13dd1	326	interrupt-parent = <&qeic>;
7a234d03 LY	327	mode = "cpu";
	328	};
	329
	330	spi@500 {
f3a2b29d AV	331	cell-index = <1>;
f3a2b29d AV	332	compatible = "fsl,spi";
cda13dd1	333	reg = <0x500 0x40>;
7a234d03	334	interrupts = <1>;
cda13dd1	335	interrupt-parent = <&qeic>;
7a234d03 LY	336	mode = "cpu";
	337	};
	338
	339	usb@6c0 {
c9c5e52d AV	340	compatible = "fsl,mpc8360-qe-usb",
c9c5e52d AV	341	"fsl,mpc8323-qe-usb";
cda13dd1 PG	342	reg = <0x6c0 0x40 0x8b00 0x100>;
	343	interrupts = <11>;
	344	interrupt-parent = <&qeic>;
c9c5e52d AV	345	fsl,fullspeed-clock = "clk21";
	346	fsl,lowspeed-clock = "brg9";
	347	gpios = <&qe_pio_b 2 0 /* USBOE */
	348	&qe_pio_b 3 0 /* USBTP */
	349	&qe_pio_b 8 0 /* USBTN */
	350	&qe_pio_b 9 0 /* USBRP */
	351	&qe_pio_b 11 0 /* USBRN */
	352	&bcsr13 5 0 /* SPEED */
	353	&bcsr13 4 1>; /* POWER */
7a234d03 LY	354	};
7a234d03 LY	355
e77b28eb	356	enet0: ucc@2000 {
7a234d03 LY	357	device_type = "network";
7a234d03 LY	358	compatible = "ucc_geth";
e77b28eb	359	cell-index = <1>;
cda13dd1 PG	360	reg = <0x2000 0x200>;
	361	interrupts = <32>;
	362	interrupt-parent = <&qeic>;
eae98266	363	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	364	rx-clock-name = "none";
9fb1e350 TT	365	tx-clock-name = "clk9";
cda13dd1	366	phy-handle = <&phy0>;
0fd8c47c	367	phy-connection-type = "rgmii-id";
cda13dd1	368	pio-handle = <&pio1>;
7a234d03 LY	369	};
7a234d03 LY	370
e77b28eb	371	enet1: ucc@3000 {
7a234d03 LY	372	device_type = "network";
7a234d03 LY	373	compatible = "ucc_geth";
e77b28eb	374	cell-index = <2>;
cda13dd1 PG	375	reg = <0x3000 0x200>;
	376	interrupts = <33>;
	377	interrupt-parent = <&qeic>;
eae98266	378	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	379	rx-clock-name = "none";
9fb1e350 TT	380	tx-clock-name = "clk4";
cda13dd1	381	phy-handle = <&phy1>;
0fd8c47c	382	phy-connection-type = "rgmii-id";
cda13dd1	383	pio-handle = <&pio2>;
7a234d03 LY	384	};
	385
	386	mdio@2120 {
	387	#address-cells = <1>;
	388	#size-cells = <0>;
cda13dd1	389	reg = <0x2120 0x18>;
d0a2f82d	390	compatible = "fsl,ucc-mdio";
7a234d03	391
600ecc19	392	phy0: ethernet-phy@0 {
cda13dd1 PG	393	interrupt-parent = <&ipic>;
	394	interrupts = <17 0x8>;
	395	reg = <0x0>;
7a234d03	396	};
600ecc19	397	phy1: ethernet-phy@1 {
cda13dd1 PG	398	interrupt-parent = <&ipic>;
	399	interrupts = <18 0x8>;
	400	reg = <0x1>;
7a234d03	401	};
1ee4af86 PG	402	tbi-phy@2 {
	403	device_type = "tbi-phy";
	404	reg = <0x2>;
	405	};
7a234d03 LY	406	};
7a234d03 LY	407
a2dd70a1	408	qeic: interrupt-controller@80 {
7a234d03	409	interrupt-controller;
a2dd70a1	410	compatible = "fsl,qe-ic";
7a234d03 LY	411	#address-cells = <0>;
7a234d03 LY	412	#interrupt-cells = <1>;
cda13dd1	413	reg = <0x80 0x80>;
7a234d03	414	big-endian;
cda13dd1 PG	415	interrupts = <32 0x8 33 0x8>; // high:32 low:33
cda13dd1 PG	416	interrupt-parent = <&ipic>;
7a234d03	417	};
1b3c5cda	418	};
7a234d03	419
ea082fa9	420	pci0: pci@e0008500 {
cda13dd1	421	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	422	interrupt-map = <
	423
	424	/* IDSEL 0x11 AD17 */
cda13dd1 PG	425	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	426	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	427	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	428	0x8800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	429
1b3c5cda KG	430	/* IDSEL 0x12 AD18 */
cda13dd1 PG	431	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	432	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	433	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	434	0x9000 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	435
1b3c5cda KG	436	/* IDSEL 0x13 AD19 */
cda13dd1 PG	437	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	438	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	439	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	440	0x9800 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	441
1b3c5cda KG	442	/* IDSEL 0x15 AD21*/
cda13dd1 PG	443	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	444	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	445	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	446	0xa800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	447
1b3c5cda KG	448	/* IDSEL 0x16 AD22*/
cda13dd1 PG	449	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	450	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	451	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	452	0xb000 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	453
1b3c5cda KG	454	/* IDSEL 0x17 AD23*/
cda13dd1 PG	455	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	456	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	457	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	458	0xb800 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	459
1b3c5cda KG	460	/* IDSEL 0x18 AD24*/
cda13dd1 PG	461	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	462	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	463	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	464	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	465	interrupt-parent = <&ipic>;
	466	interrupts = <66 0x8>;
1b3c5cda	467	bus-range = <0 0>;
cda13dd1 PG	468	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	469	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	470	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	471	clock-frequency = <66666666>;
1b3c5cda KG	472	#interrupt-cells = <1>;
	473	#size-cells = <2>;
	474	#address-cells = <3>;
5b70a097 JR	475	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	476	0xe0008300 0x8>; /* config space access registers */
1b3c5cda KG	477	compatible = "fsl,mpc8349-pci";
1b3c5cda KG	478	device_type = "pci";
1f8a25d4	479	sleep = <&pmc 0x00010000>;
7a234d03 LY	480	};
7a234d03 LY	481	};