[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / boot / dts / mpc836x_mds.dts

/*
 * MPC8360E EMDS Device Tree Source
 *
 * Copyright 2006 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */


/*
/memreserve/	00000000 1000000;
*/

/dts-v1/;

/ {
	model = "MPC8360MDS";
	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8360@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <32768>;		// L1, 32K
			i-cache-size = <32768>;		// L1, 32K
			timebase-frequency = <66000000>;
			bus-frequency = <264000000>;
			clock-frequency = <528000000>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;
	};

	bcsr@f8000000 {
		device_type = "board-control";
		reg = <0xf8000000 0x8000>;
	};

	soc8360@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <264000000>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <264000000>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <264000000>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
		};

		ipic: pic@700 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
			device_type = "ipic";
		};

		par_io@1400 {
			reg = <0x1400 0x100>;
			device_type = "par_io";
			num-ports = <7>;

			pio1: ucc_pin@01 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  3  1  0  1  0 	/* TxD0 */
					0  4  1  0  1  0 	/* TxD1 */
					0  5  1  0  1  0 	/* TxD2 */
					0  6  1  0  1  0 	/* TxD3 */
					1  6  1  0  3  0 	/* TxD4 */
					1  7  1  0  1  0 	/* TxD5 */
					1  9  1  0  2  0 	/* TxD6 */
					1  10 1  0  2  0 	/* TxD7 */
					0  9  2  0  1  0 	/* RxD0 */
					0  10 2  0  1  0 	/* RxD1 */
					0  11 2  0  1  0 	/* RxD2 */
					0  12 2  0  1  0 	/* RxD3 */
					0  13 2  0  1  0 	/* RxD4 */
					1  1  2  0  2  0 	/* RxD5 */
					1  0  2  0  2  0 	/* RxD6 */
					1  4  2  0  2  0 	/* RxD7 */
					0  7  1  0  1  0 	/* TX_EN */
					0  8  1  0  1  0 	/* TX_ER */
					0  15 2  0  1  0 	/* RX_DV */
					0  16 2  0  1  0 	/* RX_ER */
					0  0  2  0  1  0 	/* RX_CLK */
					2  9  1  0  3  0 	/* GTX_CLK - CLK10 */
					2  8  2  0  1  0>;	/* GTX125 - CLK9 */
			};
			pio2: ucc_pin@02 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0  17 1  0  1  0   /* TxD0 */
					0  18 1  0  1  0   /* TxD1 */
					0  19 1  0  1  0   /* TxD2 */
					0  20 1  0  1  0   /* TxD3 */
					1  2  1  0  1  0   /* TxD4 */
					1  3  1  0  2  0   /* TxD5 */
					1  5  1  0  3  0   /* TxD6 */
					1  8  1  0  3  0   /* TxD7 */
					0  23 2  0  1  0   /* RxD0 */
					0  24 2  0  1  0   /* RxD1 */
					0  25 2  0  1  0   /* RxD2 */
					0  26 2  0  1  0   /* RxD3 */
					0  27 2  0  1  0   /* RxD4 */
					1  12 2  0  2  0   /* RxD5 */
					1  13 2  0  3  0   /* RxD6 */
					1  11 2  0  2  0   /* RxD7 */
					0  21 1  0  1  0   /* TX_EN */
					0  22 1  0  1  0   /* TX_ER */
					0  29 2  0  1  0   /* RX_DV */
					0  30 2  0  1  0   /* RX_ER */
					0  31 2  0  1  0   /* RX_CLK */
					2  2  1  0  2  0   /* GTX_CLK - CLK10 */
					2  3  2  0  1  0   /* GTX125 - CLK4 */
					0  1  3  0  2  0   /* MDIO */
					0  2  1  0  1  0>; /* MDC */
			};

		};
	};

	qe@e0100000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0100000 0x00100000>;
		reg = <0xe0100000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <396000000>;

		muram@10000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x00010000 0x0000c000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0xc000>;
			};
		};

		spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		spi@500 {
			cell-index = <1>;
			compatible = "fsl,spi";
			reg = <0x500 0x40>;
			interrupts = <1>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		usb@6c0 {
			compatible = "qe_udc";
			reg = <0x6c0 0x40 0x8b00 0x100>;
			interrupts = <11>;
			interrupt-parent = <&qeic>;
			mode = "slave";
		};

		enet0: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <1>;
			reg = <0x2000 0x200>;
			interrupts = <32>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk9";
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio1>;
		};

		enet1: ucc@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <2>;
			reg = <0x3000 0x200>;
			interrupts = <33>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk4";
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
			pio-handle = <&pio2>;
		};

		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2120 0x18>;
			compatible = "fsl,ucc-mdio";

			phy0: ethernet-phy@00 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x0>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@01 {
				interrupt-parent = <&ipic>;
				interrupts = <18 0x8>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <32 0x8 33 0x8>; // high:32 low:33
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		cell-index = <1>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 AD17 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 AD18 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 AD19 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 AD21*/
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 AD22*/
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 AD23*/
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 AD24*/
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100>;
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
7a234d03 LY	1	/*
	2	* MPC8360E EMDS Device Tree Source
	3	*
	4	* Copyright 2006 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12
	13	/*
	14	/memreserve/ 00000000 1000000;
	15	*/
	16
cda13dd1 PG	17	/dts-v1/;
cda13dd1 PG	18
7a234d03	19	/ {
d71a1dc6 KG	20	model = "MPC8360MDS";
d71a1dc6 KG	21	compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
7a234d03 LY	22	#address-cells = <1>;
7a234d03 LY	23	#size-cells = <1>;
7a234d03	24
ea082fa9 KG	25	aliases {
	26	ethernet0 = &enet0;
	27	ethernet1 = &enet1;
	28	serial0 = &serial0;
	29	serial1 = &serial1;
	30	pci0 = &pci0;
	31	};
	32
7a234d03	33	cpus {
7a234d03 LY	34	#address-cells = <1>;
7a234d03 LY	35	#size-cells = <0>;
7a234d03 LY	36
	37	PowerPC,8360@0 {
	38	device_type = "cpu";
cda13dd1 PG	39	reg = <0x0>;
	40	d-cache-line-size = <32>; // 32 bytes
	41	i-cache-line-size = <32>; // 32 bytes
	42	d-cache-size = <32768>; // L1, 32K
	43	i-cache-size = <32768>; // L1, 32K
	44	timebase-frequency = <66000000>;
	45	bus-frequency = <264000000>;
	46	clock-frequency = <528000000>;
7a234d03 LY	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
cda13dd1	52	reg = <0x00000000 0x10000000>;
7a234d03 LY	53	};
	54
	55	bcsr@f8000000 {
	56	device_type = "board-control";
cda13dd1	57	reg = <0xf8000000 0x8000>;
7a234d03 LY	58	};
	59
	60	soc8360@e0000000 {
	61	#address-cells = <1>;
	62	#size-cells = <1>;
7a234d03	63	device_type = "soc";
cf0d19fb	64	compatible = "simple-bus";
cda13dd1 PG	65	ranges = <0x0 0xe0000000 0x00100000>;
	66	reg = <0xe0000000 0x00000200>;
	67	bus-frequency = <264000000>;
7a234d03 LY	68
	69	wdt@200 {
	70	device_type = "watchdog";
	71	compatible = "mpc83xx_wdt";
cda13dd1	72	reg = <0x200 0x100>;
7a234d03 LY	73	};
	74
	75	i2c@3000 {
27f49807 KP	76	#address-cells = <1>;
27f49807 KP	77	#size-cells = <0>;
ec9686c4	78	cell-index = <0>;
7a234d03	79	compatible = "fsl-i2c";
cda13dd1 PG	80	reg = <0x3000 0x100>;
	81	interrupts = <14 0x8>;
	82	interrupt-parent = <&ipic>;
7a234d03	83	dfsrr;
27f49807 KP	84
	85	rtc@68 {
	86	compatible = "dallas,ds1374";
cda13dd1	87	reg = <0x68>;
27f49807	88	};
7a234d03 LY	89	};
	90
	91	i2c@3100 {
27f49807 KP	92	#address-cells = <1>;
27f49807 KP	93	#size-cells = <0>;
ec9686c4	94	cell-index = <1>;
7a234d03	95	compatible = "fsl-i2c";
cda13dd1 PG	96	reg = <0x3100 0x100>;
	97	interrupts = <15 0x8>;
	98	interrupt-parent = <&ipic>;
7a234d03 LY	99	dfsrr;
	100	};
	101
ea082fa9 KG	102	serial0: serial@4500 {
ea082fa9 KG	103	cell-index = <0>;
7a234d03 LY	104	device_type = "serial";
7a234d03 LY	105	compatible = "ns16550";
cda13dd1 PG	106	reg = <0x4500 0x100>;
	107	clock-frequency = <264000000>;
	108	interrupts = <9 0x8>;
	109	interrupt-parent = <&ipic>;
7a234d03 LY	110	};
7a234d03 LY	111
ea082fa9 KG	112	serial1: serial@4600 {
ea082fa9 KG	113	cell-index = <1>;
7a234d03 LY	114	device_type = "serial";
7a234d03 LY	115	compatible = "ns16550";
cda13dd1 PG	116	reg = <0x4600 0x100>;
	117	clock-frequency = <264000000>;
	118	interrupts = <10 0x8>;
	119	interrupt-parent = <&ipic>;
7a234d03 LY	120	};
7a234d03 LY	121
dee80553 KG	122	dma@82a8 {
	123	#address-cells = <1>;
	124	#size-cells = <1>;
	125	compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
	126	reg = <0x82a8 4>;
	127	ranges = <0 0x8100 0x1a8>;
	128	interrupt-parent = <&ipic>;
	129	interrupts = <71 8>;
	130	cell-index = <0>;
	131	dma-channel@0 {
	132	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	133	reg = <0 0x80>;
	134	interrupt-parent = <&ipic>;
	135	interrupts = <71 8>;
	136	};
	137	dma-channel@80 {
	138	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	139	reg = <0x80 0x80>;
	140	interrupt-parent = <&ipic>;
	141	interrupts = <71 8>;
	142	};
	143	dma-channel@100 {
	144	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	145	reg = <0x100 0x80>;
	146	interrupt-parent = <&ipic>;
	147	interrupts = <71 8>;
	148	};
	149	dma-channel@180 {
	150	compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
	151	reg = <0x180 0x28>;
	152	interrupt-parent = <&ipic>;
	153	interrupts = <71 8>;
	154	};
	155	};
	156
7a234d03	157	crypto@30000 {
3fd44736	158	compatible = "fsl,sec2.0";
cda13dd1 PG	159	reg = <0x30000 0x10000>;
	160	interrupts = <11 0x8>;
	161	interrupt-parent = <&ipic>;
3fd44736 KP	162	fsl,num-channels = <4>;
	163	fsl,channel-fifo-len = <24>;
	164	fsl,exec-units-mask = <0x7e>;
	165	fsl,descriptor-types-mask = <0x01010ebf>;
7a234d03 LY	166	};
7a234d03 LY	167
d71a1dc6	168	ipic: pic@700 {
7a234d03 LY	169	interrupt-controller;
	170	#address-cells = <0>;
	171	#interrupt-cells = <2>;
cda13dd1	172	reg = <0x700 0x100>;
7a234d03 LY	173	device_type = "ipic";
	174	};
	175
	176	par_io@1400 {
cda13dd1	177	reg = <0x1400 0x100>;
7a234d03 LY	178	device_type = "par_io";
	179	num-ports = <7>;
	180
d71a1dc6	181	pio1: ucc_pin@01 {
7a234d03 LY	182	pio-map = <
	183	/* port pin dir open_drain assignment has_irq */
	184	0 3 1 0 1 0 /* TxD0 */
	185	0 4 1 0 1 0 /* TxD1 */
	186	0 5 1 0 1 0 /* TxD2 */
	187	0 6 1 0 1 0 /* TxD3 */
	188	1 6 1 0 3 0 /* TxD4 */
	189	1 7 1 0 1 0 /* TxD5 */
	190	1 9 1 0 2 0 /* TxD6 */
cda13dd1	191	1 10 1 0 2 0 /* TxD7 */
7a234d03	192	0 9 2 0 1 0 /* RxD0 */
cda13dd1 PG	193	0 10 2 0 1 0 /* RxD1 */
	194	0 11 2 0 1 0 /* RxD2 */
	195	0 12 2 0 1 0 /* RxD3 */
	196	0 13 2 0 1 0 /* RxD4 */
7a234d03 LY	197	1 1 2 0 2 0 /* RxD5 */
	198	1 0 2 0 2 0 /* RxD6 */
	199	1 4 2 0 2 0 /* RxD7 */
	200	0 7 1 0 1 0 /* TX_EN */
	201	0 8 1 0 1 0 /* TX_ER */
cda13dd1 PG	202	0 15 2 0 1 0 /* RX_DV */
cda13dd1 PG	203	0 16 2 0 1 0 /* RX_ER */
7a234d03 LY	204	0 0 2 0 1 0 /* RX_CLK */
	205	2 9 1 0 3 0 /* GTX_CLK - CLK10 */
	206	2 8 2 0 1 0>; /* GTX125 - CLK9 */
	207	};
d71a1dc6	208	pio2: ucc_pin@02 {
7a234d03 LY	209	pio-map = <
7a234d03 LY	210	/* port pin dir open_drain assignment has_irq */
cda13dd1 PG	211	0 17 1 0 1 0 /* TxD0 */
	212	0 18 1 0 1 0 /* TxD1 */
	213	0 19 1 0 1 0 /* TxD2 */
	214	0 20 1 0 1 0 /* TxD3 */
7a234d03 LY	215	1 2 1 0 1 0 /* TxD4 */
	216	1 3 1 0 2 0 /* TxD5 */
	217	1 5 1 0 3 0 /* TxD6 */
	218	1 8 1 0 3 0 /* TxD7 */
cda13dd1 PG	219	0 23 2 0 1 0 /* RxD0 */
	220	0 24 2 0 1 0 /* RxD1 */
	221	0 25 2 0 1 0 /* RxD2 */
	222	0 26 2 0 1 0 /* RxD3 */
	223	0 27 2 0 1 0 /* RxD4 */
	224	1 12 2 0 2 0 /* RxD5 */
	225	1 13 2 0 3 0 /* RxD6 */
	226	1 11 2 0 2 0 /* RxD7 */
	227	0 21 1 0 1 0 /* TX_EN */
	228	0 22 1 0 1 0 /* TX_ER */
	229	0 29 2 0 1 0 /* RX_DV */
	230	0 30 2 0 1 0 /* RX_ER */
	231	0 31 2 0 1 0 /* RX_CLK */
7a234d03 LY	232	2 2 1 0 2 0 /* GTX_CLK - CLK10 */
	233	2 3 2 0 1 0 /* GTX125 - CLK4 */
	234	0 1 3 0 2 0 /* MDIO */
	235	0 2 1 0 1 0>; /* MDC */
	236	};
	237
	238	};
	239	};
	240
	241	qe@e0100000 {
	242	#address-cells = <1>;
	243	#size-cells = <1>;
	244	device_type = "qe";
a2dd70a1	245	compatible = "fsl,qe";
cda13dd1 PG	246	ranges = <0x0 0xe0100000 0x00100000>;
cda13dd1 PG	247	reg = <0xe0100000 0x480>;
7a234d03	248	brg-frequency = <0>;
cda13dd1	249	bus-frequency = <396000000>;
7a234d03 LY	250
7a234d03 LY	251	muram@10000 {
390167ef PG	252	#address-cells = <1>;
390167ef PG	253	#size-cells = <1>;
a2dd70a1	254	compatible = "fsl,qe-muram", "fsl,cpm-muram";
cda13dd1	255	ranges = <0x0 0x00010000 0x0000c000>;
7a234d03	256
390167ef	257	data-only@0 {
a2dd70a1 AV	258	compatible = "fsl,qe-muram-data",
a2dd70a1 AV	259	"fsl,cpm-muram-data";
cda13dd1	260	reg = <0x0 0xc000>;
7a234d03 LY	261	};
	262	};
	263
	264	spi@4c0 {
f3a2b29d AV	265	cell-index = <0>;
f3a2b29d AV	266	compatible = "fsl,spi";
cda13dd1	267	reg = <0x4c0 0x40>;
7a234d03	268	interrupts = <2>;
cda13dd1	269	interrupt-parent = <&qeic>;
7a234d03 LY	270	mode = "cpu";
	271	};
	272
	273	spi@500 {
f3a2b29d AV	274	cell-index = <1>;
f3a2b29d AV	275	compatible = "fsl,spi";
cda13dd1	276	reg = <0x500 0x40>;
7a234d03	277	interrupts = <1>;
cda13dd1	278	interrupt-parent = <&qeic>;
7a234d03 LY	279	mode = "cpu";
	280	};
	281
	282	usb@6c0 {
7a234d03	283	compatible = "qe_udc";
cda13dd1 PG	284	reg = <0x6c0 0x40 0x8b00 0x100>;
	285	interrupts = <11>;
	286	interrupt-parent = <&qeic>;
7a234d03 LY	287	mode = "slave";
	288	};
	289
e77b28eb	290	enet0: ucc@2000 {
7a234d03 LY	291	device_type = "network";
7a234d03 LY	292	compatible = "ucc_geth";
e77b28eb	293	cell-index = <1>;
cda13dd1 PG	294	reg = <0x2000 0x200>;
	295	interrupts = <32>;
	296	interrupt-parent = <&qeic>;
eae98266	297	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	298	rx-clock-name = "none";
9fb1e350 TT	299	tx-clock-name = "clk9";
cda13dd1	300	phy-handle = <&phy0>;
0fd8c47c	301	phy-connection-type = "rgmii-id";
cda13dd1	302	pio-handle = <&pio1>;
7a234d03 LY	303	};
7a234d03 LY	304
e77b28eb	305	enet1: ucc@3000 {
7a234d03 LY	306	device_type = "network";
7a234d03 LY	307	compatible = "ucc_geth";
e77b28eb	308	cell-index = <2>;
cda13dd1 PG	309	reg = <0x3000 0x200>;
	310	interrupts = <33>;
	311	interrupt-parent = <&qeic>;
eae98266	312	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	313	rx-clock-name = "none";
9fb1e350 TT	314	tx-clock-name = "clk4";
cda13dd1	315	phy-handle = <&phy1>;
0fd8c47c	316	phy-connection-type = "rgmii-id";
cda13dd1	317	pio-handle = <&pio2>;
7a234d03 LY	318	};
	319
	320	mdio@2120 {
	321	#address-cells = <1>;
	322	#size-cells = <0>;
cda13dd1	323	reg = <0x2120 0x18>;
d0a2f82d	324	compatible = "fsl,ucc-mdio";
7a234d03	325
d71a1dc6	326	phy0: ethernet-phy@00 {
cda13dd1 PG	327	interrupt-parent = <&ipic>;
	328	interrupts = <17 0x8>;
	329	reg = <0x0>;
7a234d03	330	device_type = "ethernet-phy";
7a234d03	331	};
d71a1dc6	332	phy1: ethernet-phy@01 {
cda13dd1 PG	333	interrupt-parent = <&ipic>;
	334	interrupts = <18 0x8>;
	335	reg = <0x1>;
7a234d03	336	device_type = "ethernet-phy";
7a234d03 LY	337	};
	338	};
	339
a2dd70a1	340	qeic: interrupt-controller@80 {
7a234d03	341	interrupt-controller;
a2dd70a1	342	compatible = "fsl,qe-ic";
7a234d03 LY	343	#address-cells = <0>;
7a234d03 LY	344	#interrupt-cells = <1>;
cda13dd1	345	reg = <0x80 0x80>;
7a234d03	346	big-endian;
cda13dd1 PG	347	interrupts = <32 0x8 33 0x8>; // high:32 low:33
cda13dd1 PG	348	interrupt-parent = <&ipic>;
7a234d03	349	};
1b3c5cda	350	};
7a234d03	351
ea082fa9 KG	352	pci0: pci@e0008500 {
ea082fa9 KG	353	cell-index = <1>;
cda13dd1	354	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	355	interrupt-map = <
	356
	357	/* IDSEL 0x11 AD17 */
cda13dd1 PG	358	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	359	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	360	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	361	0x8800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	362
1b3c5cda KG	363	/* IDSEL 0x12 AD18 */
cda13dd1 PG	364	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	365	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	366	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	367	0x9000 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	368
1b3c5cda KG	369	/* IDSEL 0x13 AD19 */
cda13dd1 PG	370	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	371	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	372	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	373	0x9800 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	374
1b3c5cda KG	375	/* IDSEL 0x15 AD21*/
cda13dd1 PG	376	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	377	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	378	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	379	0xa800 0x0 0x0 0x4 &ipic 23 0x8
1b3c5cda KG	380
1b3c5cda KG	381	/* IDSEL 0x16 AD22*/
cda13dd1 PG	382	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	383	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	384	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	385	0xb000 0x0 0x0 0x4 &ipic 22 0x8
1b3c5cda KG	386
1b3c5cda KG	387	/* IDSEL 0x17 AD23*/
cda13dd1 PG	388	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	389	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	390	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	391	0xb800 0x0 0x0 0x4 &ipic 21 0x8
1b3c5cda KG	392
1b3c5cda KG	393	/* IDSEL 0x18 AD24*/
cda13dd1 PG	394	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	395	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	396	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	397	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	398	interrupt-parent = <&ipic>;
	399	interrupts = <66 0x8>;
1b3c5cda	400	bus-range = <0 0>;
cda13dd1 PG	401	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	402	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	403	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	404	clock-frequency = <66666666>;
1b3c5cda KG	405	#interrupt-cells = <1>;
	406	#size-cells = <2>;
	407	#address-cells = <3>;
cda13dd1	408	reg = <0xe0008500 0x100>;
1b3c5cda KG	409	compatible = "fsl,mpc8349-pci";
1b3c5cda KG	410	device_type = "pci";
7a234d03 LY	411	};
7a234d03 LY	412	};