[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / boot / dts / mpc8377_mds.dts

/*
 * MPC8377E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8377emds";
	compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8377@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// booting from NOR flash
		ranges = <0 0x0 0xfe000000 0x02000000
		          1 0x0 0xf8000000 0x00008000
		          3 0x0 0xe0600000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			fs@100000 {
				reg = <0x100000 0x800000>;
			};

			kernel@1d00000 {
				reg = <0x1d00000 0x200000>;
			};

			dtb@1f00000 {
				reg = <0x1f00000 0x100000>;
			};
		};

		bcsr@1,0 {
			reg = <1 0x0 0x8000>;
			compatible = "fsl,mpc837xmds-bcsr";
		};

		nand@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <3 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};

			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		sleep-nexus {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			sleep = <&pmc 0x0c000000>;
			ranges;

			i2c@3000 {
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				compatible = "fsl-i2c";
				reg = <0x3000 0x100>;
				interrupts = <14 0x8>;
				interrupt-parent = <&ipic>;
				dfsrr;

				rtc@68 {
					compatible = "dallas,ds1374";
					reg = <0x68>;
					interrupts = <19 0x8>;
					interrupt-parent = <&ipic>;
				};
			};

			sdhci@2e000 {
				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
				reg = <0x2e000 0x1000>;
				interrupts = <42 0x8>;
				interrupt-parent = <&ipic>;
				sdhci,wp-inverted;
				/* Filled in by U-Boot */
				clock-frequency = <0>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
			sleep = <&pmc 0x00c00000>;
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
			sleep = <&pmc 0xc0000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy2: ethernet-phy@2 {
					interrupt-parent = <&ipic>;
					interrupts = <17 0x8>;
					reg = <0x2>;
				};

				phy3: ethernet-phy@3 {
					interrupt-parent = <&ipic>;
					interrupts = <18 0x8>;
					reg = <0x3>;
				};

				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy3>;
			sleep = <&pmc 0x30000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <0x47 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <0x47 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <0x47 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <0x47 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <0x47 8>;
			};
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
			sleep = <&pmc 0x03000000>;
		};

		sata@18000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x18000 0x1000>;
			interrupts = <44 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x000000c0>;
		};

		sata@19000 {
			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
			reg = <0x19000 0x1000>;
			interrupts = <45 0x8>;
			interrupt-parent = <&ipic>;
			sleep = <&pmc 0x00000030>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		sleep = <&pmc 0x00010000>;
		clock-frequency = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		sleep = <&pmc 0x00300000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		sleep = <&pmc 0x000c0000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};
};
Commit	Line	Data
5761bc5d LY	1	/*
	2	* MPC8377E MDS Device Tree Source
	3	*
	4	* Copyright 2007 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "fsl,mpc8377emds";
	16	compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	serial0 = &serial0;
	24	serial1 = &serial1;
	25	pci0 = &pci0;
0585a155 AV	26	pci1 = &pci1;
0585a155 AV	27	pci2 = &pci2;
5761bc5d LY	28	};
	29
	30	cpus {
	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
	34	PowerPC,8377@0 {
	35	device_type = "cpu";
cda13dd1 PG	36	reg = <0x0>;
	37	d-cache-line-size = <32>;
	38	i-cache-line-size = <32>;
	39	d-cache-size = <32768>;
	40	i-cache-size = <32768>;
5761bc5d LY	41	timebase-frequency = <0>;
	42	bus-frequency = <0>;
	43	clock-frequency = <0>;
	44	};
	45	};
	46
	47	memory {
	48	device_type = "memory";
	49	reg = <0x00000000 0x20000000>; // 512MB at 0
	50	};
	51
d7f46190 LY	52	localbus@e0005000 {
	53	#address-cells = <2>;
	54	#size-cells = <1>;
	55	compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
	56	reg = <0xe0005000 0x1000>;
	57	interrupts = <77 0x8>;
	58	interrupt-parent = <&ipic>;
	59
	60	// booting from NOR flash
	61	ranges = <0 0x0 0xfe000000 0x02000000
	62	1 0x0 0xf8000000 0x00008000
	63	3 0x0 0xe0600000 0x00008000>;
	64
	65	flash@0,0 {
	66	#address-cells = <1>;
	67	#size-cells = <1>;
	68	compatible = "cfi-flash";
	69	reg = <0 0x0 0x2000000>;
	70	bank-width = <2>;
	71	device-width = <1>;
	72
	73	u-boot@0 {
	74	reg = <0x0 0x100000>;
	75	read-only;
	76	};
	77
	78	fs@100000 {
	79	reg = <0x100000 0x800000>;
	80	};
	81
	82	kernel@1d00000 {
	83	reg = <0x1d00000 0x200000>;
	84	};
	85
	86	dtb@1f00000 {
	87	reg = <0x1f00000 0x100000>;
	88	};
	89	};
	90
	91	bcsr@1,0 {
	92	reg = <1 0x0 0x8000>;
	93	compatible = "fsl,mpc837xmds-bcsr";
	94	};
	95
	96	nand@3,0 {
	97	#address-cells = <1>;
	98	#size-cells = <1>;
	99	compatible = "fsl,mpc8377-fcm-nand",
	100	"fsl,elbc-fcm-nand";
	101	reg = <3 0x0 0x8000>;
	102
	103	u-boot@0 {
	104	reg = <0x0 0x100000>;
	105	read-only;
	106	};
	107
	108	kernel@100000 {
	109	reg = <0x100000 0x300000>;
	110	};
	111
	112	fs@400000 {
	113	reg = <0x400000 0x1c00000>;
	114	};
	115	};
116	};
117
5761bc5d LY	118	soc@e0000000 {
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	device_type = "soc";
cf0d19fb	122	compatible = "simple-bus";
5761bc5d LY	123	ranges = <0x0 0xe0000000 0x00100000>;
	124	reg = <0xe0000000 0x00000200>;
	125	bus-frequency = <0>;
	126
	127	wdt@200 {
	128	compatible = "mpc83xx_wdt";
	129	reg = <0x200 0x100>;
	130	};
	131
125a00d7	132	sleep-nexus {
5761bc5d	133	#address-cells = <1>;
125a00d7 AV	134	#size-cells = <1>;
	135	compatible = "simple-bus";
	136	sleep = <&pmc 0x0c000000>;
	137	ranges;
8b77aeb4	138
125a00d7 AV	139	i2c@3000 {
	140	#address-cells = <1>;
	141	#size-cells = <0>;
	142	cell-index = <0>;
	143	compatible = "fsl-i2c";
	144	reg = <0x3000 0x100>;
	145	interrupts = <14 0x8>;
8b77aeb4	146	interrupt-parent = <&ipic>;
125a00d7 AV	147	dfsrr;
	148
	149	rtc@68 {
	150	compatible = "dallas,ds1374";
	151	reg = <0x68>;
	152	interrupts = <19 0x8>;
	153	interrupt-parent = <&ipic>;
	154	};
	155	};
	156
	157	sdhci@2e000 {
1a2eceaa	158	compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
125a00d7 AV	159	reg = <0x2e000 0x1000>;
	160	interrupts = <42 0x8>;
	161	interrupt-parent = <&ipic>;
50dfe70f	162	sdhci,wp-inverted;
125a00d7 AV	163	/* Filled in by U-Boot */
125a00d7 AV	164	clock-frequency = <0>;
8b77aeb4	165	};
5761bc5d LY	166	};
	167
	168	i2c@3100 {
	169	#address-cells = <1>;
	170	#size-cells = <0>;
	171	cell-index = <1>;
	172	compatible = "fsl-i2c";
	173	reg = <0x3100 0x100>;
cda13dd1 PG	174	interrupts = <15 0x8>;
cda13dd1 PG	175	interrupt-parent = <&ipic>;
5761bc5d LY	176	dfsrr;
	177	};
	178
	179	spi@7000 {
f3a2b29d AV	180	cell-index = <0>;
f3a2b29d AV	181	compatible = "fsl,spi";
5761bc5d	182	reg = <0x7000 0x1000>;
cda13dd1 PG	183	interrupts = <16 0x8>;
cda13dd1 PG	184	interrupt-parent = <&ipic>;
5761bc5d LY	185	mode = "cpu";
	186	};
	187
5761bc5d LY	188	usb@23000 {
	189	compatible = "fsl-usb2-dr";
	190	reg = <0x23000 0x1000>;
	191	#address-cells = <1>;
	192	#size-cells = <0>;
cda13dd1 PG	193	interrupt-parent = <&ipic>;
cda13dd1 PG	194	interrupts = <38 0x8>;
28b95885 LY	195	dr_mode = "host";
28b95885 LY	196	phy_type = "ulpi";
125a00d7	197	sleep = <&pmc 0x00c00000>;
5761bc5d LY	198	};
5761bc5d LY	199
5761bc5d	200	enet0: ethernet@24000 {
70b3adbb AV	201	#address-cells = <1>;
70b3adbb AV	202	#size-cells = <1>;
5761bc5d LY	203	cell-index = <0>;
	204	device_type = "network";
	205	model = "eTSEC";
	206	compatible = "gianfar";
	207	reg = <0x24000 0x1000>;
70b3adbb	208	ranges = <0x0 0x24000 0x1000>;
5761bc5d	209	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	210	interrupts = <32 0x8 33 0x8 34 0x8>;
5761bc5d	211	phy-connection-type = "mii";
cda13dd1	212	interrupt-parent = <&ipic>;
b31a1d8b	213	tbi-handle = <&tbi0>;
cda13dd1	214	phy-handle = <&phy2>;
125a00d7 AV	215	sleep = <&pmc 0xc0000000>;
125a00d7 AV	216	fsl,magic-packet;
70b3adbb AV	217
	218	mdio@520 {
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221	compatible = "fsl,gianfar-mdio";
	222	reg = <0x520 0x20>;
	223
	224	phy2: ethernet-phy@2 {
	225	interrupt-parent = <&ipic>;
	226	interrupts = <17 0x8>;
	227	reg = <0x2>;
70b3adbb AV	228	};
	229
	230	phy3: ethernet-phy@3 {
	231	interrupt-parent = <&ipic>;
	232	interrupts = <18 0x8>;
	233	reg = <0x3>;
70b3adbb AV	234	};
	235
	236	tbi0: tbi-phy@11 {
	237	reg = <0x11>;
	238	device_type = "tbi-phy";
	239	};
	240	};
5761bc5d LY	241	};
	242
	243	enet1: ethernet@25000 {
70b3adbb AV	244	#address-cells = <1>;
70b3adbb AV	245	#size-cells = <1>;
5761bc5d LY	246	cell-index = <1>;
	247	device_type = "network";
	248	model = "eTSEC";
	249	compatible = "gianfar";
	250	reg = <0x25000 0x1000>;
70b3adbb	251	ranges = <0x0 0x25000 0x1000>;
5761bc5d	252	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	253	interrupts = <35 0x8 36 0x8 37 0x8>;
5761bc5d	254	phy-connection-type = "mii";
cda13dd1	255	interrupt-parent = <&ipic>;
b31a1d8b	256	tbi-handle = <&tbi1>;
cda13dd1	257	phy-handle = <&phy3>;
125a00d7 AV	258	sleep = <&pmc 0x30000000>;
125a00d7 AV	259	fsl,magic-packet;
70b3adbb AV	260
	261	mdio@520 {
	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264	compatible = "fsl,gianfar-tbi";
	265	reg = <0x520 0x20>;
	266
	267	tbi1: tbi-phy@11 {
	268	reg = <0x11>;
	269	device_type = "tbi-phy";
	270	};
	271	};
5761bc5d LY	272	};
	273
	274	serial0: serial@4500 {
	275	cell-index = <0>;
	276	device_type = "serial";
f706bed1	277	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	278	reg = <0x4500 0x100>;
5761bc5d LY	279	clock-frequency = <0>;
cda13dd1 PG	280	interrupts = <9 0x8>;
cda13dd1 PG	281	interrupt-parent = <&ipic>;
5761bc5d LY	282	};
	283
	284	serial1: serial@4600 {
	285	cell-index = <1>;
	286	device_type = "serial";
f706bed1	287	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	288	reg = <0x4600 0x100>;
5761bc5d LY	289	clock-frequency = <0>;
cda13dd1 PG	290	interrupts = <10 0x8>;
cda13dd1 PG	291	interrupt-parent = <&ipic>;
5761bc5d LY	292	};
5761bc5d LY	293
3f346935 ZW	294	dma@82a8 {
	295	#address-cells = <1>;
	296	#size-cells = <1>;
8939700e	297	compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
3f346935 ZW	298	reg = <0x82a8 4>;
	299	ranges = <0 0x8100 0x1a8>;
	300	interrupt-parent = <&ipic>;
	301	interrupts = <0x47 8>;
	302	cell-index = <0>;
	303	dma-channel@0 {
8939700e	304	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
3f346935	305	reg = <0 0x80>;
aeb42762	306	cell-index = <0>;
8939700e KG	307	interrupt-parent = <&ipic>;
8939700e KG	308	interrupts = <0x47 8>;
3f346935 ZW	309	};
3f346935 ZW	310	dma-channel@80 {
8939700e	311	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
3f346935	312	reg = <0x80 0x80>;
aeb42762	313	cell-index = <1>;
8939700e KG	314	interrupt-parent = <&ipic>;
8939700e KG	315	interrupts = <0x47 8>;
3f346935 ZW	316	};
3f346935 ZW	317	dma-channel@100 {
8939700e	318	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
3f346935	319	reg = <0x100 0x80>;
aeb42762	320	cell-index = <2>;
8939700e KG	321	interrupt-parent = <&ipic>;
8939700e KG	322	interrupts = <0x47 8>;
3f346935 ZW	323	};
3f346935 ZW	324	dma-channel@180 {
8939700e	325	compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
3f346935	326	reg = <0x180 0x28>;
aeb42762	327	cell-index = <3>;
8939700e KG	328	interrupt-parent = <&ipic>;
8939700e KG	329	interrupts = <0x47 8>;
3f346935 ZW	330	};
	331	};
	332
dee80553	333	crypto@30000 {
3fd44736 KP	334	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	335	"fsl,sec2.1", "fsl,sec2.0";
dee80553 KG	336	reg = <0x30000 0x10000>;
	337	interrupts = <11 0x8>;
	338	interrupt-parent = <&ipic>;
3fd44736 KP	339	fsl,num-channels = <4>;
	340	fsl,channel-fifo-len = <24>;
	341	fsl,exec-units-mask = <0x9fe>;
	342	fsl,descriptor-types-mask = <0x3ab0ebf>;
125a00d7	343	sleep = <&pmc 0x03000000>;
dee80553 KG	344	};
	345
	346	sata@18000 {
	347	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
	348	reg = <0x18000 0x1000>;
	349	interrupts = <44 0x8>;
	350	interrupt-parent = <&ipic>;
125a00d7	351	sleep = <&pmc 0x000000c0>;
dee80553 KG	352	};
	353
	354	sata@19000 {
	355	compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
	356	reg = <0x19000 0x1000>;
	357	interrupts = <45 0x8>;
	358	interrupt-parent = <&ipic>;
125a00d7	359	sleep = <&pmc 0x00000030>;
dee80553 KG	360	};
dee80553 KG	361
5761bc5d LY	362	/* IPIC
	363	* interrupts cell = <intr #, sense>
	364	* sense values match linux IORESOURCE_IRQ_* defines:
	365	* sense == 8: Level, low assertion
	366	* sense == 2: Edge, high-to-low change
	367	*/
	368	ipic: pic@700 {
	369	compatible = "fsl,ipic";
	370	interrupt-controller;
	371	#address-cells = <0>;
	372	#interrupt-cells = <2>;
	373	reg = <0x700 0x100>;
	374	};
125a00d7 AV	375
	376	pmc: power@b00 {
	377	compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
	378	reg = <0xb00 0x100 0xa00 0x100>;
	379	interrupts = <80 0x8>;
	380	interrupt-parent = <&ipic>;
	381	};
5761bc5d LY	382	};
	383
	384	pci0: pci@e0008500 {
5761bc5d LY	385	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	386	interrupt-map = <
	387
	388	/* IDSEL 0x11 */
cda13dd1 PG	389	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	390	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	391	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	392	0x8800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	393
5761bc5d LY	394	/* IDSEL 0x12 */
cda13dd1 PG	395	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	396	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	397	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	398	0x9000 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	399
5761bc5d LY	400	/* IDSEL 0x13 */
cda13dd1 PG	401	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	402	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	403	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	404	0x9800 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	405
5761bc5d LY	406	/* IDSEL 0x15 */
cda13dd1 PG	407	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	408	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	409	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	410	0xa800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	411
5761bc5d LY	412	/* IDSEL 0x16 */
cda13dd1 PG	413	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	414	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	415	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	416	0xb000 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	417
5761bc5d LY	418	/* IDSEL 0x17 */
cda13dd1 PG	419	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	420	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	421	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	422	0xb800 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	423
5761bc5d LY	424	/* IDSEL 0x18 */
cda13dd1 PG	425	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	426	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	427	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	428	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	429	interrupt-parent = <&ipic>;
	430	interrupts = <66 0x8>;
	431	bus-range = <0x0 0x0>;
5761bc5d LY	432	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	433	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	434	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
125a00d7	435	sleep = <&pmc 0x00010000>;
5761bc5d LY	436	clock-frequency = <0>;
	437	#interrupt-cells = <1>;
	438	#size-cells = <2>;
	439	#address-cells = <3>;
5b70a097 JR	440	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	441	0xe0008300 0x8>; /* config space access registers */
5761bc5d LY	442	compatible = "fsl,mpc8349-pci";
	443	device_type = "pci";
	444	};
0585a155 AV	445
	446	pci1: pcie@e0009000 {
	447	#address-cells = <3>;
	448	#size-cells = <2>;
	449	#interrupt-cells = <1>;
	450	device_type = "pci";
	451	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	452	reg = <0xe0009000 0x00001000>;
	453	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	454	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	455	bus-range = <0 255>;
	456	interrupt-map-mask = <0xf800 0 0 7>;
	457	interrupt-map = <0 0 0 1 &ipic 1 8
	458	0 0 0 2 &ipic 1 8
	459	0 0 0 3 &ipic 1 8
	460	0 0 0 4 &ipic 1 8>;
125a00d7	461	sleep = <&pmc 0x00300000>;
0585a155 AV	462	clock-frequency = <0>;
	463
	464	pcie@0 {
	465	#address-cells = <3>;
	466	#size-cells = <2>;
	467	device_type = "pci";
	468	reg = <0 0 0 0 0>;
	469	ranges = <0x02000000 0 0xa8000000
	470	0x02000000 0 0xa8000000
	471	0 0x10000000
	472	0x01000000 0 0x00000000
	473	0x01000000 0 0x00000000
	474	0 0x00800000>;
	475	};
	476	};
	477
	478	pci2: pcie@e000a000 {
	479	#address-cells = <3>;
	480	#size-cells = <2>;
	481	#interrupt-cells = <1>;
	482	device_type = "pci";
	483	compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
	484	reg = <0xe000a000 0x00001000>;
	485	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	486	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	487	bus-range = <0 255>;
	488	interrupt-map-mask = <0xf800 0 0 7>;
	489	interrupt-map = <0 0 0 1 &ipic 2 8
	490	0 0 0 2 &ipic 2 8
	491	0 0 0 3 &ipic 2 8
	492	0 0 0 4 &ipic 2 8>;
125a00d7	493	sleep = <&pmc 0x000c0000>;
0585a155 AV	494	clock-frequency = <0>;
	495
	496	pcie@0 {
	497	#address-cells = <3>;
	498	#size-cells = <2>;
	499	device_type = "pci";
	500	reg = <0 0 0 0 0>;
	501	ranges = <0x02000000 0 0xc8000000
	502	0x02000000 0 0xc8000000
	503	0 0x10000000
	504	0x01000000 0 0x00000000
	505	0x01000000 0 0x00000000
	506	0 0x00800000>;
	507	};
	508	};
5761bc5d	509	};