[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / boot / dts / mpc8378_rdb.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8378E RDB Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 */

/dts-v1/;

/ {
	compatible = "fsl,mpc8378rdb";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8378@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when
		// booting from nand, but the
		// addresses are the same.
		ranges = <0x0 0x0 0xfe000000 0x00800000
		          0x1 0x0 0xe0600000 0x00008000
		          0x2 0x0 0xf0000000 0x00020000
		          0x3 0x0 0xfa000000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <0x1 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};
			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	immr@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		gpio1: gpio-controller@c00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
			reg = <0xc00 0x100>;
			interrupts = <74 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		gpio2: gpio-controller@d00 {
			#gpio-cells = <2>;
			compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
			reg = <0xd00 0x100>;
			interrupts = <75 0x8>;
			interrupt-parent = <&ipic>;
			gpio-controller;
		};

		sleep-nexus {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			sleep = <&pmc 0x0c000000>;
			ranges;

			i2c@3000 {
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				compatible = "fsl-i2c";
				reg = <0x3000 0x100>;
				interrupts = <14 0x8>;
				interrupt-parent = <&ipic>;
				dfsrr;

				dtt@48 {
					compatible = "national,lm75";
					reg = <0x48>;
				};

				at24@50 {
					compatible = "atmel,24c256";
					reg = <0x50>;
				};

				rtc@68 {
					compatible = "dallas,ds1339";
					reg = <0x68>;
				};

				mcu_pio: mcu@a {
					#gpio-cells = <2>;
					compatible = "fsl,mc9s08qg8-mpc8378erdb",
						     "fsl,mcu-mpc8349emitx";
					reg = <0x0a>;
					gpio-controller;
				};
			};

			sdhci@2e000 {
				compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
				reg = <0x2e000 0x1000>;
				interrupts = <42 0x8>;
				interrupt-parent = <&ipic>;
				sdhci,wp-inverted;
				/* Filled in by U-Boot */
				clock-frequency = <111111111>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			phy_type = "ulpi";
			sleep = <&pmc 0x00c00000>;
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
			sleep = <&pmc 0xc0000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy2: ethernet-phy@2 {
					interrupt-parent = <&ipic>;
					interrupts = <17 0x8>;
					reg = <0x2>;
				};

				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			fixed-link = <1 1 1000 0 0>;
			tbi-handle = <&tbi1>;
			sleep = <&pmc 0x30000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
			sleep = <&pmc 0x03000000>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */

				/* IDSEL AD14 IRQ6 inta */
				 0x7000 0x0 0x0 0x1 &ipic 22 0x8

				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
				 0x7800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		sleep = <&pmc 0x00010000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		sleep = <&pmc 0x00300000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		sleep = <&pmc 0x000c0000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	leds {
		compatible = "gpio-leds";

		pwr {
			gpios = <&mcu_pio 0 0>;
			default-state = "on";
		};

		hdd {
			gpios = <&mcu_pio 1 0>;
			linux,default-trigger = "disk-activity";
		};
	};
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
23dd1cbf KP	2	/*
	3	* MPC8378E RDB Device Tree Source
	4	*
	5	* Copyright 2007, 2008 Freescale Semiconductor Inc.
23dd1cbf KP	6	*/
	7
	8	/dts-v1/;
	9
	10	/ {
3b29dade	11	compatible = "fsl,mpc8378rdb";
23dd1cbf KP	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14
	15	aliases {
	16	ethernet0 = &enet0;
	17	ethernet1 = &enet1;
	18	serial0 = &serial0;
	19	serial1 = &serial1;
	20	pci0 = &pci0;
0585a155 AV	21	pci1 = &pci1;
0585a155 AV	22	pci2 = &pci2;
23dd1cbf KP	23	};
	24
	25	cpus {
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28
	29	PowerPC,8378@0 {
	30	device_type = "cpu";
cda13dd1	31	reg = <0x0>;
23dd1cbf KP	32	d-cache-line-size = <32>;
	33	i-cache-line-size = <32>;
	34	d-cache-size = <32768>;
	35	i-cache-size = <32768>;
	36	timebase-frequency = <0>;
	37	bus-frequency = <0>;
	38	clock-frequency = <0>;
	39	};
	40	};
	41
	42	memory {
	43	device_type = "memory";
	44	reg = <0x00000000 0x10000000>; // 256MB at 0
	45	};
	46
	47	localbus@e0005000 {
	48	#address-cells = <2>;
	49	#size-cells = <1>;
	50	compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
	51	reg = <0xe0005000 0x1000>;
cda13dd1	52	interrupts = <77 0x8>;
23dd1cbf KP	53	interrupt-parent = <&ipic>;
	54
	55	// CS0 and CS1 are swapped when
	56	// booting from nand, but the
	57	// addresses are the same.
cda13dd1 PG	58	ranges = <0x0 0x0 0xfe000000 0x00800000
	59	0x1 0x0 0xe0600000 0x00008000
	60	0x2 0x0 0xf0000000 0x00020000
	61	0x3 0x0 0xfa000000 0x00008000>;
23dd1cbf KP	62
	63	flash@0,0 {
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	compatible = "cfi-flash";
cda13dd1	67	reg = <0x0 0x0 0x800000>;
23dd1cbf KP	68	bank-width = <2>;
	69	device-width = <1>;
	70	};
	71
	72	nand@1,0 {
	73	#address-cells = <1>;
	74	#size-cells = <1>;
	75	compatible = "fsl,mpc8378-fcm-nand",
	76	"fsl,elbc-fcm-nand";
cda13dd1	77	reg = <0x1 0x0 0x8000>;
23dd1cbf KP	78
	79	u-boot@0 {
	80	reg = <0x0 0x100000>;
	81	read-only;
	82	};
	83
	84	kernel@100000 {
	85	reg = <0x100000 0x300000>;
	86	};
	87	fs@400000 {
	88	reg = <0x400000 0x1c00000>;
	89	};
	90	};
	91	};
	92
	93	immr@e0000000 {
	94	#address-cells = <1>;
	95	#size-cells = <1>;
	96	device_type = "soc";
	97	compatible = "simple-bus";
cda13dd1	98	ranges = <0x0 0xe0000000 0x00100000>;
23dd1cbf KP	99	reg = <0xe0000000 0x00000200>;
	100	bus-frequency = <0>;
	101
	102	wdt@200 {
	103	device_type = "watchdog";
	104	compatible = "mpc83xx_wdt";
	105	reg = <0x200 0x100>;
	106	};
	107
9e7d95c1 RP	108	gpio1: gpio-controller@c00 {
	109	#gpio-cells = <2>;
	110	compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
	111	reg = <0xc00 0x100>;
	112	interrupts = <74 0x8>;
	113	interrupt-parent = <&ipic>;
	114	gpio-controller;
	115	};
	116
	117	gpio2: gpio-controller@d00 {
	118	#gpio-cells = <2>;
	119	compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
	120	reg = <0xd00 0x100>;
	121	interrupts = <75 0x8>;
	122	interrupt-parent = <&ipic>;
	123	gpio-controller;
	124	};
	125
125a00d7	126	sleep-nexus {
23dd1cbf	127	#address-cells = <1>;
125a00d7 AV	128	#size-cells = <1>;
	129	compatible = "simple-bus";
	130	sleep = <&pmc 0x0c000000>;
	131	ranges;
f7a0be45	132
125a00d7 AV	133	i2c@3000 {
	134	#address-cells = <1>;
	135	#size-cells = <0>;
	136	cell-index = <0>;
	137	compatible = "fsl-i2c";
	138	reg = <0x3000 0x100>;
	139	interrupts = <14 0x8>;
	140	interrupt-parent = <&ipic>;
	141	dfsrr;
	142
	143	dtt@48 {
	144	compatible = "national,lm75";
	145	reg = <0x48>;
	146	};
	147
	148	at24@50 {
8d0590ce	149	compatible = "atmel,24c256";
125a00d7 AV	150	reg = <0x50>;
	151	};
	152
	153	rtc@68 {
	154	compatible = "dallas,ds1339";
	155	reg = <0x68>;
	156	};
	157
	158	mcu_pio: mcu@a {
	159	#gpio-cells = <2>;
	160	compatible = "fsl,mc9s08qg8-mpc8378erdb",
	161	"fsl,mcu-mpc8349emitx";
	162	reg = <0x0a>;
	163	gpio-controller;
	164	};
23dd1cbf	165	};
44274698	166
125a00d7	167	sdhci@2e000 {
1a2eceaa	168	compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
125a00d7 AV	169	reg = <0x2e000 0x1000>;
	170	interrupts = <42 0x8>;
	171	interrupt-parent = <&ipic>;
50dfe70f	172	sdhci,wp-inverted;
125a00d7	173	/* Filled in by U-Boot */
89f37296	174	clock-frequency = <111111111>;
44274698	175	};
23dd1cbf KP	176	};
	177
	178	i2c@3100 {
	179	#address-cells = <1>;
	180	#size-cells = <0>;
	181	cell-index = <1>;
	182	compatible = "fsl-i2c";
	183	reg = <0x3100 0x100>;
cda13dd1 PG	184	interrupts = <15 0x8>;
cda13dd1 PG	185	interrupt-parent = <&ipic>;
23dd1cbf KP	186	dfsrr;
	187	};
	188
	189	spi@7000 {
	190	cell-index = <0>;
	191	compatible = "fsl,spi";
	192	reg = <0x7000 0x1000>;
cda13dd1 PG	193	interrupts = <16 0x8>;
cda13dd1 PG	194	interrupt-parent = <&ipic>;
23dd1cbf KP	195	mode = "cpu";
	196	};
	197
dee80553 KG	198	dma@82a8 {
	199	#address-cells = <1>;
	200	#size-cells = <1>;
	201	compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
	202	reg = <0x82a8 4>;
	203	ranges = <0 0x8100 0x1a8>;
	204	interrupt-parent = <&ipic>;
	205	interrupts = <71 8>;
	206	cell-index = <0>;
	207	dma-channel@0 {
	208	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	209	reg = <0 0x80>;
aeb42762	210	cell-index = <0>;
dee80553 KG	211	interrupt-parent = <&ipic>;
	212	interrupts = <71 8>;
	213	};
	214	dma-channel@80 {
	215	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	216	reg = <0x80 0x80>;
aeb42762	217	cell-index = <1>;
dee80553 KG	218	interrupt-parent = <&ipic>;
	219	interrupts = <71 8>;
	220	};
	221	dma-channel@100 {
	222	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	223	reg = <0x100 0x80>;
aeb42762	224	cell-index = <2>;
dee80553 KG	225	interrupt-parent = <&ipic>;
	226	interrupts = <71 8>;
	227	};
	228	dma-channel@180 {
	229	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	230	reg = <0x180 0x28>;
aeb42762	231	cell-index = <3>;
dee80553 KG	232	interrupt-parent = <&ipic>;
	233	interrupts = <71 8>;
	234	};
	235	};
	236
23dd1cbf KP	237	usb@23000 {
	238	compatible = "fsl-usb2-dr";
	239	reg = <0x23000 0x1000>;
	240	#address-cells = <1>;
	241	#size-cells = <0>;
cda13dd1 PG	242	interrupt-parent = <&ipic>;
cda13dd1 PG	243	interrupts = <38 0x8>;
8e8ff3a3	244	phy_type = "ulpi";
125a00d7	245	sleep = <&pmc 0x00c00000>;
23dd1cbf KP	246	};
23dd1cbf KP	247
23dd1cbf	248	enet0: ethernet@24000 {
70b3adbb AV	249	#address-cells = <1>;
70b3adbb AV	250	#size-cells = <1>;
23dd1cbf KP	251	cell-index = <0>;
	252	device_type = "network";
	253	model = "eTSEC";
	254	compatible = "gianfar";
	255	reg = <0x24000 0x1000>;
70b3adbb	256	ranges = <0x0 0x24000 0x1000>;
23dd1cbf	257	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	258	interrupts = <32 0x8 33 0x8 34 0x8>;
23dd1cbf	259	phy-connection-type = "mii";
cda13dd1	260	interrupt-parent = <&ipic>;
70b3adbb	261	tbi-handle = <&tbi0>;
cda13dd1	262	phy-handle = <&phy2>;
125a00d7 AV	263	sleep = <&pmc 0xc0000000>;
125a00d7 AV	264	fsl,magic-packet;
70b3adbb AV	265
	266	mdio@520 {
	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	compatible = "fsl,gianfar-mdio";
	270	reg = <0x520 0x20>;
	271
	272	phy2: ethernet-phy@2 {
	273	interrupt-parent = <&ipic>;
	274	interrupts = <17 0x8>;
	275	reg = <0x2>;
70b3adbb AV	276	};
	277
	278	tbi0: tbi-phy@11 {
	279	reg = <0x11>;
	280	device_type = "tbi-phy";
	281	};
	282	};
23dd1cbf KP	283	};
	284
	285	enet1: ethernet@25000 {
70b3adbb AV	286	#address-cells = <1>;
70b3adbb AV	287	#size-cells = <1>;
23dd1cbf KP	288	cell-index = <1>;
	289	device_type = "network";
	290	model = "eTSEC";
	291	compatible = "gianfar";
	292	reg = <0x25000 0x1000>;
70b3adbb	293	ranges = <0x0 0x25000 0x1000>;
23dd1cbf	294	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	295	interrupts = <35 0x8 36 0x8 37 0x8>;
23dd1cbf	296	phy-connection-type = "mii";
cda13dd1	297	interrupt-parent = <&ipic>;
f17c6323	298	fixed-link = <1 1 1000 0 0>;
70b3adbb	299	tbi-handle = <&tbi1>;
125a00d7 AV	300	sleep = <&pmc 0x30000000>;
125a00d7 AV	301	fsl,magic-packet;
70b3adbb AV	302
	303	mdio@520 {
	304	#address-cells = <1>;
	305	#size-cells = <0>;
	306	compatible = "fsl,gianfar-tbi";
	307	reg = <0x520 0x20>;
	308
	309	tbi1: tbi-phy@11 {
	310	reg = <0x11>;
	311	device_type = "tbi-phy";
	312	};
	313	};
23dd1cbf KP	314	};
	315
	316	serial0: serial@4500 {
	317	cell-index = <0>;
	318	device_type = "serial";
f706bed1	319	compatible = "fsl,ns16550", "ns16550";
23dd1cbf KP	320	reg = <0x4500 0x100>;
23dd1cbf KP	321	clock-frequency = <0>;
cda13dd1 PG	322	interrupts = <9 0x8>;
cda13dd1 PG	323	interrupt-parent = <&ipic>;
23dd1cbf KP	324	};
	325
	326	serial1: serial@4600 {
	327	cell-index = <1>;
	328	device_type = "serial";
f706bed1	329	compatible = "fsl,ns16550", "ns16550";
23dd1cbf KP	330	reg = <0x4600 0x100>;
23dd1cbf KP	331	clock-frequency = <0>;
cda13dd1 PG	332	interrupts = <10 0x8>;
cda13dd1 PG	333	interrupt-parent = <&ipic>;
23dd1cbf KP	334	};
	335
	336	crypto@30000 {
3fd44736 KP	337	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	338	"fsl,sec2.1", "fsl,sec2.0";
23dd1cbf	339	reg = <0x30000 0x10000>;
cda13dd1 PG	340	interrupts = <11 0x8>;
cda13dd1 PG	341	interrupt-parent = <&ipic>;
3fd44736 KP	342	fsl,num-channels = <4>;
	343	fsl,channel-fifo-len = <24>;
	344	fsl,exec-units-mask = <0x9fe>;
	345	fsl,descriptor-types-mask = <0x3ab0ebf>;
125a00d7	346	sleep = <&pmc 0x03000000>;
a0e8618c AV	347	};
a0e8618c AV	348
23dd1cbf KP	349	/* IPIC
	350	* interrupts cell = <intr #, sense>
	351	* sense values match linux IORESOURCE_IRQ_* defines:
	352	* sense == 8: Level, low assertion
	353	* sense == 2: Edge, high-to-low change
	354	*/
	355	ipic: interrupt-controller@700 {
	356	compatible = "fsl,ipic";
	357	interrupt-controller;
	358	#address-cells = <0>;
	359	#interrupt-cells = <2>;
	360	reg = <0x700 0x100>;
	361	};
125a00d7 AV	362
	363	pmc: power@b00 {
	364	compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
	365	reg = <0xb00 0x100 0xa00 0x100>;
	366	interrupts = <80 0x8>;
	367	interrupt-parent = <&ipic>;
	368	};
23dd1cbf KP	369	};
	370
	371	pci0: pci@e0008500 {
	372	interrupt-map-mask = <0xf800 0 0 7>;
	373	interrupt-map = <
	374	/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
	375
	376	/* IDSEL AD14 IRQ6 inta */
cda13dd1	377	0x7000 0x0 0x0 0x1 &ipic 22 0x8
23dd1cbf KP	378
23dd1cbf KP	379	/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
cda13dd1 PG	380	0x7800 0x0 0x0 0x1 &ipic 21 0x8
	381	0x7800 0x0 0x0 0x2 &ipic 22 0x8
	382	0x7800 0x0 0x0 0x4 &ipic 23 0x8
23dd1cbf KP	383
23dd1cbf KP	384	/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
cda13dd1 PG	385	0xE000 0x0 0x0 0x1 &ipic 23 0x8
	386	0xE000 0x0 0x0 0x2 &ipic 21 0x8
	387	0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
	388	interrupt-parent = <&ipic>;
	389	interrupts = <66 0x8>;
23dd1cbf	390	bus-range = <0 0>;
cda13dd1 PG	391	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
cda13dd1 PG	392	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
1333c3d6	393	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
125a00d7	394	sleep = <&pmc 0x00010000>;
23dd1cbf KP	395	clock-frequency = <66666666>;
	396	#interrupt-cells = <1>;
	397	#size-cells = <2>;
	398	#address-cells = <3>;
5b70a097 JR	399	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	400	0xe0008300 0x8>; /* config space access registers */
23dd1cbf KP	401	compatible = "fsl,mpc8349-pci";
	402	device_type = "pci";
	403	};
0585a155 AV	404
	405	pci1: pcie@e0009000 {
	406	#address-cells = <3>;
	407	#size-cells = <2>;
	408	#interrupt-cells = <1>;
	409	device_type = "pci";
	410	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	411	reg = <0xe0009000 0x00001000>;
	412	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	413	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	414	bus-range = <0 255>;
	415	interrupt-map-mask = <0xf800 0 0 7>;
	416	interrupt-map = <0 0 0 1 &ipic 1 8
	417	0 0 0 2 &ipic 1 8
	418	0 0 0 3 &ipic 1 8
	419	0 0 0 4 &ipic 1 8>;
125a00d7	420	sleep = <&pmc 0x00300000>;
0585a155 AV	421	clock-frequency = <0>;
	422
	423	pcie@0 {
	424	#address-cells = <3>;
	425	#size-cells = <2>;
	426	device_type = "pci";
	427	reg = <0 0 0 0 0>;
	428	ranges = <0x02000000 0 0xa8000000
	429	0x02000000 0 0xa8000000
	430	0 0x10000000
	431	0x01000000 0 0x00000000
	432	0x01000000 0 0x00000000
	433	0 0x00800000>;
	434	};
	435	};
	436
	437	pci2: pcie@e000a000 {
	438	#address-cells = <3>;
	439	#size-cells = <2>;
	440	#interrupt-cells = <1>;
	441	device_type = "pci";
	442	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	443	reg = <0xe000a000 0x00001000>;
	444	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	445	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	446	bus-range = <0 255>;
	447	interrupt-map-mask = <0xf800 0 0 7>;
	448	interrupt-map = <0 0 0 1 &ipic 2 8
	449	0 0 0 2 &ipic 2 8
	450	0 0 0 3 &ipic 2 8
	451	0 0 0 4 &ipic 2 8>;
125a00d7	452	sleep = <&pmc 0x000c0000>;
0585a155 AV	453	clock-frequency = <0>;
	454
	455	pcie@0 {
	456	#address-cells = <3>;
	457	#size-cells = <2>;
	458	device_type = "pci";
	459	reg = <0 0 0 0 0>;
	460	ranges = <0x02000000 0 0xc8000000
	461	0x02000000 0 0xc8000000
	462	0 0x10000000
	463	0x01000000 0 0x00000000
	464	0x01000000 0 0x00000000
	465	0 0x00800000>;
	466	};
	467	};
6971df4f AV	468
	469	leds {
	470	compatible = "gpio-leds";
	471
	472	pwr {
	473	gpios = <&mcu_pio 0 0>;
	474	default-state = "on";
	475	};
	476
	477	hdd {
	478	gpios = <&mcu_pio 1 0>;
83e2c70e	479	linux,default-trigger = "disk-activity";
6971df4f AV	480	};
6971df4f AV	481	};
23dd1cbf	482	};