[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / boot / dts / mpc8378_rdb.dts

/*
 * MPC8378E RDB Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	compatible = "fsl,mpc8378rdb";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8378@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>;	// 256MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// CS0 and CS1 are swapped when
		// booting from nand, but the
		// addresses are the same.
		ranges = <0x0 0x0 0xfe000000 0x00800000
		          0x1 0x0 0xe0600000 0x00008000
		          0x2 0x0 0xf0000000 0x00020000
		          0x3 0x0 0xfa000000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x800000>;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <0x1 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};
			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	immr@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			device_type = "watchdog";
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <14 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
			rtc@68 {
				compatible = "dallas,ds1339";
				reg = <0x68>;
			};

			mcu_pio: mcu@a {
				#gpio-cells = <2>;
				compatible = "fsl,mc9s08qg8-mpc8378erdb",
					     "fsl,mcu-mpc8349emitx";
				reg = <0x0a>;
				gpio-controller;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			phy_type = "ulpi";
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy2: ethernet-phy@2 {
				interrupt-parent = <&ipic>;
				interrupts = <17 0x8>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@25520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-tbi";
			reg = <0x25520 0x20>;

			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};


		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			fixed-link = <1 1 1000 0 0>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: interrupt-controller@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */

				/* IDSEL AD14 IRQ6 inta */
				 0x7000 0x0 0x0 0x1 &ipic 22 0x8

				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
				 0x7800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};
};
Commit	Line	Data
23dd1cbf KP	1	/*
	2	* MPC8378E RDB Device Tree Source
	3	*
	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
3b29dade	15	compatible = "fsl,mpc8378rdb";
23dd1cbf KP	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	serial0 = &serial0;
	23	serial1 = &serial1;
	24	pci0 = &pci0;
0585a155 AV	25	pci1 = &pci1;
0585a155 AV	26	pci2 = &pci2;
23dd1cbf KP	27	};
	28
	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	PowerPC,8378@0 {
	34	device_type = "cpu";
cda13dd1	35	reg = <0x0>;
23dd1cbf KP	36	d-cache-line-size = <32>;
	37	i-cache-line-size = <32>;
	38	d-cache-size = <32768>;
	39	i-cache-size = <32768>;
	40	timebase-frequency = <0>;
	41	bus-frequency = <0>;
	42	clock-frequency = <0>;
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
	48	reg = <0x00000000 0x10000000>; // 256MB at 0
	49	};
	50
	51	localbus@e0005000 {
	52	#address-cells = <2>;
	53	#size-cells = <1>;
	54	compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
	55	reg = <0xe0005000 0x1000>;
cda13dd1	56	interrupts = <77 0x8>;
23dd1cbf KP	57	interrupt-parent = <&ipic>;
	58
	59	// CS0 and CS1 are swapped when
	60	// booting from nand, but the
	61	// addresses are the same.
cda13dd1 PG	62	ranges = <0x0 0x0 0xfe000000 0x00800000
	63	0x1 0x0 0xe0600000 0x00008000
	64	0x2 0x0 0xf0000000 0x00020000
	65	0x3 0x0 0xfa000000 0x00008000>;
23dd1cbf KP	66
	67	flash@0,0 {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	compatible = "cfi-flash";
cda13dd1	71	reg = <0x0 0x0 0x800000>;
23dd1cbf KP	72	bank-width = <2>;
	73	device-width = <1>;
	74	};
	75
	76	nand@1,0 {
	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	compatible = "fsl,mpc8378-fcm-nand",
	80	"fsl,elbc-fcm-nand";
cda13dd1	81	reg = <0x1 0x0 0x8000>;
23dd1cbf KP	82
	83	u-boot@0 {
	84	reg = <0x0 0x100000>;
	85	read-only;
	86	};
	87
	88	kernel@100000 {
	89	reg = <0x100000 0x300000>;
	90	};
	91	fs@400000 {
	92	reg = <0x400000 0x1c00000>;
	93	};
	94	};
	95	};
	96
	97	immr@e0000000 {
	98	#address-cells = <1>;
	99	#size-cells = <1>;
	100	device_type = "soc";
	101	compatible = "simple-bus";
cda13dd1	102	ranges = <0x0 0xe0000000 0x00100000>;
23dd1cbf KP	103	reg = <0xe0000000 0x00000200>;
	104	bus-frequency = <0>;
	105
	106	wdt@200 {
	107	device_type = "watchdog";
	108	compatible = "mpc83xx_wdt";
	109	reg = <0x200 0x100>;
	110	};
	111
	112	i2c@3000 {
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115	cell-index = <0>;
	116	compatible = "fsl-i2c";
	117	reg = <0x3000 0x100>;
cda13dd1 PG	118	interrupts = <14 0x8>;
cda13dd1 PG	119	interrupt-parent = <&ipic>;
23dd1cbf KP	120	dfsrr;
23dd1cbf KP	121	rtc@68 {
23dd1cbf KP	122	compatible = "dallas,ds1339";
	123	reg = <0x68>;
	124	};
44274698 AV	125
	126	mcu_pio: mcu@a {
	127	#gpio-cells = <2>;
	128	compatible = "fsl,mc9s08qg8-mpc8378erdb",
	129	"fsl,mcu-mpc8349emitx";
	130	reg = <0x0a>;
	131	gpio-controller;
	132	};
23dd1cbf KP	133	};
	134
	135	i2c@3100 {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	cell-index = <1>;
	139	compatible = "fsl-i2c";
	140	reg = <0x3100 0x100>;
cda13dd1 PG	141	interrupts = <15 0x8>;
cda13dd1 PG	142	interrupt-parent = <&ipic>;
23dd1cbf KP	143	dfsrr;
	144	};
	145
	146	spi@7000 {
	147	cell-index = <0>;
	148	compatible = "fsl,spi";
	149	reg = <0x7000 0x1000>;
cda13dd1 PG	150	interrupts = <16 0x8>;
cda13dd1 PG	151	interrupt-parent = <&ipic>;
23dd1cbf KP	152	mode = "cpu";
	153	};
	154
dee80553 KG	155	dma@82a8 {
	156	#address-cells = <1>;
	157	#size-cells = <1>;
	158	compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
	159	reg = <0x82a8 4>;
	160	ranges = <0 0x8100 0x1a8>;
	161	interrupt-parent = <&ipic>;
	162	interrupts = <71 8>;
	163	cell-index = <0>;
	164	dma-channel@0 {
	165	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	166	reg = <0 0x80>;
aeb42762	167	cell-index = <0>;
dee80553 KG	168	interrupt-parent = <&ipic>;
	169	interrupts = <71 8>;
	170	};
	171	dma-channel@80 {
	172	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	173	reg = <0x80 0x80>;
aeb42762	174	cell-index = <1>;
dee80553 KG	175	interrupt-parent = <&ipic>;
	176	interrupts = <71 8>;
	177	};
	178	dma-channel@100 {
	179	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	180	reg = <0x100 0x80>;
aeb42762	181	cell-index = <2>;
dee80553 KG	182	interrupt-parent = <&ipic>;
	183	interrupts = <71 8>;
	184	};
	185	dma-channel@180 {
	186	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	187	reg = <0x180 0x28>;
aeb42762	188	cell-index = <3>;
dee80553 KG	189	interrupt-parent = <&ipic>;
	190	interrupts = <71 8>;
	191	};
	192	};
	193
23dd1cbf KP	194	usb@23000 {
	195	compatible = "fsl-usb2-dr";
	196	reg = <0x23000 0x1000>;
	197	#address-cells = <1>;
	198	#size-cells = <0>;
cda13dd1 PG	199	interrupt-parent = <&ipic>;
cda13dd1 PG	200	interrupts = <38 0x8>;
8e8ff3a3	201	phy_type = "ulpi";
23dd1cbf KP	202	};
	203
	204	mdio@24520 {
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	compatible = "fsl,gianfar-mdio";
	208	reg = <0x24520 0x20>;
	209	phy2: ethernet-phy@2 {
cda13dd1 PG	210	interrupt-parent = <&ipic>;
	211	interrupts = <17 0x8>;
	212	reg = <0x2>;
23dd1cbf KP	213	device_type = "ethernet-phy";
23dd1cbf KP	214	};
b31a1d8b AF	215	tbi0: tbi-phy@11 {
	216	reg = <0x11>;
	217	device_type = "tbi-phy";
	218	};
	219	};
	220
	221	mdio@25520 {
	222	#address-cells = <1>;
	223	#size-cells = <0>;
	224	compatible = "fsl,gianfar-tbi";
	225	reg = <0x25520 0x20>;
	226
	227	tbi1: tbi-phy@11 {
	228	reg = <0x11>;
	229	device_type = "tbi-phy";
	230	};
23dd1cbf KP	231	};
23dd1cbf KP	232
b31a1d8b	233
23dd1cbf KP	234	enet0: ethernet@24000 {
	235	cell-index = <0>;
	236	device_type = "network";
	237	model = "eTSEC";
	238	compatible = "gianfar";
	239	reg = <0x24000 0x1000>;
	240	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	241	interrupts = <32 0x8 33 0x8 34 0x8>;
23dd1cbf	242	phy-connection-type = "mii";
cda13dd1 PG	243	interrupt-parent = <&ipic>;
cda13dd1 PG	244	phy-handle = <&phy2>;
23dd1cbf KP	245	};
	246
	247	enet1: ethernet@25000 {
	248	cell-index = <1>;
	249	device_type = "network";
	250	model = "eTSEC";
	251	compatible = "gianfar";
	252	reg = <0x25000 0x1000>;
	253	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	254	interrupts = <35 0x8 36 0x8 37 0x8>;
23dd1cbf	255	phy-connection-type = "mii";
cda13dd1	256	interrupt-parent = <&ipic>;
f17c6323	257	fixed-link = <1 1 1000 0 0>;
23dd1cbf KP	258	};
	259
	260	serial0: serial@4500 {
	261	cell-index = <0>;
	262	device_type = "serial";
	263	compatible = "ns16550";
	264	reg = <0x4500 0x100>;
	265	clock-frequency = <0>;
cda13dd1 PG	266	interrupts = <9 0x8>;
cda13dd1 PG	267	interrupt-parent = <&ipic>;
23dd1cbf KP	268	};
	269
	270	serial1: serial@4600 {
	271	cell-index = <1>;
	272	device_type = "serial";
	273	compatible = "ns16550";
	274	reg = <0x4600 0x100>;
	275	clock-frequency = <0>;
cda13dd1 PG	276	interrupts = <10 0x8>;
cda13dd1 PG	277	interrupt-parent = <&ipic>;
23dd1cbf KP	278	};
	279
	280	crypto@30000 {
3fd44736 KP	281	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	282	"fsl,sec2.1", "fsl,sec2.0";
23dd1cbf	283	reg = <0x30000 0x10000>;
cda13dd1 PG	284	interrupts = <11 0x8>;
cda13dd1 PG	285	interrupt-parent = <&ipic>;
3fd44736 KP	286	fsl,num-channels = <4>;
	287	fsl,channel-fifo-len = <24>;
	288	fsl,exec-units-mask = <0x9fe>;
	289	fsl,descriptor-types-mask = <0x3ab0ebf>;
23dd1cbf KP	290	};
	291
	292	/* IPIC
	293	* interrupts cell = <intr #, sense>
	294	* sense values match linux IORESOURCE_IRQ_* defines:
	295	* sense == 8: Level, low assertion
	296	* sense == 2: Edge, high-to-low change
	297	*/
	298	ipic: interrupt-controller@700 {
	299	compatible = "fsl,ipic";
	300	interrupt-controller;
	301	#address-cells = <0>;
	302	#interrupt-cells = <2>;
	303	reg = <0x700 0x100>;
	304	};
	305	};
	306
	307	pci0: pci@e0008500 {
	308	interrupt-map-mask = <0xf800 0 0 7>;
	309	interrupt-map = <
	310	/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
	311
	312	/* IDSEL AD14 IRQ6 inta */
cda13dd1	313	0x7000 0x0 0x0 0x1 &ipic 22 0x8
23dd1cbf KP	314
23dd1cbf KP	315	/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
cda13dd1 PG	316	0x7800 0x0 0x0 0x1 &ipic 21 0x8
	317	0x7800 0x0 0x0 0x2 &ipic 22 0x8
	318	0x7800 0x0 0x0 0x4 &ipic 23 0x8
23dd1cbf KP	319
23dd1cbf KP	320	/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
cda13dd1 PG	321	0xE000 0x0 0x0 0x1 &ipic 23 0x8
	322	0xE000 0x0 0x0 0x2 &ipic 21 0x8
	323	0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
	324	interrupt-parent = <&ipic>;
	325	interrupts = <66 0x8>;
23dd1cbf	326	bus-range = <0 0>;
cda13dd1 PG	327	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	328	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	329	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
23dd1cbf KP	330	clock-frequency = <66666666>;
	331	#interrupt-cells = <1>;
	332	#size-cells = <2>;
	333	#address-cells = <3>;
5b70a097 JR	334	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	335	0xe0008300 0x8>; /* config space access registers */
23dd1cbf KP	336	compatible = "fsl,mpc8349-pci";
	337	device_type = "pci";
	338	};
0585a155 AV	339
	340	pci1: pcie@e0009000 {
	341	#address-cells = <3>;
	342	#size-cells = <2>;
	343	#interrupt-cells = <1>;
	344	device_type = "pci";
	345	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	346	reg = <0xe0009000 0x00001000>;
	347	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	348	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	349	bus-range = <0 255>;
	350	interrupt-map-mask = <0xf800 0 0 7>;
	351	interrupt-map = <0 0 0 1 &ipic 1 8
	352	0 0 0 2 &ipic 1 8
	353	0 0 0 3 &ipic 1 8
	354	0 0 0 4 &ipic 1 8>;
	355	clock-frequency = <0>;
	356
	357	pcie@0 {
	358	#address-cells = <3>;
	359	#size-cells = <2>;
	360	device_type = "pci";
	361	reg = <0 0 0 0 0>;
	362	ranges = <0x02000000 0 0xa8000000
	363	0x02000000 0 0xa8000000
	364	0 0x10000000
	365	0x01000000 0 0x00000000
	366	0x01000000 0 0x00000000
	367	0 0x00800000>;
	368	};
	369	};
	370
	371	pci2: pcie@e000a000 {
	372	#address-cells = <3>;
	373	#size-cells = <2>;
	374	#interrupt-cells = <1>;
	375	device_type = "pci";
	376	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	377	reg = <0xe000a000 0x00001000>;
	378	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	379	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	380	bus-range = <0 255>;
	381	interrupt-map-mask = <0xf800 0 0 7>;
	382	interrupt-map = <0 0 0 1 &ipic 2 8
	383	0 0 0 2 &ipic 2 8
	384	0 0 0 3 &ipic 2 8
	385	0 0 0 4 &ipic 2 8>;
	386	clock-frequency = <0>;
	387
	388	pcie@0 {
	389	#address-cells = <3>;
	390	#size-cells = <2>;
	391	device_type = "pci";
	392	reg = <0 0 0 0 0>;
	393	ranges = <0x02000000 0 0xc8000000
	394	0x02000000 0 0xc8000000
	395	0 0x10000000
	396	0x01000000 0 0x00000000
	397	0x01000000 0 0x00000000
	398	0 0x00800000>;
	399	};
	400	};
23dd1cbf	401	};