[mirror_ubuntu-focal-kernel.git] / arch / powerpc / boot / dts / mpc8540ads.dts

/*
 * MPC8540 ADS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/include/ "fsl/e500v2_power_isa.dtsi"

/ {
	model = "MPC8540ADS";
	compatible = "MPC8540ADS", "MPC85xxADS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8540@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8540@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8540-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8540-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8540-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8540-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
				};
				phy3: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <7 1>;
					reg = <0x3>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "FEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <41 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};
		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x02 */
			0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x1000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x03 */
			0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x1800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x04 */
			0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x2000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x05 */
			0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x2800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x0c */
			0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x6000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x0d */
			0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x6800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x0e */
			0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x7000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x0f */
			0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x7800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 */
			0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x13 */
			0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x14 */
			0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2654d638 AF	1	/*
	2	* MPC8540 ADS Device Tree Source
	3	*
32f960e9	4	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
2654d638	13
2eb28006 OY	14	/include/ "fsl/e500v2_power_isa.dtsi"
2eb28006 OY	15
2654d638 AF	16	/ {
2654d638 AF	17	model = "MPC8540ADS";
52094879	18	compatible = "MPC8540ADS", "MPC85xxADS";
2654d638 AF	19	#address-cells = <1>;
2654d638 AF	20	#size-cells = <1>;
2654d638	21
ea082fa9 KG	22	aliases {
	23	ethernet0 = &enet0;
	24	ethernet1 = &enet1;
	25	ethernet2 = &enet2;
	26	serial0 = &serial0;
	27	serial1 = &serial1;
	28	pci0 = &pci0;
	29	};
	30
2654d638	31	cpus {
2654d638 AF	32	#address-cells = <1>;
2654d638 AF	33	#size-cells = <0>;
2654d638 AF	34
	35	PowerPC,8540@0 {
	36	device_type = "cpu";
32f960e9 KG	37	reg = <0x0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	42	timebase-frequency = <0>; // 33 MHz, from uboot
	43	bus-frequency = <0>; // 166 MHz
	44	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	45	next-level-cache = <&L2>;
2654d638 AF	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
32f960e9	51	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	52	};
	53
	54	soc8540@e0000000 {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
2654d638	57	device_type = "soc";
cf0d19fb	58	compatible = "simple-bus";
32f960e9	59	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	60	bus-frequency = <0>;
2654d638 AF	61
e1a22897 KG	62	ecm-law@0 {
	63	compatible = "fsl,ecm-law";
	64	reg = <0x0 0x1000>;
	65	fsl,num-laws = <8>;
	66	};
	67
	68	ecm@1000 {
	69	compatible = "fsl,mpc8540-ecm", "fsl,ecm";
	70	reg = <0x1000 0x1000>;
	71	interrupts = <17 2>;
	72	interrupt-parent = <&mpic>;
	73	};
	74
50cf6707	75	memory-controller@2000 {
8a4ab218	76	compatible = "fsl,mpc8540-memory-controller";
32f960e9	77	reg = <0x2000 0x1000>;
50cf6707	78	interrupt-parent = <&mpic>;
32f960e9	79	interrupts = <18 2>;
50cf6707 DJ	80	};
50cf6707 DJ	81
c054065b	82	L2: l2-cache-controller@20000 {
8a4ab218	83	compatible = "fsl,mpc8540-l2-cache-controller";
32f960e9 KG	84	reg = <0x20000 0x1000>;
	85	cache-line-size = <32>; // 32 bytes
	86	cache-size = <0x40000>; // L2, 256K
50cf6707	87	interrupt-parent = <&mpic>;
32f960e9	88	interrupts = <16 2>;
50cf6707 DJ	89	};
50cf6707 DJ	90
2654d638	91	i2c@3000 {
ec9686c4 KG	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	cell-index = <0>;
2654d638	95	compatible = "fsl-i2c";
32f960e9 KG	96	reg = <0x3000 0x100>;
32f960e9 KG	97	interrupts = <43 2>;
52094879	98	interrupt-parent = <&mpic>;
2654d638 AF	99	dfsrr;
	100	};
	101
dee80553 KG	102	dma@21300 {
	103	#address-cells = <1>;
	104	#size-cells = <1>;
	105	compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
	106	reg = <0x21300 0x4>;
	107	ranges = <0x0 0x21100 0x200>;
	108	cell-index = <0>;
	109	dma-channel@0 {
	110	compatible = "fsl,mpc8540-dma-channel",
	111	"fsl,eloplus-dma-channel";
	112	reg = <0x0 0x80>;
	113	cell-index = <0>;
	114	interrupt-parent = <&mpic>;
	115	interrupts = <20 2>;
	116	};
	117	dma-channel@80 {
	118	compatible = "fsl,mpc8540-dma-channel",
	119	"fsl,eloplus-dma-channel";
	120	reg = <0x80 0x80>;
	121	cell-index = <1>;
	122	interrupt-parent = <&mpic>;
	123	interrupts = <21 2>;
	124	};
	125	dma-channel@100 {
	126	compatible = "fsl,mpc8540-dma-channel",
	127	"fsl,eloplus-dma-channel";
	128	reg = <0x100 0x80>;
	129	cell-index = <2>;
	130	interrupt-parent = <&mpic>;
	131	interrupts = <22 2>;
	132	};
	133	dma-channel@180 {
	134	compatible = "fsl,mpc8540-dma-channel",
	135	"fsl,eloplus-dma-channel";
	136	reg = <0x180 0x80>;
	137	cell-index = <3>;
	138	interrupt-parent = <&mpic>;
	139	interrupts = <23 2>;
	140	};
	141	};
	142
e77b28eb	143	enet0: ethernet@24000 {
84ba4a58 AV	144	#address-cells = <1>;
84ba4a58 AV	145	#size-cells = <1>;
e77b28eb	146	cell-index = <0>;
2654d638 AF	147	device_type = "network";
	148	model = "TSEC";
	149	compatible = "gianfar";
32f960e9	150	reg = <0x24000 0x1000>;
84ba4a58	151	ranges = <0x0 0x24000 0x1000>;
eae98266	152	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	153	interrupts = <29 2 30 2 34 2>;
52094879	154	interrupt-parent = <&mpic>;
b31a1d8b	155	tbi-handle = <&tbi0>;
52094879	156	phy-handle = <&phy0>;
84ba4a58 AV	157
	158	mdio@520 {
	159	#address-cells = <1>;
	160	#size-cells = <0>;
	161	compatible = "fsl,gianfar-mdio";
	162	reg = <0x520 0x20>;
	163
	164	phy0: ethernet-phy@0 {
	165	interrupt-parent = <&mpic>;
	166	interrupts = <5 1>;
	167	reg = <0x0>;
84ba4a58 AV	168	};
	169	phy1: ethernet-phy@1 {
	170	interrupt-parent = <&mpic>;
	171	interrupts = <5 1>;
	172	reg = <0x1>;
84ba4a58 AV	173	};
	174	phy3: ethernet-phy@3 {
	175	interrupt-parent = <&mpic>;
	176	interrupts = <7 1>;
	177	reg = <0x3>;
84ba4a58 AV	178	};
	179	tbi0: tbi-phy@11 {
	180	reg = <0x11>;
	181	device_type = "tbi-phy";
	182	};
	183	};
2654d638 AF	184	};
2654d638 AF	185
e77b28eb	186	enet1: ethernet@25000 {
84ba4a58 AV	187	#address-cells = <1>;
84ba4a58 AV	188	#size-cells = <1>;
e77b28eb	189	cell-index = <1>;
2654d638 AF	190	device_type = "network";
	191	model = "TSEC";
	192	compatible = "gianfar";
32f960e9	193	reg = <0x25000 0x1000>;
84ba4a58	194	ranges = <0x0 0x25000 0x1000>;
eae98266	195	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	196	interrupts = <35 2 36 2 40 2>;
52094879	197	interrupt-parent = <&mpic>;
b31a1d8b	198	tbi-handle = <&tbi1>;
52094879	199	phy-handle = <&phy1>;
84ba4a58 AV	200
	201	mdio@520 {
	202	#address-cells = <1>;
	203	#size-cells = <0>;
	204	compatible = "fsl,gianfar-tbi";
	205	reg = <0x520 0x20>;
	206
	207	tbi1: tbi-phy@11 {
	208	reg = <0x11>;
	209	device_type = "tbi-phy";
	210	};
	211	};
2654d638 AF	212	};
2654d638 AF	213
e77b28eb	214	enet2: ethernet@26000 {
84ba4a58 AV	215	#address-cells = <1>;
84ba4a58 AV	216	#size-cells = <1>;
e77b28eb	217	cell-index = <2>;
2654d638	218	device_type = "network";
aa74a30b	219	model = "FEC";
2654d638	220	compatible = "gianfar";
32f960e9	221	reg = <0x26000 0x1000>;
84ba4a58	222	ranges = <0x0 0x26000 0x1000>;
eae98266	223	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	224	interrupts = <41 2>;
52094879	225	interrupt-parent = <&mpic>;
b31a1d8b	226	tbi-handle = <&tbi2>;
52094879	227	phy-handle = <&phy3>;
84ba4a58 AV	228
	229	mdio@520 {
	230	#address-cells = <1>;
	231	#size-cells = <0>;
	232	compatible = "fsl,gianfar-tbi";
	233	reg = <0x520 0x20>;
	234
	235	tbi2: tbi-phy@11 {
	236	reg = <0x11>;
	237	device_type = "tbi-phy";
	238	};
	239	};
2654d638 AF	240	};
2654d638 AF	241
ea082fa9 KG	242	serial0: serial@4500 {
ea082fa9 KG	243	cell-index = <0>;
2654d638	244	device_type = "serial";
f706bed1	245	compatible = "fsl,ns16550", "ns16550";
32f960e9	246	reg = <0x4500 0x100>; // reg base, size
2654d638	247	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	248	interrupts = <42 2>;
52094879	249	interrupt-parent = <&mpic>;
2654d638 AF	250	};
2654d638 AF	251
ea082fa9 KG	252	serial1: serial@4600 {
ea082fa9 KG	253	cell-index = <1>;
2654d638	254	device_type = "serial";
f706bed1	255	compatible = "fsl,ns16550", "ns16550";
32f960e9	256	reg = <0x4600 0x100>; // reg base, size
2654d638	257	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	258	interrupts = <42 2>;
52094879	259	interrupt-parent = <&mpic>;
2654d638	260	};
1b3c5cda	261	mpic: pic@40000 {
1b3c5cda KG	262	interrupt-controller;
	263	#address-cells = <0>;
	264	#interrupt-cells = <2>;
32f960e9	265	reg = <0x40000 0x40000>;
1b3c5cda KG	266	compatible = "chrp,open-pic";
1b3c5cda KG	267	device_type = "open-pic";
1b3c5cda KG	268	};
1b3c5cda KG	269	};
2654d638	270
ea082fa9	271	pci0: pci@e0008000 {
32f960e9	272	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda	273	interrupt-map = <
2654d638	274
1b3c5cda	275	/* IDSEL 0x02 */
32f960e9 KG	276	0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
	277	0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
	278	0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
	279	0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	280
1b3c5cda	281	/* IDSEL 0x03 */
32f960e9 KG	282	0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
	283	0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
	284	0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
	285	0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	286
1b3c5cda	287	/* IDSEL 0x04 */
32f960e9 KG	288	0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
	289	0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
	290	0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
	291	0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	292
1b3c5cda	293	/* IDSEL 0x05 */
32f960e9 KG	294	0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
	295	0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
	296	0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
	297	0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	298
1b3c5cda	299	/* IDSEL 0x0c */
32f960e9 KG	300	0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
	301	0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
	302	0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
	303	0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	304
1b3c5cda	305	/* IDSEL 0x0d */
32f960e9 KG	306	0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
	307	0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
	308	0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
	309	0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	310
1b3c5cda	311	/* IDSEL 0x0e */
32f960e9 KG	312	0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
	313	0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
	314	0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
	315	0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	316
1b3c5cda	317	/* IDSEL 0x0f */
32f960e9 KG	318	0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
	319	0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
	320	0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
	321	0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
2654d638	322
1b3c5cda	323	/* IDSEL 0x12 */
32f960e9 KG	324	0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
	325	0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
	326	0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
	327	0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
2654d638	328
1b3c5cda	329	/* IDSEL 0x13 */
32f960e9 KG	330	0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
	331	0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
	332	0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
	333	0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
2654d638	334
1b3c5cda	335	/* IDSEL 0x14 */
32f960e9 KG	336	0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
	337	0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
	338	0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
	339	0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
2654d638	340
1b3c5cda	341	/* IDSEL 0x15 */
32f960e9 KG	342	0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
	343	0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
	344	0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
	345	0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
1b3c5cda	346	interrupt-parent = <&mpic>;
32f960e9	347	interrupts = <24 2>;
1b3c5cda	348	bus-range = <0 0>;
32f960e9 KG	349	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	350	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	351	clock-frequency = <66666666>;
1b3c5cda KG	352	#interrupt-cells = <1>;
	353	#size-cells = <2>;
	354	#address-cells = <3>;
32f960e9	355	reg = <0xe0008000 0x1000>;
1b3c5cda KG	356	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
1b3c5cda KG	357	device_type = "pci";
2654d638 AF	358	};
2654d638 AF	359	};