[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / boot / dts / mpc8572ds.dts

/*
 * MPC8572 DS Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;
/ {
	model = "fsl,MPC8572DS";
	compatible = "fsl,MPC8572DS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8572@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};

		PowerPC,8572@1 {
			device_type = "cpu";
			reg = <0x1>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled by U-Boot
	};

	soc8572@ffe00000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xffe00000 0x100000>;
		reg = <0xffe00000 0x1000>;	// CCSRBAR & soc regs, remove once parse code for immrbase fixed
		bus-frequency = <0>;		// Filled out by uboot.

		memory-controller@2000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		memory-controller@6000 {
			compatible = "fsl,mpc8572-memory-controller";
			reg = <0x6000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8572-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@0 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x0>;
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x1>;
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x2>;
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <10 1>;
				reg = <0x3>;
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		enet2: ethernet@26000 {
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";
		};

		enet3: ethernet@27000 {
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8572-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		msi@41600 {
			compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	pci0: pcie@ffe08000 {
		cell-index = <0>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe08000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x11 func 0 - PCI slot 1 */
			0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 1 - PCI slot 1 */
			0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8900 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 2 - PCI slot 1 */
			0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 3 - PCI slot 1 */
			0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 4 - PCI slot 1 */
			0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 5 - PCI slot 1 */
			0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 6 - PCI slot 1 */
			0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x11 func 7 - PCI slot 1 */
			0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
			0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
			0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
			0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x12 func 0 - PCI slot 2 */
			0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 1 - PCI slot 2 */
			0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9100 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 2 - PCI slot 2 */
			0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9200 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 3 - PCI slot 2 */
			0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9300 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 4 - PCI slot 2 */
			0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9400 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 5 - PCI slot 2 */
			0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9500 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 6 - PCI slot 2 */
			0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9600 0x0 0x0 0x4 &mpic 0x2 0x1

			/* IDSEL 0x12 func 7 - PCI slot 2 */
			0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
			0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
			0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
			0x9700 0x0 0x0 0x4 &mpic 0x2 0x1

			// IDSEL 0x1c  USB
			0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
			0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
			0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
			0xe300 0x0 0x0 0x4 &i8259 0xb 0x2

			// IDSEL 0x1d  Audio
			0xe800 0x0 0x0 0x1 &i8259 0x6 0x2

			// IDSEL 0x1e Legacy
			0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
			0xf100 0x0 0x0 0x1 &i8259 0x7 0x2

			// IDSEL 0x1f IDE/SATA
			0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
			0xf900 0x0 0x0 0x1 &i8259 0x5 0x2

			>;

		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
			uli1575@0 {
				reg = <0x0 0x0 0x0 0x0 0x0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x2000000 0x0 0x80000000
					  0x2000000 0x0 0x80000000
					  0x0 0x20000000

					  0x1000000 0x0 0x0
					  0x1000000 0x0 0x0
					  0x0 0x100000>;
				isa@1e {
					device_type = "isa";
					#interrupt-cells = <2>;
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0x0 0x0 0x0 0x0>;
					ranges = <0x1 0x0 0x1000000 0x0 0x0
						  0x1000>;
					interrupt-parent = <&i8259>;

					i8259: interrupt-controller@20 {
						reg = <0x1 0x20 0x2
						       0x1 0xa0 0x2
						       0x1 0x4d0 0x2>;
						interrupt-controller;
						device_type = "interrupt-controller";
						#address-cells = <0>;
						#interrupt-cells = <2>;
						compatible = "chrp,iic";
						interrupts = <9 2>;
						interrupt-parent = <&mpic>;
					};

					i8042@60 {
						#size-cells = <0>;
						#address-cells = <1>;
						reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
						interrupts = <1 3 12 3>;
						interrupt-parent =
							<&i8259>;

						keyboard@0 {
							reg = <0x0>;
							compatible = "pnpPNP,303";
						};

						mouse@1 {
							reg = <0x1>;
							compatible = "pnpPNP,f03";
						};
					};

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <0x1 0x70 0x2>;
					};

					gpio@400 {
						reg = <0x1 0x400 0x80>;
					};
				};
			};
		};

	};

	pci1: pcie@ffe09000 {
		cell-index = <1>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe09000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1
			0000 0x0 0x0 0x2 &mpic 0x5 0x1
			0000 0x0 0x0 0x3 &mpic 0x6 0x1
			0000 0x0 0x0 0x4 &mpic 0x7 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci2: pcie@ffe0a000 {
		cell-index = <2>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xffe0a000 0x1000>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <27 2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1
			0000 0x0 0x0 0x2 &mpic 0x1 0x1
			0000 0x0 0x0 0x3 &mpic 0x2 0x1
			0000 0x0 0x0 0x4 &mpic 0x3 0x1
			>;
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xc0000000
				  0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};
};
Commit	Line	Data
5d54ddcb KG	1	/*
	2	* MPC8572 DS Device Tree Source
	3	*
32f960e9	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
5d54ddcb KG	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
5d54ddcb KG	13	/ {
	14	model = "fsl,MPC8572DS";
	15	compatible = "fsl,MPC8572DS";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	ethernet0 = &enet0;
	21	ethernet1 = &enet1;
	22	ethernet2 = &enet2;
	23	ethernet3 = &enet3;
	24	serial0 = &serial0;
	25	serial1 = &serial1;
	26	pci0 = &pci0;
	27	pci1 = &pci1;
	28	pci2 = &pci2;
	29	};
	30
5d54ddcb KG	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	PowerPC,8572@0 {
	36	device_type = "cpu";
32f960e9 KG	37	reg = <0x0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
5d54ddcb	42	timebase-frequency = <0>;
7e25867f KG	43	bus-frequency = <0>;
7e25867f KG	44	clock-frequency = <0>;
c054065b	45	next-level-cache = <&L2>;
7e25867f KG	46	};
	47
	48	PowerPC,8572@1 {
	49	device_type = "cpu";
32f960e9 KG	50	reg = <0x1>;
	51	d-cache-line-size = <32>; // 32 bytes
	52	i-cache-line-size = <32>; // 32 bytes
	53	d-cache-size = <0x8000>; // L1, 32K
	54	i-cache-size = <0x8000>; // L1, 32K
7e25867f	55	timebase-frequency = <0>;
5d54ddcb KG	56	bus-frequency = <0>;
5d54ddcb KG	57	clock-frequency = <0>;
c054065b	58	next-level-cache = <&L2>;
5d54ddcb KG	59	};
	60	};
	61
	62	memory {
	63	device_type = "memory";
32f960e9	64	reg = <0x0 0x0>; // Filled by U-Boot
5d54ddcb KG	65	};
	66
	67	soc8572@ffe00000 {
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	device_type = "soc";
32f960e9 KG	71	ranges = <0x0 0xffe00000 0x100000>;
32f960e9 KG	72	reg = <0xffe00000 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
5d54ddcb KG	73	bus-frequency = <0>; // Filled out by uboot.
	74
	75	memory-controller@2000 {
	76	compatible = "fsl,mpc8572-memory-controller";
32f960e9	77	reg = <0x2000 0x1000>;
5d54ddcb	78	interrupt-parent = <&mpic>;
32f960e9	79	interrupts = <18 2>;
5d54ddcb KG	80	};
	81
	82	memory-controller@6000 {
	83	compatible = "fsl,mpc8572-memory-controller";
32f960e9	84	reg = <0x6000 0x1000>;
5d54ddcb	85	interrupt-parent = <&mpic>;
32f960e9	86	interrupts = <18 2>;
5d54ddcb KG	87	};
5d54ddcb KG	88
c054065b	89	L2: l2-cache-controller@20000 {
5d54ddcb	90	compatible = "fsl,mpc8572-l2-cache-controller";
32f960e9 KG	91	reg = <0x20000 0x1000>;
	92	cache-line-size = <32>; // 32 bytes
	93	cache-size = <0x80000>; // L2, 512K
5d54ddcb	94	interrupt-parent = <&mpic>;
32f960e9	95	interrupts = <16 2>;
5d54ddcb KG	96	};
	97
	98	i2c@3000 {
ec9686c4 KG	99	#address-cells = <1>;
	100	#size-cells = <0>;
	101	cell-index = <0>;
5d54ddcb	102	compatible = "fsl-i2c";
32f960e9 KG	103	reg = <0x3000 0x100>;
32f960e9 KG	104	interrupts = <43 2>;
5d54ddcb KG	105	interrupt-parent = <&mpic>;
	106	dfsrr;
	107	};
	108
	109	i2c@3100 {
ec9686c4 KG	110	#address-cells = <1>;
	111	#size-cells = <0>;
	112	cell-index = <1>;
5d54ddcb	113	compatible = "fsl-i2c";
32f960e9 KG	114	reg = <0x3100 0x100>;
32f960e9 KG	115	interrupts = <43 2>;
5d54ddcb KG	116	interrupt-parent = <&mpic>;
	117	dfsrr;
	118	};
	119
	120	mdio@24520 {
	121	#address-cells = <1>;
	122	#size-cells = <0>;
e77b28eb	123	compatible = "fsl,gianfar-mdio";
32f960e9	124	reg = <0x24520 0x20>;
e77b28eb	125
5d54ddcb KG	126	phy0: ethernet-phy@0 {
5d54ddcb KG	127	interrupt-parent = <&mpic>;
32f960e9 KG	128	interrupts = <10 1>;
32f960e9 KG	129	reg = <0x0>;
5d54ddcb KG	130	};
	131	phy1: ethernet-phy@1 {
	132	interrupt-parent = <&mpic>;
32f960e9 KG	133	interrupts = <10 1>;
32f960e9 KG	134	reg = <0x1>;
5d54ddcb KG	135	};
	136	phy2: ethernet-phy@2 {
	137	interrupt-parent = <&mpic>;
32f960e9 KG	138	interrupts = <10 1>;
32f960e9 KG	139	reg = <0x2>;
5d54ddcb KG	140	};
	141	phy3: ethernet-phy@3 {
	142	interrupt-parent = <&mpic>;
32f960e9 KG	143	interrupts = <10 1>;
32f960e9 KG	144	reg = <0x3>;
5d54ddcb KG	145	};
	146	};
	147
e77b28eb KG	148	enet0: ethernet@24000 {
e77b28eb KG	149	cell-index = <0>;
5d54ddcb KG	150	device_type = "network";
	151	model = "eTSEC";
	152	compatible = "gianfar";
32f960e9	153	reg = <0x24000 0x1000>;
5d54ddcb	154	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	155	interrupts = <29 2 30 2 34 2>;
5d54ddcb KG	156	interrupt-parent = <&mpic>;
	157	phy-handle = <&phy0>;
	158	phy-connection-type = "rgmii-id";
	159	};
	160
e77b28eb KG	161	enet1: ethernet@25000 {
e77b28eb KG	162	cell-index = <1>;
5d54ddcb KG	163	device_type = "network";
	164	model = "eTSEC";
	165	compatible = "gianfar";
32f960e9	166	reg = <0x25000 0x1000>;
5d54ddcb	167	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	168	interrupts = <35 2 36 2 40 2>;
5d54ddcb KG	169	interrupt-parent = <&mpic>;
	170	phy-handle = <&phy1>;
	171	phy-connection-type = "rgmii-id";
	172	};
	173
e77b28eb KG	174	enet2: ethernet@26000 {
e77b28eb KG	175	cell-index = <2>;
5d54ddcb KG	176	device_type = "network";
	177	model = "eTSEC";
	178	compatible = "gianfar";
32f960e9	179	reg = <0x26000 0x1000>;
5d54ddcb	180	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	181	interrupts = <31 2 32 2 33 2>;
5d54ddcb KG	182	interrupt-parent = <&mpic>;
	183	phy-handle = <&phy2>;
	184	phy-connection-type = "rgmii-id";
	185	};
	186
e77b28eb KG	187	enet3: ethernet@27000 {
e77b28eb KG	188	cell-index = <3>;
5d54ddcb KG	189	device_type = "network";
	190	model = "eTSEC";
	191	compatible = "gianfar";
32f960e9	192	reg = <0x27000 0x1000>;
5d54ddcb	193	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	194	interrupts = <37 2 38 2 39 2>;
5d54ddcb KG	195	interrupt-parent = <&mpic>;
	196	phy-handle = <&phy3>;
	197	phy-connection-type = "rgmii-id";
	198	};
	199
ea082fa9 KG	200	serial0: serial@4500 {
ea082fa9 KG	201	cell-index = <0>;
5d54ddcb KG	202	device_type = "serial";
5d54ddcb KG	203	compatible = "ns16550";
32f960e9	204	reg = <0x4500 0x100>;
5d54ddcb	205	clock-frequency = <0>;
32f960e9	206	interrupts = <42 2>;
5d54ddcb KG	207	interrupt-parent = <&mpic>;
	208	};
	209
ea082fa9 KG	210	serial1: serial@4600 {
ea082fa9 KG	211	cell-index = <1>;
5d54ddcb KG	212	device_type = "serial";
5d54ddcb KG	213	compatible = "ns16550";
32f960e9	214	reg = <0x4600 0x100>;
5d54ddcb	215	clock-frequency = <0>;
32f960e9	216	interrupts = <42 2>;
5d54ddcb KG	217	interrupt-parent = <&mpic>;
	218	};
	219
	220	global-utilities@e0000 { //global utilities block
	221	compatible = "fsl,mpc8572-guts";
32f960e9	222	reg = <0xe0000 0x1000>;
5d54ddcb KG	223	fsl,has-rstcr;
	224	};
	225
741edc49 JJ	226	msi@41600 {
	227	compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
	228	reg = <0x41600 0x80>;
	229	msi-available-ranges = <0 0x100>;
	230	interrupts = <
	231	0xe0 0
	232	0xe1 0
	233	0xe2 0
	234	0xe3 0
	235	0xe4 0
	236	0xe5 0
	237	0xe6 0
	238	0xe7 0>;
	239	interrupt-parent = <&mpic>;
	240	};
	241
5d54ddcb	242	mpic: pic@40000 {
5d54ddcb KG	243	interrupt-controller;
	244	#address-cells = <0>;
	245	#interrupt-cells = <2>;
32f960e9	246	reg = <0x40000 0x40000>;
5d54ddcb KG	247	compatible = "chrp,open-pic";
5d54ddcb KG	248	device_type = "open-pic";
5d54ddcb KG	249	};
	250	};
	251
ea082fa9 KG	252	pci0: pcie@ffe08000 {
ea082fa9 KG	253	cell-index = <0>;
5d54ddcb KG	254	compatible = "fsl,mpc8548-pcie";
	255	device_type = "pci";
	256	#interrupt-cells = <1>;
	257	#size-cells = <2>;
	258	#address-cells = <3>;
32f960e9 KG	259	reg = <0xffe08000 0x1000>;
	260	bus-range = <0 255>;
	261	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	262	0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
	263	clock-frequency = <33333333>;
5d54ddcb	264	interrupt-parent = <&mpic>;
32f960e9 KG	265	interrupts = <24 2>;
32f960e9 KG	266	interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
5d54ddcb	267	interrupt-map = <
bebfa06c	268	/* IDSEL 0x11 func 0 - PCI slot 1 */
32f960e9 KG	269	0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
	270	0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
	271	0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
	272	0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
5d54ddcb	273
bebfa06c	274	/* IDSEL 0x11 func 1 - PCI slot 1 */
32f960e9 KG	275	0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
	276	0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
	277	0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
	278	0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	279
bebfa06c KG	280	/* IDSEL 0x11 func 2 - PCI slot 1 */
32f960e9 KG	281	0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
	282	0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
	283	0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
	284	0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	285
bebfa06c KG	286	/* IDSEL 0x11 func 3 - PCI slot 1 */
32f960e9 KG	287	0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
	288	0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
	289	0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
	290	0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	291
bebfa06c KG	292	/* IDSEL 0x11 func 4 - PCI slot 1 */
32f960e9 KG	293	0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
	294	0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
	295	0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
	296	0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	297
bebfa06c KG	298	/* IDSEL 0x11 func 5 - PCI slot 1 */
32f960e9 KG	299	0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
	300	0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
	301	0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
	302	0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	303
bebfa06c KG	304	/* IDSEL 0x11 func 6 - PCI slot 1 */
32f960e9 KG	305	0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
	306	0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
	307	0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
	308	0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	309
bebfa06c KG	310	/* IDSEL 0x11 func 7 - PCI slot 1 */
32f960e9 KG	311	0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
	312	0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
	313	0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
	314	0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
bebfa06c KG	315
bebfa06c KG	316	/* IDSEL 0x12 func 0 - PCI slot 2 */
32f960e9 KG	317	0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
	318	0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
	319	0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
	320	0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
5d54ddcb	321
bebfa06c	322	/* IDSEL 0x12 func 1 - PCI slot 2 */
32f960e9 KG	323	0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
	324	0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
	325	0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
	326	0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	327
bebfa06c KG	328	/* IDSEL 0x12 func 2 - PCI slot 2 */
32f960e9 KG	329	0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
	330	0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
	331	0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
	332	0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	333
bebfa06c KG	334	/* IDSEL 0x12 func 3 - PCI slot 2 */
32f960e9 KG	335	0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
	336	0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
	337	0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
	338	0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	339
bebfa06c KG	340	/* IDSEL 0x12 func 4 - PCI slot 2 */
32f960e9 KG	341	0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
	342	0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
	343	0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
	344	0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	345
bebfa06c KG	346	/* IDSEL 0x12 func 5 - PCI slot 2 */
32f960e9 KG	347	0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
	348	0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
	349	0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
	350	0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	351
bebfa06c KG	352	/* IDSEL 0x12 func 6 - PCI slot 2 */
32f960e9 KG	353	0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
	354	0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
	355	0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
	356	0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c KG	357
bebfa06c KG	358	/* IDSEL 0x12 func 7 - PCI slot 2 */
32f960e9 KG	359	0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
	360	0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
	361	0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
	362	0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
bebfa06c	363
5d54ddcb	364	// IDSEL 0x1c USB
32f960e9 KG	365	0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
	366	0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
	367	0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
	368	0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
5d54ddcb KG	369
5d54ddcb KG	370	// IDSEL 0x1d Audio
32f960e9	371	0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
5d54ddcb KG	372
5d54ddcb KG	373	// IDSEL 0x1e Legacy
32f960e9 KG	374	0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
32f960e9 KG	375	0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
5d54ddcb KG	376
5d54ddcb KG	377	// IDSEL 0x1f IDE/SATA
32f960e9 KG	378	0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
32f960e9 KG	379	0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
5d54ddcb KG	380
	381	>;
	382
	383	pcie@0 {
32f960e9	384	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	385	#size-cells = <2>;
	386	#address-cells = <3>;
	387	device_type = "pci";
32f960e9 KG	388	ranges = <0x2000000 0x0 0x80000000
	389	0x2000000 0x0 0x80000000
	390	0x0 0x20000000
5d54ddcb	391
32f960e9 KG	392	0x1000000 0x0 0x0
	393	0x1000000 0x0 0x0
	394	0x0 0x100000>;
5d54ddcb	395	uli1575@0 {
32f960e9	396	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	397	#size-cells = <2>;
5d54ddcb KG	398	#address-cells = <3>;
32f960e9 KG	399	ranges = <0x2000000 0x0 0x80000000
	400	0x2000000 0x0 0x80000000
	401	0x0 0x20000000
5d54ddcb	402
32f960e9 KG	403	0x1000000 0x0 0x0
	404	0x1000000 0x0 0x0
	405	0x0 0x100000>;
5d54ddcb KG	406	isa@1e {
	407	device_type = "isa";
	408	#interrupt-cells = <2>;
	409	#size-cells = <1>;
	410	#address-cells = <2>;
32f960e9 KG	411	reg = <0xf000 0x0 0x0 0x0 0x0>;
	412	ranges = <0x1 0x0 0x1000000 0x0 0x0
	413	0x1000>;
5d54ddcb KG	414	interrupt-parent = <&i8259>;
	415
	416	i8259: interrupt-controller@20 {
32f960e9 KG	417	reg = <0x1 0x20 0x2
	418	0x1 0xa0 0x2
	419	0x1 0x4d0 0x2>;
5d54ddcb KG	420	interrupt-controller;
	421	device_type = "interrupt-controller";
	422	#address-cells = <0>;
	423	#interrupt-cells = <2>;
	424	compatible = "chrp,iic";
	425	interrupts = <9 2>;
	426	interrupt-parent = <&mpic>;
	427	};
	428
	429	i8042@60 {
	430	#size-cells = <0>;
	431	#address-cells = <1>;
32f960e9 KG	432	reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
32f960e9 KG	433	interrupts = <1 3 12 3>;
5d54ddcb KG	434	interrupt-parent =
	435	<&i8259>;
	436
	437	keyboard@0 {
32f960e9	438	reg = <0x0>;
5d54ddcb KG	439	compatible = "pnpPNP,303";
	440	};
	441
	442	mouse@1 {
32f960e9	443	reg = <0x1>;
5d54ddcb KG	444	compatible = "pnpPNP,f03";
	445	};
	446	};
	447
	448	rtc@70 {
	449	compatible = "pnpPNP,b00";
32f960e9	450	reg = <0x1 0x70 0x2>;
5d54ddcb KG	451	};
	452
	453	gpio@400 {
32f960e9	454	reg = <0x1 0x400 0x80>;
5d54ddcb KG	455	};
	456	};
	457	};
	458	};
	459
	460	};
	461
ea082fa9 KG	462	pci1: pcie@ffe09000 {
ea082fa9 KG	463	cell-index = <1>;
5d54ddcb KG	464	compatible = "fsl,mpc8548-pcie";
	465	device_type = "pci";
	466	#interrupt-cells = <1>;
	467	#size-cells = <2>;
	468	#address-cells = <3>;
32f960e9 KG	469	reg = <0xffe09000 0x1000>;
	470	bus-range = <0 255>;
	471	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	472	0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
	473	clock-frequency = <33333333>;
5d54ddcb	474	interrupt-parent = <&mpic>;
32f960e9 KG	475	interrupts = <26 2>;
32f960e9 KG	476	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
5d54ddcb KG	477	interrupt-map = <
5d54ddcb KG	478	/* IDSEL 0x0 */
32f960e9 KG	479	0000 0x0 0x0 0x1 &mpic 0x4 0x1
	480	0000 0x0 0x0 0x2 &mpic 0x5 0x1
	481	0000 0x0 0x0 0x3 &mpic 0x6 0x1
	482	0000 0x0 0x0 0x4 &mpic 0x7 0x1
5d54ddcb KG	483	>;
5d54ddcb KG	484	pcie@0 {
32f960e9	485	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	486	#size-cells = <2>;
	487	#address-cells = <3>;
	488	device_type = "pci";
32f960e9 KG	489	ranges = <0x2000000 0x0 0xa0000000
	490	0x2000000 0x0 0xa0000000
	491	0x0 0x20000000
5d54ddcb	492
32f960e9 KG	493	0x1000000 0x0 0x0
	494	0x1000000 0x0 0x0
	495	0x0 0x100000>;
5d54ddcb KG	496	};
	497	};
	498
ea082fa9 KG	499	pci2: pcie@ffe0a000 {
ea082fa9 KG	500	cell-index = <2>;
5d54ddcb KG	501	compatible = "fsl,mpc8548-pcie";
	502	device_type = "pci";
	503	#interrupt-cells = <1>;
	504	#size-cells = <2>;
	505	#address-cells = <3>;
32f960e9 KG	506	reg = <0xffe0a000 0x1000>;
	507	bus-range = <0 255>;
	508	ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
	509	0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
	510	clock-frequency = <33333333>;
5d54ddcb	511	interrupt-parent = <&mpic>;
32f960e9 KG	512	interrupts = <27 2>;
32f960e9 KG	513	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
5d54ddcb KG	514	interrupt-map = <
5d54ddcb KG	515	/* IDSEL 0x0 */
32f960e9 KG	516	0000 0x0 0x0 0x1 &mpic 0x0 0x1
	517	0000 0x0 0x0 0x2 &mpic 0x1 0x1
	518	0000 0x0 0x0 0x3 &mpic 0x2 0x1
	519	0000 0x0 0x0 0x4 &mpic 0x3 0x1
5d54ddcb KG	520	>;
5d54ddcb KG	521	pcie@0 {
32f960e9	522	reg = <0x0 0x0 0x0 0x0 0x0>;
5d54ddcb KG	523	#size-cells = <2>;
	524	#address-cells = <3>;
	525	device_type = "pci";
32f960e9 KG	526	ranges = <0x2000000 0x0 0xc0000000
	527	0x2000000 0x0 0xc0000000
	528	0x0 0x20000000
5d54ddcb	529
32f960e9 KG	530	0x1000000 0x0 0x0
	531	0x1000000 0x0 0x0
	532	0x0 0x100000>;
5d54ddcb KG	533	};
	534	};
	535	};