[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / boot / dts / sbc8560.dts

/*
 * SBC8560 Device Tree Source
 *
 * Copyright 2007 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "SBC8560";
	compatible = "SBC8560";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8560@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <0x20>;	// 32 bytes
			i-cache-line-size = <0x20>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;
	};

	soc@ff700000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xff700000 0x00100000>;
		reg = <0xff700000 0x00100000>;
		clock-frequency = <0>;

		memory-controller@2000 {
			compatible = "fsl,8560-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <0x12 0x2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8560-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <0x20>;	// 32 bytes
			cache-size = <0x40000>;		// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <0x10 0x2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <0x2b 0x2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;
			phy0: ethernet-phy@19 {
				interrupt-parent = <&mpic>;
				interrupts = <0x6 0x1>;
				reg = <0x19>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1a {
				interrupt-parent = <&mpic>;
				interrupts = <0x7 0x1>;
				reg = <0x1a>;
				device_type = "ethernet-phy";
			};
			phy2: ethernet-phy@1b {
				interrupt-parent = <&mpic>;
				interrupts = <0x8 0x1>;
				reg = <0x1b>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@1c {
				interrupt-parent = <&mpic>;
				interrupts = <0x8 0x1>;
				reg = <0x1c>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy0>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy1>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "chrp,open-pic";
			reg = <0x40000 0x40000>;
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x4000 0x9000 0x2000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8560-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
				clock-frequency = <165000000>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <0x2e 0x2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
			};

			enet2: ethernet@91320 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x16200300>;
				interrupts = <0x21 0x8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy2>;
			};

			enet3: ethernet@91340 {
				device_type = "network";
				compatible = "fsl,mpc8560-fcc-enet",
				             "fsl,cpm2-fcc-enet";
				reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
				local-mac-address = [ 00 00 00 00 00 00 ];
				fsl,cpm-command = <0x1a400300>;
				interrupts = <0x22 0x8>;
				interrupt-parent = <&cpmpic>;
				phy-handle = <&phy3>;
			};
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8560-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pci@ff708000 {
		cell-index = <0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
		reg = <0xff708000 0x1000>;
		clock-frequency = <66666666>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x02 */
			0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
			0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
			0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
			0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <0x18 0x2>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	};

	localbus@ff705000 {
		compatible = "fsl,mpc8560-localbus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <0xff705000 0x100>;	// BRx, ORx, etc.

		ranges = <
			0x0 0x0 0xff800000 0x0800000	// 8MB boot flash
			0x1 0x0 0xe4000000 0x4000000	// 64MB flash
			0x3 0x0 0x20000000 0x4000000	// 64MB SDRAM
			0x4 0x0 0x24000000 0x4000000	// 64MB SDRAM
			0x5 0x0 0xfc000000 0x0c00000	// EPLD
			0x6 0x0 0xe0000000 0x4000000	// 64MB flash
			0x7 0x0 0x80000000 0x0200000	// ATM1,2
		>;

		epld@5,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <0x5 0x0 0xc00000>;
			ranges = <
				0x0 0x0 0x5 0x000000 0x1fff	// LED disp.
				0x1 0x0 0x5 0x100000 0x1fff	// switches
				0x2 0x0 0x5 0x200000 0x1fff	// ID reg.
				0x3 0x0 0x5 0x300000 0x1fff	// status reg.
				0x4 0x0 0x5 0x400000 0x1fff	// reset reg.
				0x5 0x0 0x5 0x500000 0x1fff	// Wind port
				0x7 0x0 0x5 0x700000 0x1fff	// UART #1
				0x8 0x0 0x5 0x800000 0x1fff	// UART #2
				0x9 0x0 0x5 0x900000 0x1fff	// RTC
				0xb 0x0 0x5 0xb00000 0x1fff	// EEPROM
			>;

			bidr@2,0 {
				compatible = "wrs,sbc8560-bidr";
				reg = <0x2 0x0 0x10>;
			};

			bcsr@3,0 {
				compatible = "wrs,sbc8560-bcsr";
				reg = <0x3 0x0 0x10>;
			};

			brstcr@4,0 {
				compatible = "wrs,sbc8560-brstcr";
				reg = <0x4 0x0 0x10>;
			};

			serial0: serial@7,0 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x7 0x0 0x100>;
				clock-frequency = <1843200>;
				interrupts = <0x9 0x2>;
				interrupt-parent = <&mpic>;
			};

			serial1: serial@8,0 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <0x8 0x0 0x100>;
				clock-frequency = <1843200>;
				interrupts = <0xa 0x2>;
				interrupt-parent = <&mpic>;
			};

			rtc@9,0 {
				compatible = "m48t59";
				reg = <0x9 0x0 0x1fff>;
			};
		};
	};
};
Commit	Line	Data
6a35b6f0 PG	1	/*
	2	* SBC8560 Device Tree Source
	3	*
	4	* Copyright 2007 Wind River Systems Inc.
	5	*
	6	* Paul Gortmaker (see MAINTAINERS for contact information)
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13
	14	/dts-v1/;
	15
	16	/ {
	17	model = "SBC8560";
	18	compatible = "SBC8560";
	19	#address-cells = <1>;
	20	#size-cells = <1>;
	21
	22	aliases {
	23	ethernet0 = &enet0;
	24	ethernet1 = &enet1;
	25	ethernet2 = &enet2;
	26	ethernet3 = &enet3;
	27	serial0 = &serial0;
	28	serial1 = &serial1;
	29	pci0 = &pci0;
	30	};
	31
	32	cpus {
	33	#address-cells = <1>;
	34	#size-cells = <0>;
	35
	36	PowerPC,8560@0 {
	37	device_type = "cpu";
	38	reg = <0>;
	39	d-cache-line-size = <0x20>; // 32 bytes
	40	i-cache-line-size = <0x20>; // 32 bytes
	41	d-cache-size = <0x8000>; // L1, 32K
	42	i-cache-size = <0x8000>; // L1, 32K
	43	timebase-frequency = <0>; // From uboot
	44	bus-frequency = <0>;
	45	clock-frequency = <0>;
c054065b	46	next-level-cache = <&L2>;
6a35b6f0 PG	47	};
	48	};
	49
	50	memory {
	51	device_type = "memory";
	52	reg = <0x00000000 0x20000000>;
	53	};
	54
	55	soc@ff700000 {
	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	device_type = "soc";
	59	ranges = <0x0 0xff700000 0x00100000>;
	60	reg = <0xff700000 0x00100000>;
	61	clock-frequency = <0>;
	62
	63	memory-controller@2000 {
	64	compatible = "fsl,8560-memory-controller";
	65	reg = <0x2000 0x1000>;
	66	interrupt-parent = <&mpic>;
	67	interrupts = <0x12 0x2>;
	68	};
	69
c054065b	70	L2: l2-cache-controller@20000 {
6a35b6f0 PG	71	compatible = "fsl,8560-l2-cache-controller";
	72	reg = <0x20000 0x1000>;
	73	cache-line-size = <0x20>; // 32 bytes
	74	cache-size = <0x40000>; // L2, 256K
	75	interrupt-parent = <&mpic>;
	76	interrupts = <0x10 0x2>;
	77	};
	78
	79	i2c@3000 {
	80	#address-cells = <1>;
	81	#size-cells = <0>;
	82	cell-index = <0>;
	83	compatible = "fsl-i2c";
	84	reg = <0x3000 0x100>;
	85	interrupts = <0x2b 0x2>;
	86	interrupt-parent = <&mpic>;
	87	dfsrr;
	88	};
	89
	90	i2c@3100 {
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	cell-index = <1>;
	94	compatible = "fsl-i2c";
	95	reg = <0x3100 0x100>;
	96	interrupts = <0x2b 0x2>;
	97	interrupt-parent = <&mpic>;
	98	dfsrr;
	99	};
	100
	101	mdio@24520 {
	102	#address-cells = <1>;
	103	#size-cells = <0>;
	104	compatible = "fsl,gianfar-mdio";
	105	reg = <0x24520 0x20>;
	106	phy0: ethernet-phy@19 {
	107	interrupt-parent = <&mpic>;
	108	interrupts = <0x6 0x1>;
	109	reg = <0x19>;
	110	device_type = "ethernet-phy";
	111	};
	112	phy1: ethernet-phy@1a {
	113	interrupt-parent = <&mpic>;
	114	interrupts = <0x7 0x1>;
	115	reg = <0x1a>;
	116	device_type = "ethernet-phy";
	117	};
	118	phy2: ethernet-phy@1b {
	119	interrupt-parent = <&mpic>;
	120	interrupts = <0x8 0x1>;
	121	reg = <0x1b>;
	122	device_type = "ethernet-phy";
	123	};
	124	phy3: ethernet-phy@1c {
	125	interrupt-parent = <&mpic>;
	126	interrupts = <0x8 0x1>;
	127	reg = <0x1c>;
	128	device_type = "ethernet-phy";
	129	};
	130	};
	131
	132	enet0: ethernet@24000 {
	133	cell-index = <0>;
	134	device_type = "network";
135	model = "TSEC";
136	compatible = "gianfar";
137	reg = <0x24000 0x1000>;
138	local-mac-address = [ 00 00 00 00 00 00 ];
139	interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
140	interrupt-parent = <&mpic>;
141	phy-handle = <&phy0>;
142	};
143
144	enet1: ethernet@25000 {
145	cell-index = <1>;
146	device_type = "network";
147	model = "TSEC";
148	compatible = "gianfar";
149	reg = <0x25000 0x1000>;
150	local-mac-address = [ 00 00 00 00 00 00 ];
151	interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
152	interrupt-parent = <&mpic>;
153	phy-handle = <&phy1>;
154	};
155
156	mpic: pic@40000 {
157	interrupt-controller;
158	#address-cells = <0>;
6a35b6f0	159	#interrupt-cells = <2>;
acd4b715	160	compatible = "chrp,open-pic";
6a35b6f0 PG	161	reg = <0x40000 0x40000>;
	162	device_type = "open-pic";
	163	};
	164
	165	cpm@919c0 {
	166	#address-cells = <1>;
	167	#size-cells = <1>;
	168	compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
	169	reg = <0x919c0 0x30>;
	170	ranges;
	171
	172	muram@80000 {
	173	#address-cells = <1>;
	174	#size-cells = <1>;
	175	ranges = <0x0 0x80000 0x10000>;
	176
	177	data@0 {
	178	compatible = "fsl,cpm-muram-data";
	179	reg = <0x0 0x4000 0x9000 0x2000>;
	180	};
	181	};
	182
	183	brg@919f0 {
	184	compatible = "fsl,mpc8560-brg",
	185	"fsl,cpm2-brg",
	186	"fsl,cpm-brg";
	187	reg = <0x919f0 0x10 0x915f0 0x10>;
	188	clock-frequency = <165000000>;
	189	};
	190
	191	cpmpic: pic@90c00 {
	192	interrupt-controller;
	193	#address-cells = <0>;
	194	#interrupt-cells = <2>;
	195	interrupts = <0x2e 0x2>;
	196	interrupt-parent = <&mpic>;
	197	reg = <0x90c00 0x80>;
	198	compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
	199	};
	200
	201	enet2: ethernet@91320 {
	202	device_type = "network";
	203	compatible = "fsl,mpc8560-fcc-enet",
	204	"fsl,cpm2-fcc-enet";
	205	reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
	206	local-mac-address = [ 00 00 00 00 00 00 ];
	207	fsl,cpm-command = <0x16200300>;
	208	interrupts = <0x21 0x8>;
	209	interrupt-parent = <&cpmpic>;
	210	phy-handle = <&phy2>;
	211	};
	212
	213	enet3: ethernet@91340 {
	214	device_type = "network";
	215	compatible = "fsl,mpc8560-fcc-enet",
	216	"fsl,cpm2-fcc-enet";
	217	reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
	218	local-mac-address = [ 00 00 00 00 00 00 ];
	219	fsl,cpm-command = <0x1a400300>;
	220	interrupts = <0x22 0x8>;
	221	interrupt-parent = <&cpmpic>;
	222	phy-handle = <&phy3>;
	223	};
	224	};
225
226	global-utilities@e0000 {
227	compatible = "fsl,mpc8560-guts";
228	reg = <0xe0000 0x1000>;
229	fsl,has-rstcr;
230	};
231	};
232
233	pci0: pci@ff708000 {
234	cell-index = <0>;
235	#interrupt-cells = <1>;
236	#size-cells = <2>;
237	#address-cells = <3>;
238	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
239	device_type = "pci";
240	reg = <0xff708000 0x1000>;
241	clock-frequency = <66666666>;
242	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
243	interrupt-map = <
244
245	/* IDSEL 0x02 */
246	0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
247	0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
248	0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
249	0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
250
251	interrupt-parent = <&mpic>;
252	interrupts = <0x18 0x2>;
253	bus-range = <0x0 0x0>;
254	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
255	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
256	};
257
258	localbus@ff705000 {
259	compatible = "fsl,mpc8560-localbus";
260	#address-cells = <2>;
261	#size-cells = <1>;
262	reg = <0xff705000 0x100>; // BRx, ORx, etc.
263
264	ranges = <
265	0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
266	0x1 0x0 0xe4000000 0x4000000 // 64MB flash
267	0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
268	0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
269	0x5 0x0 0xfc000000 0x0c00000 // EPLD
270	0x6 0x0 0xe0000000 0x4000000 // 64MB flash
271	0x7 0x0 0x80000000 0x0200000 // ATM1,2
272	>;
273
274	epld@5,0 {
275	compatible = "wrs,epld-localbus";
276	#address-cells = <2>;
277	#size-cells = <1>;
278	reg = <0x5 0x0 0xc00000>;
279	ranges = <
280	0x0 0x0 0x5 0x000000 0x1fff // LED disp.
281	0x1 0x0 0x5 0x100000 0x1fff // switches
282	0x2 0x0 0x5 0x200000 0x1fff // ID reg.
283	0x3 0x0 0x5 0x300000 0x1fff // status reg.
284	0x4 0x0 0x5 0x400000 0x1fff // reset reg.
285	0x5 0x0 0x5 0x500000 0x1fff // Wind port
286	0x7 0x0 0x5 0x700000 0x1fff // UART #1
287	0x8 0x0 0x5 0x800000 0x1fff // UART #2
288	0x9 0x0 0x5 0x900000 0x1fff // RTC
289	0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
290	>;
291
292	bidr@2,0 {
293	compatible = "wrs,sbc8560-bidr";
294	reg = <0x2 0x0 0x10>;
295	};
296
297	bcsr@3,0 {
298	compatible = "wrs,sbc8560-bcsr";
299	reg = <0x3 0x0 0x10>;
300	};
301
302	brstcr@4,0 {
303	compatible = "wrs,sbc8560-brstcr";
304	reg = <0x4 0x0 0x10>;
305	};
306
307	serial0: serial@7,0 {
308	device_type = "serial";
309	compatible = "ns16550";
310	reg = <0x7 0x0 0x100>;
311	clock-frequency = <1843200>;
312	interrupts = <0x9 0x2>;
313	interrupt-parent = <&mpic>;
314	};
315
316	serial1: serial@8,0 {
317	device_type = "serial";
318	compatible = "ns16550";
319	reg = <0x8 0x0 0x100>;
320	clock-frequency = <1843200>;
321	interrupts = <0xa 0x2>;
322	interrupt-parent = <&mpic>;
323	};
324
325	rtc@9,0 {
326	compatible = "m48t59";
327	reg = <0x9 0x0 0x1fff>;
328	};
329	};
330	};
331	};