[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / include / asm / bitops.h

/*
 * PowerPC atomic bit operations.
 *
 * Merged version by David Gibson <david@gibson.dropbear.id.au>.
 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
 * originally took it from the ppc32 code.
 *
 * Within a word, bits are numbered LSB first.  Lot's of places make
 * this assumption by directly testing bits with (val & (1<<nr)).
 * This can cause confusion for large (> 1 word) bitmaps on a
 * big-endian system because, unlike little endian, the number of each
 * bit depends on the word size.
 *
 * The bitop functions are defined to work on unsigned longs, so for a
 * ppc64 system the bits end up numbered:
 *   |63..............0|127............64|191...........128|255...........192|
 * and on ppc32:
 *   |31.....0|63....32|95....64|127...96|159..128|191..160|223..192|255..224|
 *
 * There are a few little-endian macros used mostly for filesystem
 * bitmaps, these work on similar bit arrays layouts, but
 * byte-oriented:
 *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
 *
 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
 * number field needs to be reversed compared to the big-endian bit
 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _ASM_POWERPC_BITOPS_H
#define _ASM_POWERPC_BITOPS_H

#ifdef __KERNEL__

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <asm/asm-compat.h>
#include <asm/synch.h>

/* PPC bit number conversion */
#define PPC_BITLSHIFT(be)	(BITS_PER_LONG - 1 - (be))
#define PPC_BIT(bit)		(1UL << PPC_BITLSHIFT(bit))
#define PPC_BITMASK(bs, be)	((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))

/* Put a PPC bit into a "normal" bit position */
#define PPC_BITEXTRACT(bits, ppc_bit, dst_bit)			\
	((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit))

#define PPC_BITLSHIFT32(be)	(32 - 1 - (be))
#define PPC_BIT32(bit)		(1UL << PPC_BITLSHIFT32(bit))
#define PPC_BITMASK32(bs, be)	((PPC_BIT32(bs) - PPC_BIT32(be))|PPC_BIT32(bs))

#define PPC_BITLSHIFT8(be)	(8 - 1 - (be))
#define PPC_BIT8(bit)		(1UL << PPC_BITLSHIFT8(bit))
#define PPC_BITMASK8(bs, be)	((PPC_BIT8(bs) - PPC_BIT8(be))|PPC_BIT8(bs))

#include <asm/barrier.h>

/* Macro for generating the ***_bits() functions */
#define DEFINE_BITOP(fn, op, prefix)		\
static __inline__ void fn(unsigned long mask,	\
		volatile unsigned long *_p)	\
{						\
	unsigned long old;			\
	unsigned long *p = (unsigned long *)_p;	\
	__asm__ __volatile__ (			\
	prefix					\
"1:"	PPC_LLARX(%0,0,%3,0) "\n"		\
	stringify_in_c(op) "%0,%0,%2\n"		\
	PPC405_ERR77(0,%3)			\
	PPC_STLCX "%0,0,%3\n"			\
	"bne- 1b\n"				\
	: "=&r" (old), "+m" (*p)		\
	: "r" (mask), "r" (p)			\
	: "cc", "memory");			\
}

DEFINE_BITOP(set_bits, or, "")
DEFINE_BITOP(clear_bits, andc, "")
DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER)
DEFINE_BITOP(change_bits, xor, "")

static __inline__ void set_bit(int nr, volatile unsigned long *addr)
{
	set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
}

static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
{
	clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
}

static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
{
	clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr));
}

static __inline__ void change_bit(int nr, volatile unsigned long *addr)
{
	change_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
}

/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
 * operands. */
#define DEFINE_TESTOP(fn, op, prefix, postfix, eh)	\
static __inline__ unsigned long fn(			\
		unsigned long mask,			\
		volatile unsigned long *_p)		\
{							\
	unsigned long old, t;				\
	unsigned long *p = (unsigned long *)_p;		\
	__asm__ __volatile__ (				\
	prefix						\
"1:"	PPC_LLARX(%0,0,%3,eh) "\n"			\
	stringify_in_c(op) "%1,%0,%2\n"			\
	PPC405_ERR77(0,%3)				\
	PPC_STLCX "%1,0,%3\n"				\
	"bne- 1b\n"					\
	postfix						\
	: "=&r" (old), "=&r" (t)			\
	: "r" (mask), "r" (p)				\
	: "cc", "memory");				\
	return (old & mask);				\
}

DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
	      PPC_ATOMIC_EXIT_BARRIER, 0)
DEFINE_TESTOP(test_and_set_bits_lock, or, "",
	      PPC_ACQUIRE_BARRIER, 1)
DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
	      PPC_ATOMIC_EXIT_BARRIER, 0)
DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
	      PPC_ATOMIC_EXIT_BARRIER, 0)

static __inline__ int test_and_set_bit(unsigned long nr,
				       volatile unsigned long *addr)
{
	return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
}

static __inline__ int test_and_set_bit_lock(unsigned long nr,
				       volatile unsigned long *addr)
{
	return test_and_set_bits_lock(BIT_MASK(nr),
				addr + BIT_WORD(nr)) != 0;
}

static __inline__ int test_and_clear_bit(unsigned long nr,
					 volatile unsigned long *addr)
{
	return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
}

static __inline__ int test_and_change_bit(unsigned long nr,
					  volatile unsigned long *addr)
{
	return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
}

#ifdef CONFIG_PPC64
static __inline__ unsigned long clear_bit_unlock_return_word(int nr,
						volatile unsigned long *addr)
{
	unsigned long old, t;
	unsigned long *p = (unsigned long *)addr + BIT_WORD(nr);
	unsigned long mask = BIT_MASK(nr);

	__asm__ __volatile__ (
	PPC_RELEASE_BARRIER
"1:"	PPC_LLARX(%0,0,%3,0) "\n"
	"andc %1,%0,%2\n"
	PPC405_ERR77(0,%3)
	PPC_STLCX "%1,0,%3\n"
	"bne- 1b\n"
	: "=&r" (old), "=&r" (t)
	: "r" (mask), "r" (p)
	: "cc", "memory");

	return old;
}

/* This is a special function for mm/filemap.c */
#define clear_bit_unlock_is_negative_byte(nr, addr)			\
	(clear_bit_unlock_return_word(nr, addr) & BIT_MASK(PG_waiters))

#endif /* CONFIG_PPC64 */

#include <asm-generic/bitops/non-atomic.h>

static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
{
	__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
	__clear_bit(nr, addr);
}

/*
 * Return the zero-based bit position (LE, not IBM bit numbering) of
 * the most significant 1-bit in a double word.
 */
static __inline__ __attribute__((const))
int __ilog2(unsigned long x)
{
	int lz;

	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
	return BITS_PER_LONG - 1 - lz;
}

static inline __attribute__((const))
int __ilog2_u32(u32 n)
{
	int bit;
	asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
	return 31 - bit;
}

#ifdef __powerpc64__
static inline __attribute__((const))
int __ilog2_u64(u64 n)
{
	int bit;
	asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
	return 63 - bit;
}
#endif

/*
 * Determines the bit position of the least significant 0 bit in the
 * specified double word. The returned bit position will be
 * zero-based, starting from the right side (63/31 - 0).
 */
static __inline__ unsigned long ffz(unsigned long x)
{
	/* no zero exists anywhere in the 8 byte area. */
	if ((x = ~x) == 0)
		return BITS_PER_LONG;

	/*
	 * Calculate the bit position of the least significant '1' bit in x
	 * (since x has been changed this will actually be the least significant
	 * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
	 * is the least significant * (RIGHT-most) 1-bit of the value in x.
	 */
	return __ilog2(x & -x);
}

#include <asm-generic/bitops/builtin-__ffs.h>

#include <asm-generic/bitops/builtin-ffs.h>

/*
 * fls: find last (most-significant) bit set.
 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
 */
static __inline__ int fls(unsigned int x)
{
	int lz;

	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
	return 32 - lz;
}

static __inline__ unsigned long __fls(unsigned long x)
{
	return __ilog2(x);
}

/*
 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
 * instruction; for 32-bit we use the generic version, which does two
 * 32-bit fls calls.
 */
#ifdef __powerpc64__
static __inline__ int fls64(__u64 x)
{
	int lz;

	asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
	return 64 - lz;
}
#else
#include <asm-generic/bitops/fls64.h>
#endif /* __powerpc64__ */

#ifdef CONFIG_PPC64
unsigned int __arch_hweight8(unsigned int w);
unsigned int __arch_hweight16(unsigned int w);
unsigned int __arch_hweight32(unsigned int w);
unsigned long __arch_hweight64(__u64 w);
#include <asm-generic/bitops/const_hweight.h>
#else
#include <asm-generic/bitops/hweight.h>
#endif

#include <asm-generic/bitops/find.h>

/* Little-endian versions */
#include <asm-generic/bitops/le.h>

/* Bitmap functions for the ext2 filesystem */

#include <asm-generic/bitops/ext2-atomic-setbit.h>

#include <asm-generic/bitops/sched.h>

#endif /* __KERNEL__ */

#endif /* _ASM_POWERPC_BITOPS_H */
Commit	Line	Data
a0e60b20 DG	1	/*
	2	* PowerPC atomic bit operations.
	3	*
	4	* Merged version by David Gibson <david@gibson.dropbear.id.au>.
	5	* Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
	6	* Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
	7	* originally took it from the ppc32 code.
	8	*
	9	* Within a word, bits are numbered LSB first. Lot's of places make
	10	* this assumption by directly testing bits with (val & (1<<nr)).
	11	* This can cause confusion for large (> 1 word) bitmaps on a
	12	* big-endian system because, unlike little endian, the number of each
	13	* bit depends on the word size.
	14	*
	15	* The bitop functions are defined to work on unsigned longs, so for a
	16	* ppc64 system the bits end up numbered:
e7a7a65e	17	* \|63..............0\|127............64\|191...........128\|255...........192\|
a0e60b20	18	* and on ppc32:
e7a7a65e	19	* \|31.....0\|63....32\|95....64\|127...96\|159..128\|191..160\|223..192\|255..224\|
a0e60b20 DG	20	*
	21	* There are a few little-endian macros used mostly for filesystem
	22	* bitmaps, these work on similar bit arrays layouts, but
	23	* byte-oriented:
	24	* \|7...0\|15...8\|23...16\|31...24\|39...32\|47...40\|55...48\|63...56\|
	25	*
	26	* The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
	27	* number field needs to be reversed compared to the big-endian bit
	28	* fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
	29	*
	30	* This program is free software; you can redistribute it and/or
	31	* modify it under the terms of the GNU General Public License
	32	* as published by the Free Software Foundation; either version
	33	* 2 of the License, or (at your option) any later version.
	34	*/
	35
	36	#ifndef _ASM_POWERPC_BITOPS_H
	37	#define _ASM_POWERPC_BITOPS_H
	38
	39	#ifdef __KERNEL__
	40
0624517d JS	41	#ifndef _LINUX_BITOPS_H
	42	#error only <linux/bitops.h> can be included directly
	43	#endif
	44
a0e60b20	45	#include <linux/compiler.h>
3ddfbcf1	46	#include <asm/asm-compat.h>
a0e60b20 DG	47	#include <asm/synch.h>
a0e60b20 DG	48
e22a2274 MS	49	/* PPC bit number conversion */
	50	#define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be))
	51	#define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit))
	52	#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) \| PPC_BIT(bs))
	53
7b9f71f9 NP	54	/* Put a PPC bit into a "normal" bit position */
	55	#define PPC_BITEXTRACT(bits, ppc_bit, dst_bit) \
	56	((((bits) >> PPC_BITLSHIFT(ppc_bit)) & 1) << (dst_bit))
	57
22bd64a6 BH	58	#define PPC_BITLSHIFT32(be) (32 - 1 - (be))
	59	#define PPC_BIT32(bit) (1UL << PPC_BITLSHIFT32(bit))
	60	#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be))\|PPC_BIT32(bs))
	61
	62	#define PPC_BITLSHIFT8(be) (8 - 1 - (be))
	63	#define PPC_BIT8(bit) (1UL << PPC_BITLSHIFT8(bit))
	64	#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be))\|PPC_BIT8(bs))
	65
c645073f	66	#include <asm/barrier.h>
a0e60b20	67
0d2d3e38	68	/* Macro for generating the **_bits() functions /
576be130	69	#define DEFINE_BITOP(fn, op, prefix) \
0d2d3e38 GT	70	static __inline__ void fn(unsigned long mask, \
	71	volatile unsigned long *_p) \
	72	{ \
	73	unsigned long old; \
	74	unsigned long p = (unsigned long )_p; \
	75	__asm__ __volatile__ ( \
	76	prefix \
864b9e6f	77	"1:" PPC_LLARX(%0,0,%3,0) "\n" \
0d2d3e38 GT	78	stringify_in_c(op) "%0,%0,%2\n" \
	79	PPC405_ERR77(0,%3) \
	80	PPC_STLCX "%0,0,%3\n" \
	81	"bne- 1b\n" \
0d2d3e38 GT	82	: "=&r" (old), "+m" (*p) \
	83	: "r" (mask), "r" (p) \
	84	: "cc", "memory"); \
	85	}
	86
576be130 ME	87	DEFINE_BITOP(set_bits, or, "")
	88	DEFINE_BITOP(clear_bits, andc, "")
	89	DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER)
	90	DEFINE_BITOP(change_bits, xor, "")
0d2d3e38	91
a0e60b20 DG	92	static __inline__ void set_bit(int nr, volatile unsigned long *addr)
a0e60b20 DG	93	{
2237f4f4	94	set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
a0e60b20 DG	95	}
	96
	97	static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
	98	{
2237f4f4	99	clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
a0e60b20 DG	100	}
a0e60b20 DG	101
66ffb04c NP	102	static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
66ffb04c NP	103	{
2237f4f4	104	clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr));
66ffb04c NP	105	}
66ffb04c NP	106
a0e60b20 DG	107	static __inline__ void change_bit(int nr, volatile unsigned long *addr)
a0e60b20 DG	108	{
2237f4f4	109	change_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
0d2d3e38	110	}
a0e60b20	111
0d2d3e38 GT	112	/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
0d2d3e38 GT	113	* operands. */
864b9e6f AB	114	#define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \
	115	static __inline__ unsigned long fn( \
	116	unsigned long mask, \
	117	volatile unsigned long *_p) \
	118	{ \
	119	unsigned long old, t; \
	120	unsigned long p = (unsigned long )_p; \
	121	__asm__ __volatile__ ( \
	122	prefix \
	123	"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
	124	stringify_in_c(op) "%1,%0,%2\n" \
	125	PPC405_ERR77(0,%3) \
	126	PPC_STLCX "%1,0,%3\n" \
	127	"bne- 1b\n" \
	128	postfix \
	129	: "=&r" (old), "=&r" (t) \
	130	: "r" (mask), "r" (p) \
	131	: "cc", "memory"); \
	132	return (old & mask); \
a0e60b20 DG	133	}
a0e60b20 DG	134
b97021f8 BH	135	DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
b97021f8 BH	136	PPC_ATOMIC_EXIT_BARRIER, 0)
f10e2e5b AB	137	DEFINE_TESTOP(test_and_set_bits_lock, or, "",
f10e2e5b AB	138	PPC_ACQUIRE_BARRIER, 1)
b97021f8 BH	139	DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
	140	PPC_ATOMIC_EXIT_BARRIER, 0)
	141	DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
	142	PPC_ATOMIC_EXIT_BARRIER, 0)
0d2d3e38	143
a0e60b20 DG	144	static __inline__ int test_and_set_bit(unsigned long nr,
	145	volatile unsigned long *addr)
	146	{
2237f4f4	147	return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
a0e60b20 DG	148	}
a0e60b20 DG	149
66ffb04c NP	150	static __inline__ int test_and_set_bit_lock(unsigned long nr,
	151	volatile unsigned long *addr)
	152	{
2237f4f4 AM	153	return test_and_set_bits_lock(BIT_MASK(nr),
2237f4f4 AM	154	addr + BIT_WORD(nr)) != 0;
66ffb04c NP	155	}
66ffb04c NP	156
a0e60b20 DG	157	static __inline__ int test_and_clear_bit(unsigned long nr,
	158	volatile unsigned long *addr)
	159	{
2237f4f4	160	return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
a0e60b20 DG	161	}
	162
	163	static __inline__ int test_and_change_bit(unsigned long nr,
	164	volatile unsigned long *addr)
	165	{
2237f4f4	166	return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0;
a0e60b20 DG	167	}
a0e60b20 DG	168
d11914b2 NP	169	#ifdef CONFIG_PPC64
	170	static __inline__ unsigned long clear_bit_unlock_return_word(int nr,
	171	volatile unsigned long *addr)
	172	{
	173	unsigned long old, t;
	174	unsigned long p = (unsigned long )addr + BIT_WORD(nr);
	175	unsigned long mask = BIT_MASK(nr);
	176
	177	__asm__ __volatile__ (
	178	PPC_RELEASE_BARRIER
	179	"1:" PPC_LLARX(%0,0,%3,0) "\n"
	180	"andc %1,%0,%2\n"
	181	PPC405_ERR77(0,%3)
	182	PPC_STLCX "%1,0,%3\n"
	183	"bne- 1b\n"
	184	: "=&r" (old), "=&r" (t)
	185	: "r" (mask), "r" (p)
	186	: "cc", "memory");
	187
	188	return old;
	189	}
	190
	191	/* This is a special function for mm/filemap.c */
	192	#define clear_bit_unlock_is_negative_byte(nr, addr) \
	193	(clear_bit_unlock_return_word(nr, addr) & BIT_MASK(PG_waiters))
	194
	195	#endif /* CONFIG_PPC64 */
	196
e779b2f9	197	#include <asm-generic/bitops/non-atomic.h>
a0e60b20	198
66ffb04c NP	199	static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
66ffb04c NP	200	{
f10e2e5b	201	__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
66ffb04c NP	202	__clear_bit(nr, addr);
	203	}
	204
a0e60b20 DG	205	/*
	206	* Return the zero-based bit position (LE, not IBM bit numbering) of
	207	* the most significant 1-bit in a double word.
	208	*/
ef55d53c DH	209	static __inline__ __attribute__((const))
ef55d53c DH	210	int __ilog2(unsigned long x)
a0e60b20 DG	211	{
	212	int lz;
	213
3ddfbcf1	214	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
a0e60b20 DG	215	return BITS_PER_LONG - 1 - lz;
	216	}
	217
ef55d53c DH	218	static inline __attribute__((const))
	219	int __ilog2_u32(u32 n)
	220	{
	221	int bit;
	222	asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
	223	return 31 - bit;
	224	}
	225
	226	#ifdef __powerpc64__
	227	static inline __attribute__((const))
02241696	228	int __ilog2_u64(u64 n)
ef55d53c DH	229	{
	230	int bit;
	231	asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
	232	return 63 - bit;
	233	}
	234	#endif
	235
a0e60b20 DG	236	/*
	237	* Determines the bit position of the least significant 0 bit in the
	238	* specified double word. The returned bit position will be
	239	* zero-based, starting from the right side (63/31 - 0).
	240	*/
	241	static __inline__ unsigned long ffz(unsigned long x)
	242	{
	243	/* no zero exists anywhere in the 8 byte area. */
	244	if ((x = ~x) == 0)
	245	return BITS_PER_LONG;
	246
	247	/*
25985edc LDM	248	* Calculate the bit position of the least significant '1' bit in x
25985edc LDM	249	* (since x has been changed this will actually be the least significant
a0e60b20 DG	250	* '0' bit in * the original x). Note: (x & -x) gives us a mask that
	251	* is the least significant * (RIGHT-most) 1-bit of the value in x.
	252	*/
	253	return __ilog2(x & -x);
	254	}
	255
f83647d6	256	#include <asm-generic/bitops/builtin-__ffs.h>
a0e60b20	257
f83647d6	258	#include <asm-generic/bitops/builtin-ffs.h>
a0e60b20 DG	259
	260	/*
	261	* fls: find last (most-significant) bit set.
	262	* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
	263	*/
	264	static __inline__ int fls(unsigned int x)
	265	{
	266	int lz;
	267
	268	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
	269	return 32 - lz;
	270	}
9f264be6	271
56a6b1eb AH	272	static __inline__ unsigned long __fls(unsigned long x)
	273	{
	274	return __ilog2(x);
	275	}
	276
9f264be6 PM	277	/*
	278	* 64-bit can do this using one cntlzd (count leading zeroes doubleword)
	279	* instruction; for 32-bit we use the generic version, which does two
	280	* 32-bit fls calls.
	281	*/
	282	#ifdef __powerpc64__
	283	static __inline__ int fls64(__u64 x)
	284	{
	285	int lz;
	286
	287	asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
	288	return 64 - lz;
	289	}
	290	#else
e779b2f9	291	#include <asm-generic/bitops/fls64.h>
9f264be6 PM	292	#endif /* __powerpc64__ */
9f264be6 PM	293
64ff3128 AB	294	#ifdef CONFIG_PPC64
	295	unsigned int __arch_hweight8(unsigned int w);
	296	unsigned int __arch_hweight16(unsigned int w);
	297	unsigned int __arch_hweight32(unsigned int w);
	298	unsigned long __arch_hweight64(__u64 w);
	299	#include <asm-generic/bitops/const_hweight.h>
	300	#else
e779b2f9	301	#include <asm-generic/bitops/hweight.h>
64ff3128 AB	302	#endif
64ff3128 AB	303
47b9d9bd	304	#include <asm-generic/bitops/find.h>
a0e60b20 DG	305
a0e60b20 DG	306	/* Little-endian versions */
79597be9	307	#include <asm-generic/bitops/le.h>
a0e60b20	308
a0e60b20 DG	309	/* Bitmap functions for the ext2 filesystem */
a0e60b20 DG	310
148817ba	311	#include <asm-generic/bitops/ext2-atomic-setbit.h>
a0e60b20	312
e779b2f9	313	#include <asm-generic/bitops/sched.h>
a0e60b20 DG	314
	315	#endif /* __KERNEL__ */
	316
	317	#endif /* _ASM_POWERPC_BITOPS_H */