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11a6f6ab AK |
1 | #ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ |
2 | #define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ | |
8d2169e8 DG |
3 | /* |
4 | * PowerPC64 memory management structures | |
5 | * | |
6 | * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> | |
7 | * PPC64 rework. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <asm/asm-compat.h> | |
16 | #include <asm/page.h> | |
891121e6 | 17 | #include <asm/bug.h> |
8d2169e8 | 18 | |
78f1dbde AK |
19 | /* |
20 | * This is necessary to get the definition of PGTABLE_RANGE which we | |
21 | * need for various slices related matters. Note that this isn't the | |
22 | * complete pgtable.h but only a portion of it. | |
23 | */ | |
3dfcb315 | 24 | #include <asm/book3s/64/pgtable.h> |
cf9427b8 | 25 | #include <asm/bug.h> |
dad6f37c | 26 | #include <asm/processor.h> |
78f1dbde | 27 | |
8d2169e8 DG |
28 | /* |
29 | * SLB | |
30 | */ | |
31 | ||
32 | #define SLB_NUM_BOLTED 3 | |
33 | #define SLB_CACHE_ENTRIES 8 | |
46db2f86 | 34 | #define SLB_MIN_SIZE 32 |
8d2169e8 DG |
35 | |
36 | /* Bits in the SLB ESID word */ | |
37 | #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ | |
38 | ||
39 | /* Bits in the SLB VSID word */ | |
40 | #define SLB_VSID_SHIFT 12 | |
1189be65 PM |
41 | #define SLB_VSID_SHIFT_1T 24 |
42 | #define SLB_VSID_SSIZE_SHIFT 62 | |
8d2169e8 DG |
43 | #define SLB_VSID_B ASM_CONST(0xc000000000000000) |
44 | #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) | |
45 | #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) | |
46 | #define SLB_VSID_KS ASM_CONST(0x0000000000000800) | |
47 | #define SLB_VSID_KP ASM_CONST(0x0000000000000400) | |
48 | #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ | |
49 | #define SLB_VSID_L ASM_CONST(0x0000000000000100) | |
50 | #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ | |
51 | #define SLB_VSID_LP ASM_CONST(0x0000000000000030) | |
52 | #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) | |
53 | #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) | |
54 | #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) | |
55 | #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) | |
56 | #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) | |
57 | ||
58 | #define SLB_VSID_KERNEL (SLB_VSID_KP) | |
59 | #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) | |
60 | ||
61 | #define SLBIE_C (0x08000000) | |
1189be65 | 62 | #define SLBIE_SSIZE_SHIFT 25 |
8d2169e8 DG |
63 | |
64 | /* | |
65 | * Hash table | |
66 | */ | |
67 | ||
68 | #define HPTES_PER_GROUP 8 | |
69 | ||
2454c7e9 | 70 | #define HPTE_V_SSIZE_SHIFT 62 |
8d2169e8 | 71 | #define HPTE_V_AVPN_SHIFT 7 |
2454c7e9 | 72 | #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) |
8d2169e8 | 73 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) |
91bbbe22 | 74 | #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
8d2169e8 DG |
75 | #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
76 | #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) | |
77 | #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) | |
78 | #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) | |
79 | #define HPTE_V_VALID ASM_CONST(0x0000000000000001) | |
80 | ||
50de596d AK |
81 | /* |
82 | * ISA 3.0 have a different HPTE format. | |
83 | */ | |
84 | #define HPTE_R_3_0_SSIZE_SHIFT 58 | |
8d2169e8 DG |
85 | #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) |
86 | #define HPTE_R_TS ASM_CONST(0x4000000000000000) | |
de56a948 | 87 | #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) |
8d2169e8 | 88 | #define HPTE_R_RPN_SHIFT 12 |
de56a948 | 89 | #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) |
8d2169e8 | 90 | #define HPTE_R_PP ASM_CONST(0x0000000000000003) |
8550e2fa | 91 | #define HPTE_R_PPP ASM_CONST(0x8000000000000003) |
8d2169e8 | 92 | #define HPTE_R_N ASM_CONST(0x0000000000000004) |
de56a948 PM |
93 | #define HPTE_R_G ASM_CONST(0x0000000000000008) |
94 | #define HPTE_R_M ASM_CONST(0x0000000000000010) | |
95 | #define HPTE_R_I ASM_CONST(0x0000000000000020) | |
96 | #define HPTE_R_W ASM_CONST(0x0000000000000040) | |
97 | #define HPTE_R_WIMG ASM_CONST(0x0000000000000078) | |
8d2169e8 DG |
98 | #define HPTE_R_C ASM_CONST(0x0000000000000080) |
99 | #define HPTE_R_R ASM_CONST(0x0000000000000100) | |
de56a948 | 100 | #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) |
8d2169e8 | 101 | |
b7abc5c5 SS |
102 | #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) |
103 | #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) | |
104 | ||
8d2169e8 | 105 | /* Values for PP (assumes Ks=0, Kp=1) */ |
8d2169e8 DG |
106 | #define PP_RWXX 0 /* Supervisor read/write, User none */ |
107 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | |
108 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | |
109 | #define PP_RXRX 3 /* Supervisor read, User read */ | |
697d3899 | 110 | #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ |
8d2169e8 | 111 | |
b4072df4 PM |
112 | /* Fields for tlbiel instruction in architecture 2.06 */ |
113 | #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ | |
114 | #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ | |
115 | #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ | |
116 | #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ | |
117 | #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ | |
118 | #define TLBIEL_INVAL_SET_SHIFT 12 | |
119 | ||
120 | #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ | |
45706bb5 | 121 | #define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ |
c3ab300e | 122 | #define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */ |
1a472c9d | 123 | #define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */ |
b4072df4 | 124 | |
8d2169e8 DG |
125 | #ifndef __ASSEMBLY__ |
126 | ||
7025776e BH |
127 | struct mmu_hash_ops { |
128 | void (*hpte_invalidate)(unsigned long slot, | |
129 | unsigned long vpn, | |
130 | int bpsize, int apsize, | |
131 | int ssize, int local); | |
132 | long (*hpte_updatepp)(unsigned long slot, | |
133 | unsigned long newpp, | |
134 | unsigned long vpn, | |
135 | int bpsize, int apsize, | |
136 | int ssize, unsigned long flags); | |
137 | void (*hpte_updateboltedpp)(unsigned long newpp, | |
138 | unsigned long ea, | |
139 | int psize, int ssize); | |
140 | long (*hpte_insert)(unsigned long hpte_group, | |
141 | unsigned long vpn, | |
142 | unsigned long prpn, | |
143 | unsigned long rflags, | |
144 | unsigned long vflags, | |
145 | int psize, int apsize, | |
146 | int ssize); | |
147 | long (*hpte_remove)(unsigned long hpte_group); | |
148 | int (*hpte_removebolted)(unsigned long ea, | |
149 | int psize, int ssize); | |
150 | void (*flush_hash_range)(unsigned long number, int local); | |
151 | void (*hugepage_invalidate)(unsigned long vsid, | |
152 | unsigned long addr, | |
153 | unsigned char *hpte_slot_array, | |
154 | int psize, int ssize, int local); | |
155 | /* | |
156 | * Special for kexec. | |
157 | * To be called in real mode with interrupts disabled. No locks are | |
158 | * taken as such, concurrent access on pre POWER5 hardware could result | |
159 | * in a deadlock. | |
160 | * The linear mapping is destroyed as well. | |
161 | */ | |
162 | void (*hpte_clear_all)(void); | |
163 | }; | |
164 | extern struct mmu_hash_ops mmu_hash_ops; | |
165 | ||
8e561e7e | 166 | struct hash_pte { |
12f04f2b AB |
167 | __be64 v; |
168 | __be64 r; | |
8e561e7e | 169 | }; |
8d2169e8 | 170 | |
8e561e7e | 171 | extern struct hash_pte *htab_address; |
8d2169e8 DG |
172 | extern unsigned long htab_size_bytes; |
173 | extern unsigned long htab_hash_mask; | |
174 | ||
cf9427b8 AK |
175 | |
176 | static inline int shift_to_mmu_psize(unsigned int shift) | |
177 | { | |
178 | int psize; | |
179 | ||
180 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) | |
181 | if (mmu_psize_defs[psize].shift == shift) | |
182 | return psize; | |
183 | return -1; | |
184 | } | |
185 | ||
186 | static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) | |
187 | { | |
188 | if (mmu_psize_defs[mmu_psize].shift) | |
189 | return mmu_psize_defs[mmu_psize].shift; | |
190 | BUG(); | |
191 | } | |
8d2169e8 DG |
192 | |
193 | #endif /* __ASSEMBLY__ */ | |
194 | ||
2454c7e9 PM |
195 | /* |
196 | * Segment sizes. | |
197 | * These are the values used by hardware in the B field of | |
198 | * SLB entries and the first dword of MMU hashtable entries. | |
199 | * The B field is 2 bits; the values 2 and 3 are unused and reserved. | |
200 | */ | |
201 | #define MMU_SEGSIZE_256M 0 | |
202 | #define MMU_SEGSIZE_1T 1 | |
203 | ||
5524a27d AK |
204 | /* |
205 | * encode page number shift. | |
206 | * in order to fit the 78 bit va in a 64 bit variable we shift the va by | |
207 | * 12 bits. This enable us to address upto 76 bit va. | |
208 | * For hpt hash from a va we can ignore the page size bits of va and for | |
209 | * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure | |
210 | * we work in all cases including 4k page size. | |
211 | */ | |
212 | #define VPN_SHIFT 12 | |
1189be65 | 213 | |
b1022fbd AK |
214 | /* |
215 | * HPTE Large Page (LP) details | |
216 | */ | |
217 | #define LP_SHIFT 12 | |
218 | #define LP_BITS 8 | |
219 | #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) | |
220 | ||
8d2169e8 DG |
221 | #ifndef __ASSEMBLY__ |
222 | ||
73d16a6e IM |
223 | static inline int slb_vsid_shift(int ssize) |
224 | { | |
225 | if (ssize == MMU_SEGSIZE_256M) | |
226 | return SLB_VSID_SHIFT; | |
227 | return SLB_VSID_SHIFT_1T; | |
228 | } | |
229 | ||
5524a27d AK |
230 | static inline int segment_shift(int ssize) |
231 | { | |
232 | if (ssize == MMU_SEGSIZE_256M) | |
233 | return SID_SHIFT; | |
234 | return SID_SHIFT_1T; | |
235 | } | |
236 | ||
8d2169e8 | 237 | /* |
1189be65 | 238 | * The current system page and segment sizes |
8d2169e8 | 239 | */ |
1189be65 PM |
240 | extern int mmu_kernel_ssize; |
241 | extern int mmu_highuser_ssize; | |
584f8b71 | 242 | extern u16 mmu_slb_size; |
572fb578 | 243 | extern unsigned long tce_alloc_start, tce_alloc_end; |
8d2169e8 DG |
244 | |
245 | /* | |
246 | * If the processor supports 64k normal pages but not 64k cache | |
247 | * inhibited pages, we have to be prepared to switch processes | |
248 | * to use 4k pages when they create cache-inhibited mappings. | |
249 | * If this is the case, mmu_ci_restrictions will be set to 1. | |
250 | */ | |
251 | extern int mmu_ci_restrictions; | |
252 | ||
5524a27d AK |
253 | /* |
254 | * This computes the AVPN and B fields of the first dword of a HPTE, | |
255 | * for use when we want to match an existing PTE. The bottom 7 bits | |
256 | * of the returned value are zero. | |
257 | */ | |
258 | static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, | |
259 | int ssize) | |
260 | { | |
261 | unsigned long v; | |
262 | /* | |
263 | * The AVA field omits the low-order 23 bits of the 78 bits VA. | |
264 | * These bits are not needed in the PTE, because the | |
265 | * low-order b of these bits are part of the byte offset | |
266 | * into the virtual page and, if b < 23, the high-order | |
267 | * 23-b of these bits are always used in selecting the | |
268 | * PTEGs to be searched | |
269 | */ | |
270 | v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); | |
271 | v <<= HPTE_V_AVPN_SHIFT; | |
50de596d AK |
272 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) |
273 | v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; | |
5524a27d AK |
274 | return v; |
275 | } | |
276 | ||
8d2169e8 DG |
277 | /* |
278 | * This function sets the AVPN and L fields of the HPTE appropriately | |
b1022fbd | 279 | * using the base page size and actual page size. |
8d2169e8 | 280 | */ |
b1022fbd AK |
281 | static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, |
282 | int actual_psize, int ssize) | |
8d2169e8 | 283 | { |
1189be65 | 284 | unsigned long v; |
b1022fbd AK |
285 | v = hpte_encode_avpn(vpn, base_psize, ssize); |
286 | if (actual_psize != MMU_PAGE_4K) | |
8d2169e8 DG |
287 | v |= HPTE_V_LARGE; |
288 | return v; | |
289 | } | |
290 | ||
291 | /* | |
292 | * This function sets the ARPN, and LP fields of the HPTE appropriately | |
293 | * for the page size. We assume the pa is already "clean" that is properly | |
294 | * aligned for the requested page size | |
295 | */ | |
b1022fbd | 296 | static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, |
50de596d | 297 | int actual_psize, int ssize) |
8d2169e8 | 298 | { |
50de596d AK |
299 | |
300 | if (cpu_has_feature(CPU_FTR_ARCH_300)) | |
301 | pa |= ((unsigned long) ssize) << HPTE_R_3_0_SSIZE_SHIFT; | |
302 | ||
8d2169e8 | 303 | /* A 4K page needs no special encoding */ |
b1022fbd | 304 | if (actual_psize == MMU_PAGE_4K) |
8d2169e8 DG |
305 | return pa & HPTE_R_RPN; |
306 | else { | |
b1022fbd AK |
307 | unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; |
308 | unsigned int shift = mmu_psize_defs[actual_psize].shift; | |
309 | return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); | |
8d2169e8 | 310 | } |
8d2169e8 DG |
311 | } |
312 | ||
313 | /* | |
5524a27d | 314 | * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. |
8d2169e8 | 315 | */ |
5524a27d AK |
316 | static inline unsigned long hpt_vpn(unsigned long ea, |
317 | unsigned long vsid, int ssize) | |
1189be65 | 318 | { |
5524a27d AK |
319 | unsigned long mask; |
320 | int s_shift = segment_shift(ssize); | |
321 | ||
322 | mask = (1ul << (s_shift - VPN_SHIFT)) - 1; | |
323 | return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); | |
1189be65 | 324 | } |
8d2169e8 | 325 | |
1189be65 PM |
326 | /* |
327 | * This hashes a virtual address | |
328 | */ | |
5524a27d AK |
329 | static inline unsigned long hpt_hash(unsigned long vpn, |
330 | unsigned int shift, int ssize) | |
8d2169e8 | 331 | { |
5524a27d | 332 | int mask; |
1189be65 PM |
333 | unsigned long hash, vsid; |
334 | ||
5524a27d | 335 | /* VPN_SHIFT can be atmost 12 */ |
1189be65 | 336 | if (ssize == MMU_SEGSIZE_256M) { |
5524a27d AK |
337 | mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; |
338 | hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ | |
339 | ((vpn & mask) >> (shift - VPN_SHIFT)); | |
1189be65 | 340 | } else { |
5524a27d AK |
341 | mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; |
342 | vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); | |
343 | hash = vsid ^ (vsid << 25) ^ | |
344 | ((vpn & mask) >> (shift - VPN_SHIFT)) ; | |
1189be65 PM |
345 | } |
346 | return hash & 0x7fffffffffUL; | |
8d2169e8 DG |
347 | } |
348 | ||
aefa5688 AK |
349 | #define HPTE_LOCAL_UPDATE 0x1 |
350 | #define HPTE_NOHPTE_UPDATE 0x2 | |
351 | ||
8d2169e8 DG |
352 | extern int __hash_page_4K(unsigned long ea, unsigned long access, |
353 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 354 | unsigned long flags, int ssize, int subpage_prot); |
8d2169e8 DG |
355 | extern int __hash_page_64K(unsigned long ea, unsigned long access, |
356 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 357 | unsigned long flags, int ssize); |
8d2169e8 | 358 | struct mm_struct; |
0895ecda | 359 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); |
aefa5688 AK |
360 | extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
361 | unsigned long access, unsigned long trap, | |
362 | unsigned long flags); | |
363 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, | |
364 | unsigned long dsisr); | |
a4fe3ce7 | 365 | int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, |
aefa5688 AK |
366 | pte_t *ptep, unsigned long trap, unsigned long flags, |
367 | int ssize, unsigned int shift, unsigned int mmu_psize); | |
6d492ecc AK |
368 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
369 | extern int __hash_page_thp(unsigned long ea, unsigned long access, | |
370 | unsigned long vsid, pmd_t *pmdp, unsigned long trap, | |
aefa5688 | 371 | unsigned long flags, int ssize, unsigned int psize); |
6d492ecc AK |
372 | #else |
373 | static inline int __hash_page_thp(unsigned long ea, unsigned long access, | |
374 | unsigned long vsid, pmd_t *pmdp, | |
aefa5688 | 375 | unsigned long trap, unsigned long flags, |
6d492ecc AK |
376 | int ssize, unsigned int psize) |
377 | { | |
378 | BUG(); | |
ff1e7683 | 379 | return -1; |
6d492ecc AK |
380 | } |
381 | #endif | |
4b8692c0 BH |
382 | extern void hash_failure_debug(unsigned long ea, unsigned long access, |
383 | unsigned long vsid, unsigned long trap, | |
d8139ebf AK |
384 | int ssize, int psize, int lpsize, |
385 | unsigned long pte); | |
8d2169e8 | 386 | extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, |
bc033b63 | 387 | unsigned long pstart, unsigned long prot, |
1189be65 | 388 | int psize, int ssize); |
f6026df1 AB |
389 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
390 | int psize, int ssize); | |
41151e77 | 391 | extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); |
fa28237c | 392 | extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); |
8d2169e8 | 393 | |
8d2169e8 DG |
394 | extern void hpte_init_native(void); |
395 | extern void hpte_init_lpar(void); | |
8d2169e8 | 396 | extern void hpte_init_beat(void); |
7f2c8577 | 397 | extern void hpte_init_beat_v3(void); |
8d2169e8 | 398 | |
8d2169e8 DG |
399 | extern void slb_initialize(void); |
400 | extern void slb_flush_and_rebolt(void); | |
8d2169e8 | 401 | |
67439b76 | 402 | extern void slb_vmalloc_update(void); |
46db2f86 | 403 | extern void slb_set_size(u16 size); |
8d2169e8 DG |
404 | #endif /* __ASSEMBLY__ */ |
405 | ||
406 | /* | |
f033d659 | 407 | * VSID allocation (256MB segment) |
8d2169e8 | 408 | * |
c60ac569 AK |
409 | * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated |
410 | * from mmu context id and effective segment id of the address. | |
8d2169e8 | 411 | * |
c60ac569 AK |
412 | * For user processes max context id is limited to ((1ul << 19) - 5) |
413 | * for kernel space, we use the top 4 context ids to map address as below | |
414 | * NOTE: each context only support 64TB now. | |
415 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
416 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
417 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
418 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
8d2169e8 DG |
419 | * |
420 | * The proto-VSIDs are then scrambled into real VSIDs with the | |
421 | * multiplicative hash: | |
422 | * | |
423 | * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS | |
8d2169e8 | 424 | * |
f033d659 | 425 | * VSID_MULTIPLIER is prime, so in particular it is |
8d2169e8 DG |
426 | * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. |
427 | * Because the modulus is 2^n-1 we can compute it efficiently without | |
c60ac569 AK |
428 | * a divide or extra multiply (see below). The scramble function gives |
429 | * robust scattering in the hash table (at least based on some initial | |
430 | * results). | |
8d2169e8 | 431 | * |
c60ac569 AK |
432 | * We also consider VSID 0 special. We use VSID 0 for slb entries mapping |
433 | * bad address. This enables us to consolidate bad address handling in | |
434 | * hash_page. | |
8d2169e8 | 435 | * |
c60ac569 AK |
436 | * We also need to avoid the last segment of the last context, because that |
437 | * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 | |
438 | * because of the modulo operation in vsid scramble. But the vmemmap | |
439 | * (which is what uses region 0xf) will never be close to 64TB in size | |
440 | * (it's 56 bytes per page of system memory). | |
8d2169e8 | 441 | */ |
8d2169e8 | 442 | |
e39d1a47 | 443 | #define CONTEXT_BITS 19 |
af81d787 AK |
444 | #define ESID_BITS 18 |
445 | #define ESID_BITS_1T 6 | |
e39d1a47 | 446 | |
c60ac569 AK |
447 | /* |
448 | * 256MB segment | |
af81d787 | 449 | * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments |
c60ac569 AK |
450 | * available for user + kernel mapping. The top 4 contexts are used for |
451 | * kernel mapping. Each segment contains 2^28 bytes. Each | |
452 | * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts | |
453 | * (19 == 37 + 28 - 46). | |
454 | */ | |
455 | #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5) | |
456 | ||
048ee099 AK |
457 | /* |
458 | * This should be computed such that protovosid * vsid_mulitplier | |
459 | * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus | |
460 | */ | |
461 | #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ | |
af81d787 | 462 | #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS) |
1189be65 | 463 | #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) |
8d2169e8 | 464 | |
1189be65 | 465 | #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ |
af81d787 | 466 | #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T) |
1189be65 PM |
467 | #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) |
468 | ||
8d2169e8 | 469 | |
af81d787 | 470 | #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) |
8d2169e8 DG |
471 | |
472 | /* | |
473 | * This macro generates asm code to compute the VSID scramble | |
474 | * function. Used in slb_allocate() and do_stab_bolted. The function | |
475 | * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS | |
476 | * | |
027dfac6 | 477 | * rt = register containing the proto-VSID and into which the |
8d2169e8 DG |
478 | * VSID will be stored |
479 | * rx = scratch register (clobbered) | |
480 | * | |
481 | * - rt and rx must be different registers | |
1189be65 | 482 | * - The answer will end up in the low VSID_BITS bits of rt. The higher |
8d2169e8 DG |
483 | * bits may contain other garbage, so you may need to mask the |
484 | * result. | |
485 | */ | |
1189be65 PM |
486 | #define ASM_VSID_SCRAMBLE(rt, rx, size) \ |
487 | lis rx,VSID_MULTIPLIER_##size@h; \ | |
488 | ori rx,rx,VSID_MULTIPLIER_##size@l; \ | |
8d2169e8 DG |
489 | mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ |
490 | \ | |
1189be65 PM |
491 | srdi rx,rt,VSID_BITS_##size; \ |
492 | clrldi rt,rt,(64-VSID_BITS_##size); \ | |
8d2169e8 | 493 | add rt,rt,rx; /* add high and low bits */ \ |
c60ac569 AK |
494 | /* NOTE: explanation based on VSID_BITS_##size = 36 \ |
495 | * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ | |
8d2169e8 DG |
496 | * 2^36-1+2^28-1. That in particular means that if r3 >= \ |
497 | * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ | |
498 | * the bit clear, r3 already has the answer we want, if it \ | |
499 | * doesn't, the answer is the low 36 bits of r3+1. So in all \ | |
500 | * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ | |
501 | addi rx,rt,1; \ | |
1189be65 | 502 | srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ |
8d2169e8 DG |
503 | add rt,rt,rx |
504 | ||
78f1dbde | 505 | /* 4 bits per slice and we have one slice per 1TB */ |
dd1842a2 | 506 | #define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) |
8d2169e8 DG |
507 | |
508 | #ifndef __ASSEMBLY__ | |
509 | ||
d28513bc DG |
510 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
511 | /* | |
512 | * For the sub-page protection option, we extend the PGD with one of | |
513 | * these. Basically we have a 3-level tree, with the top level being | |
514 | * the protptrs array. To optimize speed and memory consumption when | |
515 | * only addresses < 4GB are being protected, pointers to the first | |
516 | * four pages of sub-page protection words are stored in the low_prot | |
517 | * array. | |
518 | * Each page of sub-page protection words protects 1GB (4 bytes | |
519 | * protects 64k). For the 3-level tree, each page of pointers then | |
520 | * protects 8TB. | |
521 | */ | |
522 | struct subpage_prot_table { | |
523 | unsigned long maxaddr; /* only addresses < this are protected */ | |
dad6f37c | 524 | unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; |
d28513bc DG |
525 | unsigned int *low_prot[4]; |
526 | }; | |
527 | ||
528 | #define SBP_L1_BITS (PAGE_SHIFT - 2) | |
529 | #define SBP_L2_BITS (PAGE_SHIFT - 3) | |
530 | #define SBP_L1_COUNT (1 << SBP_L1_BITS) | |
531 | #define SBP_L2_COUNT (1 << SBP_L2_BITS) | |
532 | #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) | |
533 | #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) | |
534 | ||
535 | extern void subpage_prot_free(struct mm_struct *mm); | |
536 | extern void subpage_prot_init_new_context(struct mm_struct *mm); | |
537 | #else | |
538 | static inline void subpage_prot_free(struct mm_struct *mm) {} | |
539 | static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } | |
540 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
541 | ||
8d2169e8 | 542 | #if 0 |
1189be65 PM |
543 | /* |
544 | * The code below is equivalent to this function for arguments | |
545 | * < 2^VSID_BITS, which is all this should ever be called | |
546 | * with. However gcc is not clever enough to compute the | |
547 | * modulus (2^n-1) without a second multiply. | |
548 | */ | |
34692708 | 549 | #define vsid_scramble(protovsid, size) \ |
1189be65 | 550 | ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) |
8d2169e8 | 551 | |
1189be65 PM |
552 | #else /* 1 */ |
553 | #define vsid_scramble(protovsid, size) \ | |
554 | ({ \ | |
555 | unsigned long x; \ | |
556 | x = (protovsid) * VSID_MULTIPLIER_##size; \ | |
557 | x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ | |
558 | (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ | |
559 | }) | |
8d2169e8 | 560 | #endif /* 1 */ |
8d2169e8 | 561 | |
1189be65 PM |
562 | /* Returns the segment size indicator for a user address */ |
563 | static inline int user_segment_size(unsigned long addr) | |
8d2169e8 | 564 | { |
1189be65 PM |
565 | /* Use 1T segments if possible for addresses >= 1T */ |
566 | if (addr >= (1UL << SID_SHIFT_1T)) | |
567 | return mmu_highuser_ssize; | |
568 | return MMU_SEGSIZE_256M; | |
8d2169e8 DG |
569 | } |
570 | ||
1189be65 PM |
571 | static inline unsigned long get_vsid(unsigned long context, unsigned long ea, |
572 | int ssize) | |
573 | { | |
c60ac569 AK |
574 | /* |
575 | * Bad address. We return VSID 0 for that | |
576 | */ | |
dd1842a2 | 577 | if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE) |
c60ac569 AK |
578 | return 0; |
579 | ||
1189be65 | 580 | if (ssize == MMU_SEGSIZE_256M) |
af81d787 | 581 | return vsid_scramble((context << ESID_BITS) |
1189be65 | 582 | | (ea >> SID_SHIFT), 256M); |
af81d787 | 583 | return vsid_scramble((context << ESID_BITS_1T) |
1189be65 PM |
584 | | (ea >> SID_SHIFT_1T), 1T); |
585 | } | |
586 | ||
c60ac569 AK |
587 | /* |
588 | * This is only valid for addresses >= PAGE_OFFSET | |
589 | * | |
590 | * For kernel space, we use the top 4 context ids to map address as below | |
591 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
592 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
593 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
594 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
595 | */ | |
596 | static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) | |
597 | { | |
598 | unsigned long context; | |
599 | ||
600 | /* | |
601 | * kernel take the top 4 context from the available range | |
602 | */ | |
603 | context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1; | |
604 | return get_vsid(context, ea, ssize); | |
605 | } | |
5c3c7ede DG |
606 | |
607 | unsigned htab_shift_for_mem_size(unsigned long mem_size); | |
608 | ||
8d2169e8 DG |
609 | #endif /* __ASSEMBLY__ */ |
610 | ||
11a6f6ab | 611 | #endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */ |