[mirror_ubuntu-artful-kernel.git] / arch / powerpc / include / asm / book3s / 64 / mmu.h

#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
#define _ASM_POWERPC_BOOK3S_64_MMU_H_

#ifndef __ASSEMBLY__
/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def {
	unsigned int	shift;	/* number of bits */
	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	union {
		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */
	};
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#endif /* __ASSEMBLY__ */

/* 64-bit classic hash table MMU */
#include <asm/book3s/64/mmu-hash.h>

#ifndef __ASSEMBLY__
/*
 * ISA 3.0 partition and process table entry format
 */
struct prtb_entry {
	__be64 prtb0;
	__be64 prtb1;
};
extern struct prtb_entry *process_tb;

struct patb_entry {
	__be64 patb0;
	__be64 patb1;
};
extern struct patb_entry *partition_tb;

/* Bits in patb0 field */
#define PATB_HR		(1UL << 63)
#define RPDB_MASK	0x0fffffffffffff00UL
#define RPDB_SHIFT	(1UL << 8)
#define RTS1_SHIFT	61		/* top 2 bits of radix tree size */
#define RTS1_MASK	(3UL << RTS1_SHIFT)
#define RTS2_SHIFT	5		/* bottom 3 bits of radix tree size */
#define RTS2_MASK	(7UL << RTS2_SHIFT)
#define RPDS_MASK	0x1f		/* root page dir. size field */

/* Bits in patb1 field */
#define PATB_GR		(1UL << 63)	/* guest uses radix; must match HR */
#define PRTS_MASK	0x1f		/* process table size field */
#define PRTB_MASK	0x0ffffffffffff000UL

/*
 * Limit process table to PAGE_SIZE table. This
 * also limit the max pid we can support.
 * MAX_USER_CONTEXT * 16 bytes of space.
 */
#define PRTB_SIZE_SHIFT	(CONTEXT_BITS + 4)
#define PRTB_ENTRIES	(1ul << CONTEXT_BITS)

/*
 * Power9 currently only support 64K partition table size.
 */
#define PATB_SIZE_SHIFT	16

typedef unsigned long mm_context_id_t;
struct spinlock;

/* Maximum possible number of NPUs in a system. */
#define NV_MAX_NPUS 8

typedef struct {
	mm_context_id_t id;
	u16 user_psize;		/* page size index */

	/* NPU NMMU context */
	struct npu_context *npu_context;

#ifdef CONFIG_PPC_MM_SLICES
	u64 low_slices_psize;	/* SLB page size encodings */
	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
	unsigned long addr_limit;
#else
	u16 sllp;		/* SLB page size encoding */
#endif
	unsigned long vdso_base;
#ifdef CONFIG_PPC_SUBPAGE_PROT
	struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
#ifdef CONFIG_PPC_ICSWX
	struct spinlock *cop_lockp; /* guard acop and cop_pid */
	unsigned long acop;	/* mask of enabled coprocessor types */
	unsigned int cop_pid;	/* pid value used with coprocessors */
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_64K_PAGES
	/* for 4K PTE fragment support */
	void *pte_frag;
#endif
#ifdef CONFIG_SPAPR_TCE_IOMMU
	struct list_head iommu_group_mem_list;
#endif
} mm_context_t;

/*
 * The current system page and segment sizes
 */
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_vmemmap_psize;
extern int mmu_io_psize;

/* MMU initialization */
void mmu_early_init_devtree(void);
void hash__early_init_devtree(void);
void radix__early_init_devtree(void);
extern void radix_init_native(void);
extern void hash__early_init_mmu(void);
extern void radix__early_init_mmu(void);
static inline void early_init_mmu(void)
{
	if (radix_enabled())
		return radix__early_init_mmu();
	return hash__early_init_mmu();
}
extern void hash__early_init_mmu_secondary(void);
extern void radix__early_init_mmu_secondary(void);
static inline void early_init_mmu_secondary(void)
{
	if (radix_enabled())
		return radix__early_init_mmu_secondary();
	return hash__early_init_mmu_secondary();
}

extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
					      phys_addr_t first_memblock_size)
{
	if (early_radix_enabled())
		return radix__setup_initial_memory_limit(first_memblock_base,
						   first_memblock_size);
	return hash__setup_initial_memory_limit(first_memblock_base,
					   first_memblock_size);
}

extern int (*register_process_table)(unsigned long base, unsigned long page_size,
				     unsigned long tbl_size);

#ifdef CONFIG_PPC_PSERIES
extern void radix_init_pseries(void);
#else
static inline void radix_init_pseries(void) { };
#endif

#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
Commit	Line	Data
11a6f6ab AK	1	#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
	2	#define _ASM_POWERPC_BOOK3S_64_MMU_H_
	3
	4	#ifndef __ASSEMBLY__
	5	/*
	6	* Page size definition
	7	*
	8	* shift : is the "PAGE_SHIFT" value for that page size
	9	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	10	* directly to a slbmte "vsid" value
	11	* penc : is the HPTE encoding mask for the "LP" field:
	12	*
	13	*/
	14	struct mmu_psize_def {
	15	unsigned int shift; /* number of bits */
	16	int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
	17	unsigned int tlbiel; /* tlbiel supported for that page size */
	18	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
2bfd65e4 AK	19	union {
	20	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	21	unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
	22	};
11a6f6ab AK	23	};
11a6f6ab AK	24	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
566ca99a	25
11a6f6ab AK	26	#endif /* __ASSEMBLY__ */
11a6f6ab AK	27
11a6f6ab AK	28	/* 64-bit classic hash table MMU */
11a6f6ab AK	29	#include <asm/book3s/64/mmu-hash.h>
11a6f6ab AK	30
11a6f6ab AK	31	#ifndef __ASSEMBLY__
e9983344	32	/*
8ab102d6	33	* ISA 3.0 partition and process table entry format
e9983344 AK	34	*/
	35	struct prtb_entry {
	36	__be64 prtb0;
	37	__be64 prtb1;
	38	};
	39	extern struct prtb_entry *process_tb;
	40
	41	struct patb_entry {
	42	__be64 patb0;
	43	__be64 patb1;
	44	};
	45	extern struct patb_entry *partition_tb;
	46
dbcbfee0	47	/* Bits in patb0 field */
e9983344	48	#define PATB_HR (1UL << 63)
70cd4c10	49	#define RPDB_MASK 0x0fffffffffffff00UL
e9983344	50	#define RPDB_SHIFT (1UL << 8)
dbcbfee0 PM	51	#define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
	52	#define RTS1_MASK (3UL << RTS1_SHIFT)
	53	#define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
	54	#define RTS2_MASK (7UL << RTS2_SHIFT)
	55	#define RPDS_MASK 0x1f /* root page dir. size field */
	56
	57	/* Bits in patb1 field */
	58	#define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
	59	#define PRTS_MASK 0x1f /* process table size field */
70cd4c10	60	#define PRTB_MASK 0x0ffffffffffff000UL
dbcbfee0	61
e9983344 AK	62	/*
	63	* Limit process table to PAGE_SIZE table. This
	64	* also limit the max pid we can support.
	65	* MAX_USER_CONTEXT * 16 bytes of space.
	66	*/
	67	#define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
760573c1 ME	68	#define PRTB_ENTRIES (1ul << CONTEXT_BITS)
760573c1 ME	69
e9983344 AK	70	/*
	71	* Power9 currently only support 64K partition table size.
	72	*/
	73	#define PATB_SIZE_SHIFT 16
11a6f6ab AK	74
	75	typedef unsigned long mm_context_id_t;
	76	struct spinlock;
	77
1ab66d1f AP	78	/* Maximum possible number of NPUs in a system. */
	79	#define NV_MAX_NPUS 8
	80
11a6f6ab AK	81	typedef struct {
	82	mm_context_id_t id;
	83	u16 user_psize; /* page size index */
	84
1ab66d1f AP	85	/* NPU NMMU context */
	86	struct npu_context *npu_context;
	87
11a6f6ab AK	88	#ifdef CONFIG_PPC_MM_SLICES
	89	u64 low_slices_psize; /* SLB page size encodings */
	90	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
957b778a	91	unsigned long addr_limit;
11a6f6ab AK	92	#else
	93	u16 sllp; /* SLB page size encoding */
	94	#endif
	95	unsigned long vdso_base;
	96	#ifdef CONFIG_PPC_SUBPAGE_PROT
	97	struct subpage_prot_table spt;
	98	#endif /* CONFIG_PPC_SUBPAGE_PROT */
	99	#ifdef CONFIG_PPC_ICSWX
	100	struct spinlock cop_lockp; / guard acop and cop_pid */
	101	unsigned long acop; /* mask of enabled coprocessor types */
	102	unsigned int cop_pid; /* pid value used with coprocessors */
	103	#endif /* CONFIG_PPC_ICSWX */
	104	#ifdef CONFIG_PPC_64K_PAGES
	105	/* for 4K PTE fragment support */
	106	void *pte_frag;
	107	#endif
	108	#ifdef CONFIG_SPAPR_TCE_IOMMU
	109	struct list_head iommu_group_mem_list;
	110	#endif
	111	} mm_context_t;
	112
	113	/*
	114	* The current system page and segment sizes
	115	*/
	116	extern int mmu_linear_psize;
	117	extern int mmu_virtual_psize;
	118	extern int mmu_vmalloc_psize;
	119	extern int mmu_vmemmap_psize;
	120	extern int mmu_io_psize;
	121
756d08d1	122	/* MMU initialization */
1a01dc87	123	void mmu_early_init_devtree(void);
bacf9cf8	124	void hash__early_init_devtree(void);
2537b09c	125	void radix__early_init_devtree(void);
2bfd65e4	126	extern void radix_init_native(void);
756d08d1	127	extern void hash__early_init_mmu(void);
2bfd65e4	128	extern void radix__early_init_mmu(void);
756d08d1 AK	129	static inline void early_init_mmu(void)
756d08d1 AK	130	{
2bfd65e4 AK	131	if (radix_enabled())
2bfd65e4 AK	132	return radix__early_init_mmu();
756d08d1 AK	133	return hash__early_init_mmu();
	134	}
	135	extern void hash__early_init_mmu_secondary(void);
2bfd65e4	136	extern void radix__early_init_mmu_secondary(void);
756d08d1 AK	137	static inline void early_init_mmu_secondary(void)
756d08d1 AK	138	{
2bfd65e4 AK	139	if (radix_enabled())
2bfd65e4 AK	140	return radix__early_init_mmu_secondary();
756d08d1 AK	141	return hash__early_init_mmu_secondary();
	142	}
	143
	144	extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	145	phys_addr_t first_memblock_size);
2bfd65e4 AK	146	extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
2bfd65e4 AK	147	phys_addr_t first_memblock_size);
756d08d1 AK	148	static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	149	phys_addr_t first_memblock_size)
	150	{
b8f1b4f8	151	if (early_radix_enabled())
2bfd65e4 AK	152	return radix__setup_initial_memory_limit(first_memblock_base,
2bfd65e4 AK	153	first_memblock_size);
756d08d1 AK	154	return hash__setup_initial_memory_limit(first_memblock_base,
	155	first_memblock_size);
	156	}
eea8148c ME	157
	158	extern int (*register_process_table)(unsigned long base, unsigned long page_size,
	159	unsigned long tbl_size);
	160
cc3d2940 PM	161	#ifdef CONFIG_PPC_PSERIES
	162	extern void radix_init_pseries(void);
	163	#else
	164	static inline void radix_init_pseries(void) { };
	165	#endif
	166
11a6f6ab AK	167	#endif /* __ASSEMBLY__ */
11a6f6ab AK	168	#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */