[mirror_ubuntu-artful-kernel.git] / arch / powerpc / include / asm / book3s / 64 / mmu.h

#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
#define _ASM_POWERPC_BOOK3S_64_MMU_H_

#ifndef __ASSEMBLY__
/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def {
	unsigned int	shift;	/* number of bits */
	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#define radix_enabled() (0)
#endif /* __ASSEMBLY__ */

/* 64-bit classic hash table MMU */
#include <asm/book3s/64/mmu-hash.h>

#ifndef __ASSEMBLY__
/*
 * ISA 3.0 partiton and process table entry format
 */
struct prtb_entry {
	__be64 prtb0;
	__be64 prtb1;
};
extern struct prtb_entry *process_tb;

struct patb_entry {
	__be64 patb0;
	__be64 patb1;
};
extern struct patb_entry *partition_tb;

#define PATB_HR		(1UL << 63)
#define PATB_GR		(1UL << 63)
#define RPDB_MASK	0x0ffffffffffff00fUL
#define RPDB_SHIFT	(1UL << 8)
/*
 * Limit process table to PAGE_SIZE table. This
 * also limit the max pid we can support.
 * MAX_USER_CONTEXT * 16 bytes of space.
 */
#define PRTB_SIZE_SHIFT	(CONTEXT_BITS + 4)
/*
 * Power9 currently only support 64K partition table size.
 */
#define PATB_SIZE_SHIFT	16

typedef unsigned long mm_context_id_t;
struct spinlock;

typedef struct {
	mm_context_id_t id;
	u16 user_psize;		/* page size index */

#ifdef CONFIG_PPC_MM_SLICES
	u64 low_slices_psize;	/* SLB page size encodings */
	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
#else
	u16 sllp;		/* SLB page size encoding */
#endif
	unsigned long vdso_base;
#ifdef CONFIG_PPC_SUBPAGE_PROT
	struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
#ifdef CONFIG_PPC_ICSWX
	struct spinlock *cop_lockp; /* guard acop and cop_pid */
	unsigned long acop;	/* mask of enabled coprocessor types */
	unsigned int cop_pid;	/* pid value used with coprocessors */
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_64K_PAGES
	/* for 4K PTE fragment support */
	void *pte_frag;
#endif
#ifdef CONFIG_SPAPR_TCE_IOMMU
	struct list_head iommu_group_mem_list;
#endif
} mm_context_t;

/*
 * The current system page and segment sizes
 */
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_vmemmap_psize;
extern int mmu_io_psize;

/* MMU initialization */
extern void hash__early_init_mmu(void);
static inline void early_init_mmu(void)
{
	return hash__early_init_mmu();
}
extern void hash__early_init_mmu_secondary(void);
static inline void early_init_mmu_secondary(void)
{
	return hash__early_init_mmu_secondary();
}

extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
					      phys_addr_t first_memblock_size)
{
	return hash__setup_initial_memory_limit(first_memblock_base,
					   first_memblock_size);
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
Commit	Line	Data
11a6f6ab AK	1	#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
	2	#define _ASM_POWERPC_BOOK3S_64_MMU_H_
	3
	4	#ifndef __ASSEMBLY__
	5	/*
	6	* Page size definition
	7	*
	8	* shift : is the "PAGE_SHIFT" value for that page size
	9	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	10	* directly to a slbmte "vsid" value
	11	* penc : is the HPTE encoding mask for the "LP" field:
	12	*
	13	*/
	14	struct mmu_psize_def {
	15	unsigned int shift; /* number of bits */
	16	int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
	17	unsigned int tlbiel; /* tlbiel supported for that page size */
	18	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
	19	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	20	};
	21	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
566ca99a AK	22
566ca99a AK	23	#define radix_enabled() (0)
11a6f6ab AK	24	#endif /* __ASSEMBLY__ */
11a6f6ab AK	25
11a6f6ab AK	26	/* 64-bit classic hash table MMU */
11a6f6ab AK	27	#include <asm/book3s/64/mmu-hash.h>
11a6f6ab AK	28
11a6f6ab AK	29	#ifndef __ASSEMBLY__
e9983344 AK	30	/*
	31	* ISA 3.0 partiton and process table entry format
	32	*/
	33	struct prtb_entry {
	34	__be64 prtb0;
	35	__be64 prtb1;
	36	};
	37	extern struct prtb_entry *process_tb;
	38
	39	struct patb_entry {
	40	__be64 patb0;
	41	__be64 patb1;
	42	};
	43	extern struct patb_entry *partition_tb;
	44
	45	#define PATB_HR (1UL << 63)
	46	#define PATB_GR (1UL << 63)
	47	#define RPDB_MASK 0x0ffffffffffff00fUL
	48	#define RPDB_SHIFT (1UL << 8)
	49	/*
	50	* Limit process table to PAGE_SIZE table. This
	51	* also limit the max pid we can support.
	52	* MAX_USER_CONTEXT * 16 bytes of space.
	53	*/
	54	#define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
	55	/*
	56	* Power9 currently only support 64K partition table size.
	57	*/
	58	#define PATB_SIZE_SHIFT 16
11a6f6ab AK	59
	60	typedef unsigned long mm_context_id_t;
	61	struct spinlock;
	62
	63	typedef struct {
	64	mm_context_id_t id;
	65	u16 user_psize; /* page size index */
	66
	67	#ifdef CONFIG_PPC_MM_SLICES
	68	u64 low_slices_psize; /* SLB page size encodings */
	69	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
	70	#else
	71	u16 sllp; /* SLB page size encoding */
	72	#endif
	73	unsigned long vdso_base;
	74	#ifdef CONFIG_PPC_SUBPAGE_PROT
	75	struct subpage_prot_table spt;
	76	#endif /* CONFIG_PPC_SUBPAGE_PROT */
	77	#ifdef CONFIG_PPC_ICSWX
	78	struct spinlock cop_lockp; / guard acop and cop_pid */
	79	unsigned long acop; /* mask of enabled coprocessor types */
	80	unsigned int cop_pid; /* pid value used with coprocessors */
	81	#endif /* CONFIG_PPC_ICSWX */
	82	#ifdef CONFIG_PPC_64K_PAGES
	83	/* for 4K PTE fragment support */
	84	void *pte_frag;
	85	#endif
	86	#ifdef CONFIG_SPAPR_TCE_IOMMU
	87	struct list_head iommu_group_mem_list;
	88	#endif
	89	} mm_context_t;
	90
	91	/*
	92	* The current system page and segment sizes
	93	*/
	94	extern int mmu_linear_psize;
	95	extern int mmu_virtual_psize;
	96	extern int mmu_vmalloc_psize;
	97	extern int mmu_vmemmap_psize;
	98	extern int mmu_io_psize;
	99
756d08d1 AK	100	/* MMU initialization */
	101	extern void hash__early_init_mmu(void);
	102	static inline void early_init_mmu(void)
	103	{
	104	return hash__early_init_mmu();
	105	}
	106	extern void hash__early_init_mmu_secondary(void);
	107	static inline void early_init_mmu_secondary(void)
	108	{
	109	return hash__early_init_mmu_secondary();
	110	}
	111
	112	extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	113	phys_addr_t first_memblock_size);
	114	static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	115	phys_addr_t first_memblock_size)
	116	{
	117	return hash__setup_initial_memory_limit(first_memblock_base,
	118	first_memblock_size);
	119	}
11a6f6ab AK	120	#endif /* __ASSEMBLY__ */
11a6f6ab AK	121	#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */