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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
9849a569 KS |
5 | #include <asm-generic/5level-fixup.h> |
6 | ||
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
c137a275 | 10 | #endif |
9849a569 | 11 | |
2e873519 AK |
12 | /* |
13 | * Common bits between hash and Radix page table | |
14 | */ | |
15 | #define _PAGE_BIT_SWAP_TYPE 0 | |
16 | ||
6b8cb66a | 17 | #define _PAGE_RO 0 |
fd893fe5 | 18 | #define _PAGE_SHARED 0 |
6b8cb66a | 19 | |
2e873519 AK |
20 | #define _PAGE_EXEC 0x00001 /* execute permission */ |
21 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
22 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
23 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) | |
24 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
25 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
26 | #define _PAGE_SAO 0x00010 /* Strong access order */ | |
27 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ | |
28 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
29 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
30 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 31 | /* |
2e873519 | 32 | * Software bits |
3dfcb315 | 33 | */ |
69dfbaeb AK |
34 | #define _RPAGE_SW0 0x2000000000000000UL |
35 | #define _RPAGE_SW1 0x00800 | |
36 | #define _RPAGE_SW2 0x00400 | |
37 | #define _RPAGE_SW3 0x00200 | |
049d567a AK |
38 | #define _RPAGE_RSV1 0x1000000000000000UL |
39 | #define _RPAGE_RSV2 0x0800000000000000UL | |
40 | #define _RPAGE_RSV3 0x0400000000000000UL | |
41 | #define _RPAGE_RSV4 0x0200000000000000UL | |
6aa59f51 AK |
42 | |
43 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
44 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
49c6e7a9 AK |
45 | /* |
46 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
47 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
48 | * differentiate between two use a SW field when invalidating. | |
49 | * | |
50 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
51 | * | |
52 | * This is used only when _PAGE_PRESENT is cleared. | |
53 | */ | |
54 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
55 | |
56 | /* | |
57 | * Top and bottom bits of RPN which can be used by hash | |
58 | * translation mode, because we expect them to be zero | |
59 | * otherwise. | |
60 | */ | |
32789d38 AK |
61 | #define _RPAGE_RPN0 0x01000 |
62 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
63 | #define _RPAGE_RPN44 0x0100000000000000UL |
64 | #define _RPAGE_RPN43 0x0080000000000000UL | |
65 | #define _RPAGE_RPN42 0x0040000000000000UL | |
66 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 67 | |
2f18d533 AK |
68 | /* Max physical address bit as per radix table */ |
69 | #define _RPAGE_PA_MAX 57 | |
70 | ||
71 | /* | |
72 | * Max physical address bit we will use for now. | |
73 | * | |
74 | * This is mostly a hardware limitation and for now Power9 has | |
75 | * a 51 bit limit. | |
76 | * | |
77 | * This is different from the number of physical bit required to address | |
78 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
79 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
80 | * number of sections we can support (SECTIONS_SHIFT). | |
81 | * | |
82 | * This is different from Radix page table limitation above and | |
83 | * should always be less than that. The limit is done such that | |
84 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
85 | * for hash linux page table specific bits. | |
86 | * | |
87 | * In order to be compatible with future hardware generations we keep | |
88 | * some offsets and limit this for now to 53 | |
89 | */ | |
90 | #define _PAGE_PA_MAX 53 | |
91 | ||
69dfbaeb | 92 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 93 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 OH |
94 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
95 | #define __HAVE_ARCH_PTE_DEVMAP | |
96 | ||
2e873519 AK |
97 | /* |
98 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
99 | * Instead of fixing all of them, add an alternate define which | |
100 | * maps CI pte mapping. | |
101 | */ | |
102 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
103 | /* | |
2f18d533 AK |
104 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
105 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
106 | * and every thing below PAGE_SHIFT; | |
2e873519 | 107 | */ |
2f18d533 | 108 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
2e873519 AK |
109 | /* |
110 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
111 | * in here, on radix we expect them to be zero. | |
112 | */ | |
113 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
114 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
97a60d01 | 115 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
116 | /* |
117 | * user access blocked by key | |
118 | */ | |
119 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
120 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
121 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ | |
122 | _PAGE_RW | _PAGE_EXEC) | |
123 | /* | |
124 | * No page size encoding in the linux PTE | |
125 | */ | |
126 | #define _PAGE_PSIZE 0 | |
127 | /* | |
128 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
129 | * pgprot changes | |
130 | */ | |
131 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
132 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
97a60d01 | 133 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
134 | /* |
135 | * Mask of bits returned by pte_pgprot() | |
136 | */ | |
137 | #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ | |
138 | H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ | |
139 | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ | |
140 | _PAGE_SOFT_DIRTY) | |
3dfcb315 | 141 | /* |
2e873519 AK |
142 | * We define 2 sets of base prot bits, one for basic pages (ie, |
143 | * cacheable kernel and user pages) and one for non cacheable | |
144 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
145 | * the processor might need it for DMA coherency. | |
3dfcb315 | 146 | */ |
2e873519 AK |
147 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) |
148 | #define _PAGE_BASE (_PAGE_BASE_NC) | |
149 | ||
150 | /* Permission masks used to generate the __P and __S table, | |
151 | * | |
152 | * Note:__pgprot is defined in arch/powerpc/include/asm/page.h | |
153 | * | |
154 | * Write permissions imply read permissions for now (we could make write-only | |
155 | * pages on BookE but we don't bother for now). Execute permission control is | |
156 | * possible on platforms that define _PAGE_EXEC | |
157 | * | |
158 | * Note due to the way vm flags are laid out, the bits are XWR | |
159 | */ | |
160 | #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) | |
161 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) | |
162 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) | |
163 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) | |
164 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
165 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) | |
166 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
167 | ||
168 | #define __P000 PAGE_NONE | |
169 | #define __P001 PAGE_READONLY | |
170 | #define __P010 PAGE_COPY | |
171 | #define __P011 PAGE_COPY | |
172 | #define __P100 PAGE_READONLY_X | |
173 | #define __P101 PAGE_READONLY_X | |
174 | #define __P110 PAGE_COPY_X | |
175 | #define __P111 PAGE_COPY_X | |
176 | ||
177 | #define __S000 PAGE_NONE | |
178 | #define __S001 PAGE_READONLY | |
179 | #define __S010 PAGE_SHARED | |
180 | #define __S011 PAGE_SHARED | |
181 | #define __S100 PAGE_READONLY_X | |
182 | #define __S101 PAGE_READONLY_X | |
183 | #define __S110 PAGE_SHARED_X | |
184 | #define __S111 PAGE_SHARED_X | |
185 | ||
186 | /* Permission masks used for kernel mappings */ | |
187 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
188 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
189 | _PAGE_TOLERANT) | |
190 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
191 | _PAGE_NON_IDEMPOTENT) | |
192 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) | |
193 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
194 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
195 | ||
196 | /* | |
197 | * Protection used for kernel text. We want the debuggers to be able to | |
198 | * set breakpoints anywhere, so don't write protect the kernel text | |
199 | * on platforms where such control is possible. | |
200 | */ | |
201 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ | |
202 | defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) | |
203 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_X | |
204 | #else | |
205 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX | |
206 | #endif | |
207 | ||
208 | /* Make modules code happy. We don't set RO yet */ | |
209 | #define PAGE_KERNEL_EXEC PAGE_KERNEL_X | |
210 | #define PAGE_AGP (PAGE_KERNEL_NC) | |
3dfcb315 | 211 | |
dd1842a2 AK |
212 | #ifndef __ASSEMBLY__ |
213 | /* | |
214 | * page table defines | |
215 | */ | |
216 | extern unsigned long __pte_index_size; | |
217 | extern unsigned long __pmd_index_size; | |
218 | extern unsigned long __pud_index_size; | |
219 | extern unsigned long __pgd_index_size; | |
220 | extern unsigned long __pmd_cache_index; | |
221 | #define PTE_INDEX_SIZE __pte_index_size | |
222 | #define PMD_INDEX_SIZE __pmd_index_size | |
223 | #define PUD_INDEX_SIZE __pud_index_size | |
224 | #define PGD_INDEX_SIZE __pgd_index_size | |
225 | #define PMD_CACHE_INDEX __pmd_cache_index | |
226 | /* | |
227 | * Because of use of pte fragments and THP, size of page table | |
228 | * are not always derived out of index size above. | |
229 | */ | |
230 | extern unsigned long __pte_table_size; | |
231 | extern unsigned long __pmd_table_size; | |
232 | extern unsigned long __pud_table_size; | |
233 | extern unsigned long __pgd_table_size; | |
234 | #define PTE_TABLE_SIZE __pte_table_size | |
235 | #define PMD_TABLE_SIZE __pmd_table_size | |
236 | #define PUD_TABLE_SIZE __pud_table_size | |
237 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
238 | |
239 | extern unsigned long __pmd_val_bits; | |
240 | extern unsigned long __pud_val_bits; | |
241 | extern unsigned long __pgd_val_bits; | |
242 | #define PMD_VAL_BITS __pmd_val_bits | |
243 | #define PUD_VAL_BITS __pud_val_bits | |
244 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
245 | |
246 | extern unsigned long __pte_frag_nr; | |
247 | #define PTE_FRAG_NR __pte_frag_nr | |
248 | extern unsigned long __pte_frag_size_shift; | |
249 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
250 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 AK |
251 | |
252 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
253 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
254 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
255 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
256 | ||
257 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
258 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
259 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
260 | #define PMD_MASK (~(PMD_SIZE-1)) | |
261 | ||
262 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
263 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
264 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
265 | #define PUD_MASK (~(PUD_SIZE-1)) | |
266 | ||
267 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
268 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
269 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
270 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
271 | ||
272 | /* Bits to mask out from a PMD to get to the PTE page */ | |
273 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
274 | /* Bits to mask out from a PUD to get to the PMD page */ | |
275 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
276 | /* Bits to mask out from a PGD to get to the PUD page */ | |
277 | #define PGD_MASKED_BITS 0xc0000000000000ffUL | |
d6a9996e AK |
278 | |
279 | extern unsigned long __vmalloc_start; | |
280 | extern unsigned long __vmalloc_end; | |
281 | #define VMALLOC_START __vmalloc_start | |
282 | #define VMALLOC_END __vmalloc_end | |
283 | ||
284 | extern unsigned long __kernel_virt_start; | |
285 | extern unsigned long __kernel_virt_size; | |
63ee9b2f | 286 | extern unsigned long __kernel_io_start; |
d6a9996e AK |
287 | #define KERN_VIRT_START __kernel_virt_start |
288 | #define KERN_VIRT_SIZE __kernel_virt_size | |
63ee9b2f | 289 | #define KERN_IO_START __kernel_io_start |
d6a9996e AK |
290 | extern struct page *vmemmap; |
291 | extern unsigned long ioremap_bot; | |
bfa37087 | 292 | extern unsigned long pci_io_base; |
dd1842a2 | 293 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 294 | |
ab537dca | 295 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 296 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 297 | |
a9252aae AK |
298 | #ifdef CONFIG_PPC_64K_PAGES |
299 | #include <asm/book3s/64/pgtable-64k.h> | |
300 | #else | |
301 | #include <asm/book3s/64/pgtable-4k.h> | |
302 | #endif | |
303 | ||
3dfcb315 | 304 | #include <asm/barrier.h> |
3dfcb315 AK |
305 | /* |
306 | * The second half of the kernel virtual space is used for IO mappings, | |
307 | * it's itself carved into the PIO region (ISA and PHB IO space) and | |
308 | * the ioremap space | |
309 | * | |
310 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
311 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
312 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
313 | */ | |
3dfcb315 AK |
314 | #define FULL_IO_SIZE 0x80000000ul |
315 | #define ISA_IO_BASE (KERN_IO_START) | |
316 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
317 | #define PHB_IO_BASE (ISA_IO_END) | |
318 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
319 | #define IOREMAP_BASE (PHB_IO_END) | |
320 | #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) | |
321 | ||
b0412ea9 | 322 | /* Advertise special mapping type for AGP */ |
b0412ea9 AK |
323 | #define HAVE_PAGE_AGP |
324 | ||
325 | /* Advertise support for _PAGE_SPECIAL */ | |
326 | #define __HAVE_ARCH_PTE_SPECIAL | |
327 | ||
3dfcb315 AK |
328 | #ifndef __ASSEMBLY__ |
329 | ||
330 | /* | |
331 | * This is the default implementation of various PTE accessors, it's | |
332 | * used in all cases except Book3S with 64K pages where we have a | |
333 | * concept of sub-pages | |
334 | */ | |
335 | #ifndef __real_pte | |
336 | ||
3dfcb315 AK |
337 | #define __real_pte(e,p) ((real_pte_t){(e)}) |
338 | #define __rpte_to_pte(r) ((r).pte) | |
945537df | 339 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
340 | |
341 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
342 | do { \ | |
343 | index = 0; \ | |
344 | shift = mmu_psize_defs[psize].shift; \ | |
345 | ||
346 | #define pte_iterate_hashed_end() } while(0) | |
347 | ||
348 | /* | |
349 | * We expect this to be called only for user addresses or kernel virtual | |
350 | * addresses other than the linear mapping. | |
351 | */ | |
352 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
353 | ||
354 | #endif /* __real_pte */ | |
355 | ||
ac94ac79 AK |
356 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
357 | pte_t *ptep, unsigned long clr, | |
358 | unsigned long set, int huge) | |
359 | { | |
360 | if (radix_enabled()) | |
361 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
362 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
363 | } | |
13f829a5 AK |
364 | /* |
365 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
366 | * We currently remove entries from the hashtable regardless of whether | |
367 | * the entry was young or dirty. | |
368 | * | |
369 | * We should be more intelligent about this but for the moment we override | |
370 | * these functions and force a tlb flush unconditionally | |
371 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
372 | * function for both hash and radix. | |
373 | */ | |
374 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
375 | unsigned long addr, pte_t *ptep) | |
376 | { | |
377 | unsigned long old; | |
378 | ||
66c570f5 | 379 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
380 | return 0; |
381 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
382 | return (old & _PAGE_ACCESSED) != 0; | |
383 | } | |
384 | ||
385 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
386 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
387 | ({ \ | |
388 | int __r; \ | |
389 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
390 | __r; \ | |
391 | }) | |
392 | ||
d19469e8 | 393 | static inline int __pte_write(pte_t pte) |
52c50ca7 AK |
394 | { |
395 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); | |
396 | } | |
397 | ||
398 | #ifdef CONFIG_NUMA_BALANCING | |
399 | #define pte_savedwrite pte_savedwrite | |
400 | static inline bool pte_savedwrite(pte_t pte) | |
401 | { | |
402 | /* | |
403 | * Saved write ptes are prot none ptes that doesn't have | |
404 | * privileged bit sit. We mark prot none as one which has | |
405 | * present and pviliged bit set and RWX cleared. To mark | |
406 | * protnone which used to have _PAGE_WRITE set we clear | |
407 | * the privileged bit. | |
408 | */ | |
409 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); | |
410 | } | |
411 | #else | |
412 | #define pte_savedwrite pte_savedwrite | |
413 | static inline bool pte_savedwrite(pte_t pte) | |
414 | { | |
415 | return false; | |
416 | } | |
417 | #endif | |
418 | ||
d19469e8 AK |
419 | static inline int pte_write(pte_t pte) |
420 | { | |
421 | return __pte_write(pte) || pte_savedwrite(pte); | |
422 | } | |
423 | ||
ca8afd40 CL |
424 | static inline int pte_read(pte_t pte) |
425 | { | |
426 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
427 | } | |
428 | ||
13f829a5 AK |
429 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
430 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
431 | pte_t *ptep) | |
432 | { | |
d19469e8 | 433 | if (__pte_write(*ptep)) |
52c50ca7 AK |
434 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
435 | else if (unlikely(pte_savedwrite(*ptep))) | |
436 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); | |
13f829a5 AK |
437 | } |
438 | ||
439 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, | |
440 | unsigned long addr, pte_t *ptep) | |
441 | { | |
52c50ca7 AK |
442 | /* |
443 | * We should not find protnone for hugetlb, but this complete the | |
444 | * interface. | |
445 | */ | |
d19469e8 | 446 | if (__pte_write(*ptep)) |
52c50ca7 AK |
447 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
448 | else if (unlikely(pte_savedwrite(*ptep))) | |
449 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); | |
13f829a5 AK |
450 | } |
451 | ||
452 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
453 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
454 | unsigned long addr, pte_t *ptep) | |
455 | { | |
456 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
457 | return __pte(old); | |
458 | } | |
459 | ||
f4894b80 AK |
460 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
461 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
462 | unsigned long addr, | |
463 | pte_t *ptep, int full) | |
464 | { | |
465 | if (full && radix_enabled()) { | |
466 | /* | |
467 | * Let's skip the DD1 style pte update here. We know that | |
468 | * this is a full mm pte clear and hence can be sure there is | |
469 | * no parallel set_pte. | |
470 | */ | |
471 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
472 | } | |
473 | return ptep_get_and_clear(mm, addr, ptep); | |
474 | } | |
475 | ||
476 | ||
13f829a5 AK |
477 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
478 | pte_t * ptep) | |
479 | { | |
480 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
481 | } | |
66c570f5 | 482 | |
66c570f5 AK |
483 | static inline int pte_dirty(pte_t pte) |
484 | { | |
485 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
486 | } | |
487 | ||
488 | static inline int pte_young(pte_t pte) | |
489 | { | |
490 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
491 | } | |
492 | ||
493 | static inline int pte_special(pte_t pte) | |
494 | { | |
495 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
496 | } | |
497 | ||
13f829a5 AK |
498 | static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } |
499 | ||
500 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
501 | static inline bool pte_soft_dirty(pte_t pte) | |
502 | { | |
66c570f5 | 503 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 504 | } |
66c570f5 | 505 | |
13f829a5 AK |
506 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
507 | { | |
508 | return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); | |
509 | } | |
510 | ||
511 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
512 | { | |
513 | return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); | |
514 | } | |
515 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
516 | ||
517 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
518 | static inline int pte_protnone(pte_t pte) |
519 | { | |
c137a275 AK |
520 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
521 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
522 | } | |
523 | ||
524 | #define pte_mk_savedwrite pte_mk_savedwrite | |
525 | static inline pte_t pte_mk_savedwrite(pte_t pte) | |
526 | { | |
527 | /* | |
528 | * Used by Autonuma subsystem to preserve the write bit | |
529 | * while marking the pte PROT_NONE. Only allow this | |
530 | * on PROT_NONE pte | |
531 | */ | |
532 | VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != | |
533 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); | |
534 | return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED); | |
535 | } | |
536 | ||
537 | #define pte_clear_savedwrite pte_clear_savedwrite | |
538 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
539 | { | |
540 | /* | |
541 | * Used by KSM subsystem to make a protnone pte readonly. | |
542 | */ | |
543 | VM_BUG_ON(!pte_protnone(pte)); | |
544 | return __pte(pte_val(pte) | _PAGE_PRIVILEGED); | |
545 | } | |
d19469e8 AK |
546 | #else |
547 | #define pte_clear_savedwrite pte_clear_savedwrite | |
548 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
549 | { | |
550 | VM_WARN_ON(1); | |
551 | return __pte(pte_val(pte) & ~_PAGE_WRITE); | |
552 | } | |
13f829a5 AK |
553 | #endif /* CONFIG_NUMA_BALANCING */ |
554 | ||
555 | static inline int pte_present(pte_t pte) | |
556 | { | |
49c6e7a9 AK |
557 | /* |
558 | * A pte is considerent present if _PAGE_PRESENT is set. | |
559 | * We also need to consider the pte present which is marked | |
560 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
561 | * if we find _PAGE_PRESENT cleared. | |
562 | */ | |
563 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); | |
13f829a5 AK |
564 | } |
565 | /* | |
566 | * Conversion functions: convert a page and protection to a page entry, | |
567 | * and a page entry and page directory to the page they refer to. | |
568 | * | |
569 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
570 | * long for now. | |
571 | */ | |
572 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
573 | { | |
574 | return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | | |
575 | pgprot_val(pgprot)); | |
576 | } | |
577 | ||
578 | static inline unsigned long pte_pfn(pte_t pte) | |
579 | { | |
580 | return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; | |
581 | } | |
582 | ||
583 | /* Generic modifiers for PTE bits */ | |
584 | static inline pte_t pte_wrprotect(pte_t pte) | |
585 | { | |
d19469e8 AK |
586 | if (unlikely(pte_savedwrite(pte))) |
587 | return pte_clear_savedwrite(pte); | |
13f829a5 AK |
588 | return __pte(pte_val(pte) & ~_PAGE_WRITE); |
589 | } | |
590 | ||
591 | static inline pte_t pte_mkclean(pte_t pte) | |
592 | { | |
593 | return __pte(pte_val(pte) & ~_PAGE_DIRTY); | |
594 | } | |
595 | ||
596 | static inline pte_t pte_mkold(pte_t pte) | |
597 | { | |
598 | return __pte(pte_val(pte) & ~_PAGE_ACCESSED); | |
599 | } | |
600 | ||
601 | static inline pte_t pte_mkwrite(pte_t pte) | |
602 | { | |
603 | /* | |
604 | * write implies read, hence set both | |
605 | */ | |
606 | return __pte(pte_val(pte) | _PAGE_RW); | |
607 | } | |
608 | ||
609 | static inline pte_t pte_mkdirty(pte_t pte) | |
610 | { | |
611 | return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); | |
612 | } | |
613 | ||
614 | static inline pte_t pte_mkyoung(pte_t pte) | |
615 | { | |
616 | return __pte(pte_val(pte) | _PAGE_ACCESSED); | |
617 | } | |
618 | ||
619 | static inline pte_t pte_mkspecial(pte_t pte) | |
620 | { | |
621 | return __pte(pte_val(pte) | _PAGE_SPECIAL); | |
622 | } | |
623 | ||
624 | static inline pte_t pte_mkhuge(pte_t pte) | |
625 | { | |
626 | return pte; | |
627 | } | |
628 | ||
ebd31197 OH |
629 | static inline pte_t pte_mkdevmap(pte_t pte) |
630 | { | |
631 | return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP); | |
632 | } | |
633 | ||
c9c98bc5 OH |
634 | /* |
635 | * This is potentially called with a pmd as the argument, in which case it's not | |
636 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
637 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
638 | * use in page directory entries (ie. non-ptes). | |
639 | */ | |
ebd31197 OH |
640 | static inline int pte_devmap(pte_t pte) |
641 | { | |
c9c98bc5 OH |
642 | u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
643 | ||
644 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
645 | } |
646 | ||
13f829a5 AK |
647 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
648 | { | |
649 | /* FIXME!! check whether this need to be a conditional */ | |
650 | return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); | |
651 | } | |
652 | ||
34fbadd8 AK |
653 | static inline bool pte_user(pte_t pte) |
654 | { | |
66c570f5 | 655 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); |
34fbadd8 AK |
656 | } |
657 | ||
658 | /* Encode and de-code a swap entry */ | |
659 | #define MAX_SWAPFILES_CHECK() do { \ | |
660 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
661 | /* \ | |
662 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
663 | * We filter HPTEFLAGS on set_pte. \ | |
664 | */ \ | |
665 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ | |
666 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ | |
667 | } while (0) | |
668 | /* | |
669 | * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; | |
670 | */ | |
671 | #define SWP_TYPE_BITS 5 | |
672 | #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ | |
673 | & ((1UL << SWP_TYPE_BITS) - 1)) | |
674 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) | |
675 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
676 | ((type) << _PAGE_BIT_SWAP_TYPE) \ | |
677 | | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) | |
678 | /* | |
679 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
680 | * swap type and offset we get from swap and convert that to pte to find a | |
681 | * matching pte in linux page table. | |
682 | * Clear bits not found in swap entries here. | |
683 | */ | |
684 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
685 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
686 | ||
687 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
688 | #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) | |
689 | #else | |
690 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
691 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
692 | ||
693 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
694 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
695 | { | |
696 | return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); | |
697 | } | |
66c570f5 | 698 | |
34fbadd8 AK |
699 | static inline bool pte_swp_soft_dirty(pte_t pte) |
700 | { | |
66c570f5 | 701 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 702 | } |
66c570f5 | 703 | |
34fbadd8 AK |
704 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
705 | { | |
706 | return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); | |
707 | } | |
708 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
709 | ||
710 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) | |
711 | { | |
712 | /* | |
713 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
714 | */ | |
715 | if (access & ~ptev) | |
716 | return false; | |
717 | /* | |
718 | * This check for access to privilege space | |
719 | */ | |
720 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
721 | return false; | |
722 | ||
723 | return true; | |
724 | } | |
ac94ac79 AK |
725 | /* |
726 | * Generic functions with hash/radix callbacks | |
727 | */ | |
728 | ||
a06b5515 | 729 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 730 | pte_t *ptep, pte_t entry, |
a06b5515 AK |
731 | unsigned long address, |
732 | int psize) | |
ac94ac79 AK |
733 | { |
734 | if (radix_enabled()) | |
a06b5515 AK |
735 | return radix__ptep_set_access_flags(vma, ptep, entry, |
736 | address, psize); | |
ac94ac79 AK |
737 | return hash__ptep_set_access_flags(ptep, entry); |
738 | } | |
739 | ||
740 | #define __HAVE_ARCH_PTE_SAME | |
741 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
742 | { | |
743 | if (radix_enabled()) | |
744 | return radix__pte_same(pte_a, pte_b); | |
745 | return hash__pte_same(pte_a, pte_b); | |
746 | } | |
747 | ||
748 | static inline int pte_none(pte_t pte) | |
749 | { | |
750 | if (radix_enabled()) | |
751 | return radix__pte_none(pte); | |
752 | return hash__pte_none(pte); | |
753 | } | |
754 | ||
755 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
756 | pte_t *ptep, pte_t pte, int percpu) | |
757 | { | |
758 | if (radix_enabled()) | |
759 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
760 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
761 | } | |
34fbadd8 | 762 | |
13f829a5 AK |
763 | #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
764 | ||
765 | #define pgprot_noncached pgprot_noncached | |
766 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
767 | { | |
768 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
769 | _PAGE_NON_IDEMPOTENT); | |
770 | } | |
771 | ||
772 | #define pgprot_noncached_wc pgprot_noncached_wc | |
773 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
774 | { | |
775 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
776 | _PAGE_TOLERANT); | |
777 | } | |
778 | ||
779 | #define pgprot_cached pgprot_cached | |
780 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
781 | { | |
782 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
783 | } | |
784 | ||
785 | #define pgprot_writecombine pgprot_writecombine | |
786 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
787 | { | |
788 | return pgprot_noncached_wc(prot); | |
789 | } | |
790 | /* | |
791 | * check a pte mapping have cache inhibited property | |
792 | */ | |
793 | static inline bool pte_ci(pte_t pte) | |
794 | { | |
795 | unsigned long pte_v = pte_val(pte); | |
796 | ||
797 | if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || | |
798 | ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) | |
799 | return true; | |
800 | return false; | |
801 | } | |
802 | ||
f281b5d5 AK |
803 | static inline void pmd_set(pmd_t *pmdp, unsigned long val) |
804 | { | |
805 | *pmdp = __pmd(val); | |
806 | } | |
807 | ||
808 | static inline void pmd_clear(pmd_t *pmdp) | |
809 | { | |
810 | *pmdp = __pmd(0); | |
811 | } | |
812 | ||
66c570f5 AK |
813 | static inline int pmd_none(pmd_t pmd) |
814 | { | |
815 | return !pmd_raw(pmd); | |
816 | } | |
817 | ||
818 | static inline int pmd_present(pmd_t pmd) | |
819 | { | |
820 | ||
821 | return !pmd_none(pmd); | |
822 | } | |
3dfcb315 | 823 | |
ac94ac79 AK |
824 | static inline int pmd_bad(pmd_t pmd) |
825 | { | |
826 | if (radix_enabled()) | |
827 | return radix__pmd_bad(pmd); | |
828 | return hash__pmd_bad(pmd); | |
829 | } | |
830 | ||
f281b5d5 AK |
831 | static inline void pud_set(pud_t *pudp, unsigned long val) |
832 | { | |
833 | *pudp = __pud(val); | |
834 | } | |
835 | ||
836 | static inline void pud_clear(pud_t *pudp) | |
837 | { | |
838 | *pudp = __pud(0); | |
839 | } | |
840 | ||
66c570f5 AK |
841 | static inline int pud_none(pud_t pud) |
842 | { | |
843 | return !pud_raw(pud); | |
844 | } | |
845 | ||
846 | static inline int pud_present(pud_t pud) | |
847 | { | |
848 | return !pud_none(pud); | |
849 | } | |
3dfcb315 AK |
850 | |
851 | extern struct page *pud_page(pud_t pud); | |
371352ca | 852 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
853 | static inline pte_t pud_pte(pud_t pud) |
854 | { | |
66c570f5 | 855 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
856 | } |
857 | ||
858 | static inline pud_t pte_pud(pte_t pte) | |
859 | { | |
66c570f5 | 860 | return __pud_raw(pte_raw(pte)); |
3dfcb315 AK |
861 | } |
862 | #define pud_write(pud) pte_write(pud_pte(pud)) | |
ac94ac79 AK |
863 | |
864 | static inline int pud_bad(pud_t pud) | |
865 | { | |
866 | if (radix_enabled()) | |
867 | return radix__pud_bad(pud); | |
868 | return hash__pud_bad(pud); | |
869 | } | |
870 | ||
871 | ||
3dfcb315 | 872 | #define pgd_write(pgd) pte_write(pgd_pte(pgd)) |
f281b5d5 AK |
873 | static inline void pgd_set(pgd_t *pgdp, unsigned long val) |
874 | { | |
875 | *pgdp = __pgd(val); | |
876 | } | |
3dfcb315 | 877 | |
368ced78 AK |
878 | static inline void pgd_clear(pgd_t *pgdp) |
879 | { | |
880 | *pgdp = __pgd(0); | |
881 | } | |
882 | ||
66c570f5 AK |
883 | static inline int pgd_none(pgd_t pgd) |
884 | { | |
885 | return !pgd_raw(pgd); | |
886 | } | |
887 | ||
888 | static inline int pgd_present(pgd_t pgd) | |
889 | { | |
890 | return !pgd_none(pgd); | |
891 | } | |
368ced78 AK |
892 | |
893 | static inline pte_t pgd_pte(pgd_t pgd) | |
894 | { | |
66c570f5 | 895 | return __pte_raw(pgd_raw(pgd)); |
368ced78 AK |
896 | } |
897 | ||
898 | static inline pgd_t pte_pgd(pte_t pte) | |
899 | { | |
66c570f5 | 900 | return __pgd_raw(pte_raw(pte)); |
368ced78 AK |
901 | } |
902 | ||
ac94ac79 AK |
903 | static inline int pgd_bad(pgd_t pgd) |
904 | { | |
905 | if (radix_enabled()) | |
906 | return radix__pgd_bad(pgd); | |
907 | return hash__pgd_bad(pgd); | |
908 | } | |
909 | ||
368ced78 AK |
910 | extern struct page *pgd_page(pgd_t pgd); |
911 | ||
aba480e1 AK |
912 | /* Pointers in the page table tree are physical addresses */ |
913 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
914 | ||
915 | #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) | |
916 | #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) | |
917 | #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) | |
918 | ||
919 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) | |
920 | #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) | |
921 | #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) | |
922 | #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) | |
923 | ||
3dfcb315 AK |
924 | /* |
925 | * Find an entry in a page-table-directory. We combine the address region | |
926 | * (the high order N bits) and the pgd portion of the address. | |
927 | */ | |
3dfcb315 AK |
928 | |
929 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
930 | ||
368ced78 AK |
931 | #define pud_offset(pgdp, addr) \ |
932 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) | |
3dfcb315 | 933 | #define pmd_offset(pudp,addr) \ |
371352ca | 934 | (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) |
3dfcb315 | 935 | #define pte_offset_kernel(dir,addr) \ |
371352ca | 936 | (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) |
3dfcb315 AK |
937 | |
938 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
939 | #define pte_unmap(pte) do { } while(0) | |
940 | ||
941 | /* to find an entry in a kernel page-table-directory */ | |
942 | /* This now only contains the vmalloc pages */ | |
943 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
3dfcb315 AK |
944 | |
945 | #define pte_ERROR(e) \ | |
946 | pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
947 | #define pmd_ERROR(e) \ | |
948 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
949 | #define pud_ERROR(e) \ |
950 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
951 | #define pgd_ERROR(e) \ |
952 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
953 | ||
31a14fae AK |
954 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, |
955 | unsigned long flags) | |
7207f436 | 956 | { |
d9225ad9 AK |
957 | if (radix_enabled()) { |
958 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
959 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
960 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
961 | #endif | |
962 | return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); | |
963 | } | |
31a14fae | 964 | return hash__map_kernel_page(ea, pa, flags); |
7207f436 | 965 | } |
31a14fae AK |
966 | |
967 | static inline int __meminit vmemmap_create_mapping(unsigned long start, | |
968 | unsigned long page_size, | |
969 | unsigned long phys) | |
7207f436 | 970 | { |
d9225ad9 AK |
971 | if (radix_enabled()) |
972 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 973 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 974 | } |
31a14fae AK |
975 | |
976 | #ifdef CONFIG_MEMORY_HOTPLUG | |
977 | static inline void vmemmap_remove_mapping(unsigned long start, | |
978 | unsigned long page_size) | |
7207f436 | 979 | { |
d9225ad9 AK |
980 | if (radix_enabled()) |
981 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 982 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 983 | } |
31a14fae | 984 | #endif |
3dfcb315 AK |
985 | struct page *realmode_pfn_to_page(unsigned long pfn); |
986 | ||
3dfcb315 AK |
987 | static inline pte_t pmd_pte(pmd_t pmd) |
988 | { | |
66c570f5 | 989 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
990 | } |
991 | ||
992 | static inline pmd_t pte_pmd(pte_t pte) | |
993 | { | |
66c570f5 | 994 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
995 | } |
996 | ||
997 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
998 | { | |
999 | return (pte_t *)pmd; | |
1000 | } | |
3dfcb315 AK |
1001 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1002 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1003 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1004 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1005 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1006 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1007 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 AK |
1008 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
1009 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
c137a275 AK |
1010 | #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) |
1011 | #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) | |
7207f436 LD |
1012 | |
1013 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1014 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1015 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1016 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
1017 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
1018 | ||
1ca72129 AK |
1019 | #ifdef CONFIG_NUMA_BALANCING |
1020 | static inline int pmd_protnone(pmd_t pmd) | |
1021 | { | |
1022 | return pte_protnone(pmd_pte(pmd)); | |
1023 | } | |
1024 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1025 | |
3dfcb315 | 1026 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
d19469e8 | 1027 | #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) |
c137a275 | 1028 | #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) |
3dfcb315 | 1029 | |
6a1ea362 AK |
1030 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1031 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
1032 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); | |
1033 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1034 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1035 | pmd_t *pmdp, pmd_t pmd); | |
1036 | extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, | |
1037 | pmd_t *pmd); | |
3df33f12 AK |
1038 | extern int hash__has_transparent_hugepage(void); |
1039 | static inline int has_transparent_hugepage(void) | |
1040 | { | |
bde3eb62 AK |
1041 | if (radix_enabled()) |
1042 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1043 | return hash__has_transparent_hugepage(); |
1044 | } | |
c04a5880 | 1045 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1046 | |
3df33f12 AK |
1047 | static inline unsigned long |
1048 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1049 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1050 | { |
bde3eb62 AK |
1051 | if (radix_enabled()) |
1052 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1053 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1054 | } | |
1055 | ||
1056 | static inline int pmd_large(pmd_t pmd) | |
1057 | { | |
66c570f5 | 1058 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); |
3df33f12 AK |
1059 | } |
1060 | ||
1061 | static inline pmd_t pmd_mknotpresent(pmd_t pmd) | |
1062 | { | |
1063 | return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); | |
1064 | } | |
1065 | /* | |
1066 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1067 | * the below will work for radix too | |
1068 | */ | |
1069 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1070 | unsigned long addr, pmd_t *pmdp) | |
1071 | { | |
1072 | unsigned long old; | |
1073 | ||
66c570f5 | 1074 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1075 | return 0; |
1076 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1077 | return ((old & _PAGE_ACCESSED) != 0); | |
1078 | } | |
1079 | ||
1080 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
1081 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1082 | pmd_t *pmdp) | |
1083 | { | |
d19469e8 | 1084 | if (__pmd_write((*pmdp))) |
52c50ca7 AK |
1085 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
1086 | else if (unlikely(pmd_savedwrite(*pmdp))) | |
1087 | pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); | |
3dfcb315 AK |
1088 | } |
1089 | ||
ab624762 AK |
1090 | static inline int pmd_trans_huge(pmd_t pmd) |
1091 | { | |
1092 | if (radix_enabled()) | |
1093 | return radix__pmd_trans_huge(pmd); | |
1094 | return hash__pmd_trans_huge(pmd); | |
1095 | } | |
1096 | ||
1097 | #define __HAVE_ARCH_PMD_SAME | |
1098 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1099 | { | |
1100 | if (radix_enabled()) | |
1101 | return radix__pmd_same(pmd_a, pmd_b); | |
1102 | return hash__pmd_same(pmd_a, pmd_b); | |
1103 | } | |
1104 | ||
3dfcb315 AK |
1105 | static inline pmd_t pmd_mkhuge(pmd_t pmd) |
1106 | { | |
ab624762 AK |
1107 | if (radix_enabled()) |
1108 | return radix__pmd_mkhuge(pmd); | |
1109 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1110 | } |
1111 | ||
3dfcb315 AK |
1112 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1113 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1114 | unsigned long address, pmd_t *pmdp, | |
1115 | pmd_t entry, int dirty); | |
1116 | ||
3dfcb315 AK |
1117 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1118 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1119 | unsigned long address, pmd_t *pmdp); | |
3dfcb315 AK |
1120 | |
1121 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1122 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1123 | unsigned long addr, pmd_t *pmdp) | |
1124 | { | |
bde3eb62 AK |
1125 | if (radix_enabled()) |
1126 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1127 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1128 | } | |
3dfcb315 | 1129 | |
3df33f12 AK |
1130 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1131 | unsigned long address, pmd_t *pmdp) | |
1132 | { | |
bde3eb62 AK |
1133 | if (radix_enabled()) |
1134 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1135 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1136 | } | |
3dfcb315 AK |
1137 | #define pmdp_collapse_flush pmdp_collapse_flush |
1138 | ||
1139 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
3df33f12 AK |
1140 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1141 | pmd_t *pmdp, pgtable_t pgtable) | |
1142 | { | |
bde3eb62 AK |
1143 | if (radix_enabled()) |
1144 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1145 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1146 | } | |
1147 | ||
3dfcb315 | 1148 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1149 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1150 | pmd_t *pmdp) | |
1151 | { | |
bde3eb62 AK |
1152 | if (radix_enabled()) |
1153 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1154 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1155 | } | |
3dfcb315 AK |
1156 | |
1157 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
1158 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
1159 | pmd_t *pmdp); | |
1160 | ||
c777e2a8 | 1161 | #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE |
3df33f12 AK |
1162 | static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, |
1163 | unsigned long address, pmd_t *pmdp) | |
1164 | { | |
bde3eb62 AK |
1165 | if (radix_enabled()) |
1166 | return radix__pmdp_huge_split_prepare(vma, address, pmdp); | |
3df33f12 AK |
1167 | return hash__pmdp_huge_split_prepare(vma, address, pmdp); |
1168 | } | |
c777e2a8 | 1169 | |
3dfcb315 AK |
1170 | #define pmd_move_must_withdraw pmd_move_must_withdraw |
1171 | struct spinlock; | |
1172 | static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, | |
1dd38b6c AK |
1173 | struct spinlock *old_pmd_ptl, |
1174 | struct vm_area_struct *vma) | |
3dfcb315 | 1175 | { |
bde3eb62 AK |
1176 | if (radix_enabled()) |
1177 | return false; | |
3dfcb315 AK |
1178 | /* |
1179 | * Archs like ppc64 use pgtable to store per pmd | |
1180 | * specific information. So when we switch the pmd, | |
1181 | * we should also withdraw and deposit the pgtable | |
1182 | */ | |
1183 | return true; | |
1184 | } | |
953c66c2 AK |
1185 | |
1186 | ||
1187 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit | |
1188 | static inline bool arch_needs_pgtable_deposit(void) | |
1189 | { | |
1190 | if (radix_enabled()) | |
1191 | return false; | |
1192 | return true; | |
1193 | } | |
fa4531f7 | 1194 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1195 | |
ebd31197 OH |
1196 | |
1197 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1198 | { | |
1199 | return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); | |
1200 | } | |
1201 | ||
1202 | static inline int pmd_devmap(pmd_t pmd) | |
1203 | { | |
1204 | return pte_devmap(pmd_pte(pmd)); | |
1205 | } | |
1206 | ||
1207 | static inline int pud_devmap(pud_t pud) | |
1208 | { | |
1209 | return 0; | |
1210 | } | |
1211 | ||
1212 | static inline int pgd_devmap(pgd_t pgd) | |
1213 | { | |
1214 | return 0; | |
1215 | } | |
6a1ea362 | 1216 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 OH |
1217 | |
1218 | static inline const int pud_pfn(pud_t pud) | |
1219 | { | |
1220 | /* | |
1221 | * Currently all calls to pud_pfn() are gated around a pud_devmap() | |
1222 | * check so this should never be used. If it grows another user we | |
1223 | * want to know about it. | |
1224 | */ | |
1225 | BUILD_BUG(); | |
1226 | return 0; | |
1227 | } | |
029d9252 | 1228 | |
3dfcb315 AK |
1229 | #endif /* __ASSEMBLY__ */ |
1230 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |