[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / include / asm / cpm.h

#ifndef __CPM_H
#define __CPM_H

#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/of.h>

/*
 * SPI Parameter RAM common to QE and CPM.
 */
struct spi_pram {
	__be16	rbase;	/* Rx Buffer descriptor base address */
	__be16	tbase;	/* Tx Buffer descriptor base address */
	u8	rfcr;	/* Rx function code */
	u8	tfcr;	/* Tx function code */
	__be16	mrblr;	/* Max receive buffer length */
	__be32	rstate;	/* Internal */
	__be32	rdp;	/* Internal */
	__be16	rbptr;	/* Internal */
	__be16	rbc;	/* Internal */
	__be32	rxtmp;	/* Internal */
	__be32	tstate;	/* Internal */
	__be32	tdp;	/* Internal */
	__be16	tbptr;	/* Internal */
	__be16	tbc;	/* Internal */
	__be32	txtmp;	/* Internal */
	__be32	res;	/* Tx temp. */
	__be16  rpbase;	/* Relocation pointer (CPM1 only) */
	__be16	res1;	/* Reserved */
};

/*
 * USB Controller pram common to QE and CPM.
 */
struct usb_ctlr {
	u8	usb_usmod;
	u8	usb_usadr;
	u8	usb_uscom;
	u8	res1[1];
	__be16	usb_usep[4];
	u8	res2[4];
	__be16	usb_usber;
	u8	res3[2];
	__be16	usb_usbmr;
	u8	res4[1];
	u8	usb_usbs;
	/* Fields down below are QE-only */
	__be16	usb_ussft;
	u8	res5[2];
	__be16	usb_usfrn;
	u8	res6[0x22];
} __attribute__ ((packed));

/*
 * Function code bits, usually generic to devices.
 */
#ifdef CONFIG_CPM1
#define CPMFCR_GBL	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
#define CPMFCR_TC2	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
#define CPMFCR_DTB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
#define CPMFCR_BDB	((u_char)0x00)	/* Flag doesn't exist in CPM1 */
#else
#define CPMFCR_GBL	((u_char)0x20)	/* Set memory snooping */
#define CPMFCR_TC2	((u_char)0x04)	/* Transfer code 2 value */
#define CPMFCR_DTB	((u_char)0x02)	/* Use local bus for data when set */
#define CPMFCR_BDB	((u_char)0x01)	/* Use local bus for BD when set */
#endif
#define CPMFCR_EB	((u_char)0x10)	/* Set big endian byte order */

/* Opcodes common to CPM1 and CPM2
*/
#define CPM_CR_INIT_TRX		((ushort)0x0000)
#define CPM_CR_INIT_RX		((ushort)0x0001)
#define CPM_CR_INIT_TX		((ushort)0x0002)
#define CPM_CR_HUNT_MODE	((ushort)0x0003)
#define CPM_CR_STOP_TX		((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX	((ushort)0x0005)
#define CPM_CR_RESTART_TX	((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)
#define CPM_CR_SET_GADDR	((ushort)0x0008)
#define CPM_CR_SET_TIMER	((ushort)0x0008)
#define CPM_CR_STOP_IDMA	((ushort)0x000b)

/* Buffer descriptors used by many of the CPM protocols. */
typedef struct cpm_buf_desc {
	ushort	cbd_sc;		/* Status and Control */
	ushort	cbd_datlen;	/* Data length in buffer */
	uint	cbd_bufaddr;	/* Buffer address in host memory */
} cbd_t;

/* Buffer descriptor control/status used by serial
 */

#define BD_SC_EMPTY	(0x8000)	/* Receive is empty */
#define BD_SC_READY	(0x8000)	/* Transmit is ready */
#define BD_SC_WRAP	(0x2000)	/* Last buffer descriptor */
#define BD_SC_INTRPT	(0x1000)	/* Interrupt on change */
#define BD_SC_LAST	(0x0800)	/* Last buffer in frame */
#define BD_SC_TC	(0x0400)	/* Transmit CRC */
#define BD_SC_CM	(0x0200)	/* Continous mode */
#define BD_SC_ID	(0x0100)	/* Rec'd too many idles */
#define BD_SC_P		(0x0100)	/* xmt preamble */
#define BD_SC_BR	(0x0020)	/* Break received */
#define BD_SC_FR	(0x0010)	/* Framing error */
#define BD_SC_PR	(0x0008)	/* Parity error */
#define BD_SC_NAK	(0x0004)	/* NAK - did not respond */
#define BD_SC_OV	(0x0002)	/* Overrun */
#define BD_SC_UN	(0x0002)	/* Underrun */
#define BD_SC_CD	(0x0001)	/* */
#define BD_SC_CL	(0x0001)	/* Collision */

/* Buffer descriptor control/status used by Ethernet receive.
 * Common to SCC and FCC.
 */
#define BD_ENET_RX_EMPTY	(0x8000)
#define BD_ENET_RX_WRAP		(0x2000)
#define BD_ENET_RX_INTR		(0x1000)
#define BD_ENET_RX_LAST		(0x0800)
#define BD_ENET_RX_FIRST	(0x0400)
#define BD_ENET_RX_MISS		(0x0100)
#define BD_ENET_RX_BC		(0x0080)	/* FCC Only */
#define BD_ENET_RX_MC		(0x0040)	/* FCC Only */
#define BD_ENET_RX_LG		(0x0020)
#define BD_ENET_RX_NO		(0x0010)
#define BD_ENET_RX_SH		(0x0008)
#define BD_ENET_RX_CR		(0x0004)
#define BD_ENET_RX_OV		(0x0002)
#define BD_ENET_RX_CL		(0x0001)
#define BD_ENET_RX_STATS	(0x01ff)	/* All status bits */

/* Buffer descriptor control/status used by Ethernet transmit.
 * Common to SCC and FCC.
 */
#define BD_ENET_TX_READY	(0x8000)
#define BD_ENET_TX_PAD		(0x4000)
#define BD_ENET_TX_WRAP		(0x2000)
#define BD_ENET_TX_INTR		(0x1000)
#define BD_ENET_TX_LAST		(0x0800)
#define BD_ENET_TX_TC		(0x0400)
#define BD_ENET_TX_DEF		(0x0200)
#define BD_ENET_TX_HB		(0x0100)
#define BD_ENET_TX_LC		(0x0080)
#define BD_ENET_TX_RL		(0x0040)
#define BD_ENET_TX_RCMASK	(0x003c)
#define BD_ENET_TX_UN		(0x0002)
#define BD_ENET_TX_CSL		(0x0001)
#define BD_ENET_TX_STATS	(0x03ff)	/* All status bits */

/* Buffer descriptor control/status used by Transparent mode SCC.
 */
#define BD_SCC_TX_LAST		(0x0800)

/* Buffer descriptor control/status used by I2C.
 */
#define BD_I2C_START		(0x0400)

int cpm_muram_init(void);

#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
int cpm_muram_free(unsigned long offset);
unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
void __iomem *cpm_muram_addr(unsigned long offset);
unsigned long cpm_muram_offset(void __iomem *addr);
dma_addr_t cpm_muram_dma(void __iomem *addr);
#else
static inline unsigned long cpm_muram_alloc(unsigned long size,
					    unsigned long align)
{
	return -ENOSYS;
}

static inline int cpm_muram_free(unsigned long offset)
{
	return -ENOSYS;
}

static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
						  unsigned long size)
{
	return -ENOSYS;
}

static inline void __iomem *cpm_muram_addr(unsigned long offset)
{
	return NULL;
}

static inline unsigned long cpm_muram_offset(void __iomem *addr)
{
	return -ENOSYS;
}

static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
{
	return 0;
}
#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */

#ifdef CONFIG_CPM
int cpm_command(u32 command, u8 opcode);
#else
static inline int cpm_command(u32 command, u8 opcode)
{
	return -ENOSYS;
}
#endif /* CONFIG_CPM */

int cpm2_gpiochip_add32(struct device_node *np);

#endif
Commit	Line	Data
15f8c604 SW	1	#ifndef __CPM_H
	2	#define __CPM_H
	3
	4	#include <linux/compiler.h>
	5	#include <linux/types.h>
58c12bdc	6	#include <linux/errno.h>
e193325e	7	#include <linux/of.h>
15f8c604	8
56825c88 AV	9	/*
	10	* SPI Parameter RAM common to QE and CPM.
	11	*/
	12	struct spi_pram {
	13	__be16 rbase; /* Rx Buffer descriptor base address */
	14	__be16 tbase; /* Tx Buffer descriptor base address */
	15	u8 rfcr; /* Rx function code */
	16	u8 tfcr; /* Tx function code */
	17	__be16 mrblr; /* Max receive buffer length */
	18	__be32 rstate; /* Internal */
	19	__be32 rdp; /* Internal */
	20	__be16 rbptr; /* Internal */
	21	__be16 rbc; /* Internal */
	22	__be32 rxtmp; /* Internal */
	23	__be32 tstate; /* Internal */
	24	__be32 tdp; /* Internal */
	25	__be16 tbptr; /* Internal */
	26	__be16 tbc; /* Internal */
	27	__be32 txtmp; /* Internal */
	28	__be32 res; /* Tx temp. */
	29	__be16 rpbase; /* Relocation pointer (CPM1 only) */
	30	__be16 res1; /* Reserved */
	31	};
	32
80952988 AV	33	/*
	34	* USB Controller pram common to QE and CPM.
	35	*/
	36	struct usb_ctlr {
	37	u8 usb_usmod;
	38	u8 usb_usadr;
	39	u8 usb_uscom;
	40	u8 res1[1];
	41	__be16 usb_usep[4];
	42	u8 res2[4];
	43	__be16 usb_usber;
	44	u8 res3[2];
	45	__be16 usb_usbmr;
	46	u8 res4[1];
	47	u8 usb_usbs;
	48	/* Fields down below are QE-only */
	49	__be16 usb_ussft;
	50	u8 res5[2];
	51	__be16 usb_usfrn;
	52	u8 res6[0x22];
	53	} __attribute__ ((packed));
	54
71d94fe8 AV	55	/*
	56	* Function code bits, usually generic to devices.
	57	*/
	58	#ifdef CONFIG_CPM1
	59	#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
	60	#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
	61	#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
	62	#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
	63	#else
	64	#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
	65	#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
	66	#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
	67	#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
	68	#endif
	69	#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
	70
e24e788a LP	71	/* Opcodes common to CPM1 and CPM2
	72	*/
	73	#define CPM_CR_INIT_TRX ((ushort)0x0000)
	74	#define CPM_CR_INIT_RX ((ushort)0x0001)
	75	#define CPM_CR_INIT_TX ((ushort)0x0002)
	76	#define CPM_CR_HUNT_MODE ((ushort)0x0003)
	77	#define CPM_CR_STOP_TX ((ushort)0x0004)
	78	#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
	79	#define CPM_CR_RESTART_TX ((ushort)0x0006)
	80	#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
	81	#define CPM_CR_SET_GADDR ((ushort)0x0008)
	82	#define CPM_CR_SET_TIMER ((ushort)0x0008)
	83	#define CPM_CR_STOP_IDMA ((ushort)0x000b)
	84
44f25fb4 JF	85	/* Buffer descriptors used by many of the CPM protocols. */
	86	typedef struct cpm_buf_desc {
	87	ushort cbd_sc; /* Status and Control */
	88	ushort cbd_datlen; /* Data length in buffer */
	89	uint cbd_bufaddr; /* Buffer address in host memory */
	90	} cbd_t;
	91
	92	/* Buffer descriptor control/status used by serial
	93	*/
	94
	95	#define BD_SC_EMPTY (0x8000) /* Receive is empty */
	96	#define BD_SC_READY (0x8000) /* Transmit is ready */
	97	#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
	98	#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
	99	#define BD_SC_LAST (0x0800) /* Last buffer in frame */
	100	#define BD_SC_TC (0x0400) /* Transmit CRC */
	101	#define BD_SC_CM (0x0200) /* Continous mode */
	102	#define BD_SC_ID (0x0100) /* Rec'd too many idles */
	103	#define BD_SC_P (0x0100) /* xmt preamble */
	104	#define BD_SC_BR (0x0020) /* Break received */
	105	#define BD_SC_FR (0x0010) /* Framing error */
	106	#define BD_SC_PR (0x0008) /* Parity error */
	107	#define BD_SC_NAK (0x0004) /* NAK - did not respond */
	108	#define BD_SC_OV (0x0002) /* Overrun */
	109	#define BD_SC_UN (0x0002) /* Underrun */
	110	#define BD_SC_CD (0x0001) /* */
	111	#define BD_SC_CL (0x0001) /* Collision */
	112
	113	/* Buffer descriptor control/status used by Ethernet receive.
	114	* Common to SCC and FCC.
	115	*/
	116	#define BD_ENET_RX_EMPTY (0x8000)
	117	#define BD_ENET_RX_WRAP (0x2000)
	118	#define BD_ENET_RX_INTR (0x1000)
	119	#define BD_ENET_RX_LAST (0x0800)
	120	#define BD_ENET_RX_FIRST (0x0400)
	121	#define BD_ENET_RX_MISS (0x0100)
	122	#define BD_ENET_RX_BC (0x0080) /* FCC Only */
	123	#define BD_ENET_RX_MC (0x0040) /* FCC Only */
	124	#define BD_ENET_RX_LG (0x0020)
	125	#define BD_ENET_RX_NO (0x0010)
	126	#define BD_ENET_RX_SH (0x0008)
	127	#define BD_ENET_RX_CR (0x0004)
	128	#define BD_ENET_RX_OV (0x0002)
	129	#define BD_ENET_RX_CL (0x0001)
	130	#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
	131
	132	/* Buffer descriptor control/status used by Ethernet transmit.
	133	* Common to SCC and FCC.
	134	*/
	135	#define BD_ENET_TX_READY (0x8000)
	136	#define BD_ENET_TX_PAD (0x4000)
	137	#define BD_ENET_TX_WRAP (0x2000)
	138	#define BD_ENET_TX_INTR (0x1000)
	139	#define BD_ENET_TX_LAST (0x0800)
	140	#define BD_ENET_TX_TC (0x0400)
	141	#define BD_ENET_TX_DEF (0x0200)
	142	#define BD_ENET_TX_HB (0x0100)
	143	#define BD_ENET_TX_LC (0x0080)
	144	#define BD_ENET_TX_RL (0x0040)
	145	#define BD_ENET_TX_RCMASK (0x003c)
	146	#define BD_ENET_TX_UN (0x0002)
	147	#define BD_ENET_TX_CSL (0x0001)
	148	#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
149
150	/* Buffer descriptor control/status used by Transparent mode SCC.
151	*/
152	#define BD_SCC_TX_LAST (0x0800)
153
154	/* Buffer descriptor control/status used by I2C.
155	*/
156	#define BD_I2C_START (0x0400)
157
15f8c604	158	int cpm_muram_init(void);
58c12bdc AV	159
58c12bdc AV	160	#if defined(CONFIG_CPM) \|\| defined(CONFIG_QUICC_ENGINE)
15f8c604 SW	161	unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
	162	int cpm_muram_free(unsigned long offset);
	163	unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
	164	void __iomem *cpm_muram_addr(unsigned long offset);
5093bb96	165	unsigned long cpm_muram_offset(void __iomem *addr);
15f8c604	166	dma_addr_t cpm_muram_dma(void __iomem *addr);
58c12bdc AV	167	#else
	168	static inline unsigned long cpm_muram_alloc(unsigned long size,
	169	unsigned long align)
	170	{
	171	return -ENOSYS;
	172	}
	173
	174	static inline int cpm_muram_free(unsigned long offset)
	175	{
	176	return -ENOSYS;
	177	}
	178
	179	static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
	180	unsigned long size)
	181	{
	182	return -ENOSYS;
	183	}
	184
	185	static inline void __iomem *cpm_muram_addr(unsigned long offset)
	186	{
	187	return NULL;
	188	}
	189
	190	static inline unsigned long cpm_muram_offset(void __iomem *addr)
	191	{
	192	return -ENOSYS;
	193	}
	194
	195	static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
	196	{
	197	return 0;
	198	}
	199	#endif /* defined(CONFIG_CPM) \|\| defined(CONFIG_QUICC_ENGINE) */
	200
	201	#ifdef CONFIG_CPM
362f9b6f	202	int cpm_command(u32 command, u8 opcode);
58c12bdc AV	203	#else
	204	static inline int cpm_command(u32 command, u8 opcode)
	205	{
	206	return -ENOSYS;
	207	}
	208	#endif /* CONFIG_CPM */
15f8c604	209
e193325e LP	210	int cpm2_gpiochip_add32(struct device_node *np);
e193325e LP	211
15f8c604	212	#endif