[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / include / asm / dma.h

#ifndef _ASM_POWERPC_DMA_H
#define _ASM_POWERPC_DMA_H
#ifdef __KERNEL__

/*
 * Defines for using and allocating dma channels.
 * Written by Hennus Bergman, 1992.
 * High DMA channel support & info by Hannu Savolainen
 * and John Boyd, Nov. 1992.
 * Changes for ppc sound by Christoph Nadig
 */

/*
 * Note: Adapted for PowerPC by Gary Thomas
 * Modified by Cort Dougan <cort@cs.nmt.edu>
 *
 * None of this really applies for Power Macintoshes.  There is
 * basically just enough here to get kernel/dma.c to compile.
 */

#include <asm/io.h>
#include <linux/spinlock.h>

#ifndef MAX_DMA_CHANNELS
#define MAX_DMA_CHANNELS	8
#endif

/* The maximum address that we can perform a DMA transfer to on this platform */
/* Doesn't really apply... */
#define MAX_DMA_ADDRESS		(~0UL)

#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb	outb_p
#else
#define dma_outb	outb
#endif

#define dma_inb		inb

/*
 * NOTES about DMA transfers:
 *
 *  controller 1: channels 0-3, byte operations, ports 00-1F
 *  controller 2: channels 4-7, word operations, ports C0-DF
 *
 *  - ALL registers are 8 bits only, regardless of transfer size
 *  - channel 4 is not used - cascades 1 into 2.
 *  - channels 0-3 are byte - addresses/counts are for physical bytes
 *  - channels 5-7 are word - addresses/counts are for physical words
 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
 *  - transfer count loaded to registers is 1 less than actual count
 *  - controller 2 offsets are all even (2x offsets for controller 1)
 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
 *  - page registers for 0-3 use bit 0, represent 64K pages
 *
 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
 * Note that addresses loaded into registers must be _physical_ addresses,
 * not logical addresses (which may differ if paging is active).
 *
 *  Address mapping for channels 0-3:
 *
 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *   P7  ...  P0  A7 ... A0  A7 ... A0
 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
 *
 *  Address mapping for channels 5-7:
 *
 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
 *    |  ...  |   \   \   ... \  \  \  ... \  \
 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
 *    |  ...  |     \   \   ... \  \  \  ... \
 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
 *
 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
 * the hardware level, so odd-byte transfers aren't possible).
 *
 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
 *
 */

/* 8237 DMA controllers */
#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */

/* DMA controller registers */
#define DMA1_CMD_REG		0x08	/* command register (w) */
#define DMA1_STAT_REG		0x08	/* status register (r) */
#define DMA1_REQ_REG		0x09	/* request register (w) */
#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
#define DMA1_MODE_REG		0x0B	/* mode register (w) */
#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG		0x0D	/* Temporary Register (r) */
#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
#define DMA1_CLR_MASK_REG	0x0E	/* Clear Mask */
#define DMA1_MASK_ALL_REG	0x0F	/* all-channels mask (w) */

#define DMA2_CMD_REG		0xD0	/* command register (w) */
#define DMA2_STAT_REG		0xD0	/* status register (r) */
#define DMA2_REQ_REG		0xD2	/* request register (w) */
#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
#define DMA2_MODE_REG		0xD6	/* mode register (w) */
#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG		0xDA	/* Temporary Register (r) */
#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
#define DMA2_CLR_MASK_REG	0xDC	/* Clear Mask */
#define DMA2_MASK_ALL_REG	0xDE	/* all-channels mask (w) */

#define DMA_ADDR_0		0x00	/* DMA address registers */
#define DMA_ADDR_1		0x02
#define DMA_ADDR_2		0x04
#define DMA_ADDR_3		0x06
#define DMA_ADDR_4		0xC0
#define DMA_ADDR_5		0xC4
#define DMA_ADDR_6		0xC8
#define DMA_ADDR_7		0xCC

#define DMA_CNT_0		0x01	/* DMA count registers */
#define DMA_CNT_1		0x03
#define DMA_CNT_2		0x05
#define DMA_CNT_3		0x07
#define DMA_CNT_4		0xC2
#define DMA_CNT_5		0xC6
#define DMA_CNT_6		0xCA
#define DMA_CNT_7		0xCE

#define DMA_LO_PAGE_0		0x87	/* DMA page registers */
#define DMA_LO_PAGE_1		0x83
#define DMA_LO_PAGE_2		0x81
#define DMA_LO_PAGE_3		0x82
#define DMA_LO_PAGE_5		0x8B
#define DMA_LO_PAGE_6		0x89
#define DMA_LO_PAGE_7		0x8A

#define DMA_HI_PAGE_0		0x487	/* DMA page registers */
#define DMA_HI_PAGE_1		0x483
#define DMA_HI_PAGE_2		0x481
#define DMA_HI_PAGE_3		0x482
#define DMA_HI_PAGE_5		0x48B
#define DMA_HI_PAGE_6		0x489
#define DMA_HI_PAGE_7		0x48A

#define DMA1_EXT_REG		0x40B
#define DMA2_EXT_REG		0x4D6

#ifndef __powerpc64__
    /* in arch/ppc/kernel/setup.c -- Cort */
    extern unsigned int DMA_MODE_WRITE;
    extern unsigned int DMA_MODE_READ;
    extern unsigned long ISA_DMA_THRESHOLD;
#else
    #define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
    #define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
#endif

#define DMA_MODE_CASCADE	0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */

#define DMA_AUTOINIT		0x10

extern spinlock_t dma_spin_lock;

static __inline__ unsigned long claim_dma_lock(void)
{
	unsigned long flags;
	spin_lock_irqsave(&dma_spin_lock, flags);
	return flags;
}

static __inline__ void release_dma_lock(unsigned long flags)
{
	spin_unlock_irqrestore(&dma_spin_lock, flags);
}

/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
	unsigned char ucDmaCmd = 0x00;

	if (dmanr != 4) {
		dma_outb(0, DMA2_MASK_REG);	/* This may not be enabled */
		dma_outb(ucDmaCmd, DMA2_CMD_REG);	/* Enable group */
	}
	if (dmanr <= 3) {
		dma_outb(dmanr, DMA1_MASK_REG);
		dma_outb(ucDmaCmd, DMA1_CMD_REG);	/* Enable group */
	} else {
		dma_outb(dmanr & 3, DMA2_MASK_REG);
	}
}

static __inline__ void disable_dma(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(dmanr | 4, DMA1_MASK_REG);
	else
		dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}

/* Clear the 'DMA Pointer Flip Flop'.
 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 * Use this once to initialize the FF to a known state.
 * After that, keep track of it. :-)
 * --- In order to do that, the DMA routines below should ---
 * --- only be used while interrupts are disabled! ---
 */
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(0, DMA1_CLEAR_FF_REG);
	else
		dma_outb(0, DMA2_CLEAR_FF_REG);
}

/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
	if (dmanr <= 3)
		dma_outb(mode | dmanr, DMA1_MODE_REG);
	else
		dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
}

/* Set only the page register bits of the transfer address.
 * This is used for successive transfers when we know the contents of
 * the lower 16 bits of the DMA current address register, but a 64k boundary
 * may have been crossed.
 */
static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
{
	switch (dmanr) {
	case 0:
		dma_outb(pagenr, DMA_LO_PAGE_0);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
		break;
	case 1:
		dma_outb(pagenr, DMA_LO_PAGE_1);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
		break;
	case 2:
		dma_outb(pagenr, DMA_LO_PAGE_2);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
		break;
	case 3:
		dma_outb(pagenr, DMA_LO_PAGE_3);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
		break;
	case 5:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
		break;
	case 6:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
		break;
	case 7:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
		break;
	}
}

/* Set transfer address & page bits for specific DMA channel.
 * Assumes dma flipflop is clear.
 */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
{
	if (dmanr <= 3) {
		dma_outb(phys & 0xff,
			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
		dma_outb((phys >> 8) & 0xff,
			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
	} else {
		dma_outb((phys >> 1) & 0xff,
			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
		dma_outb((phys >> 9) & 0xff,
			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
	}
	set_dma_page(dmanr, phys >> 16);
}


/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 * a specific DMA channel.
 * You must ensure the parameters are valid.
 * NOTE: from a manual: "the number of transfers is one more
 * than the initial word count"! This is taken into account.
 * Assumes dma flip-flop is clear.
 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 */
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
	count--;
	if (dmanr <= 3) {
		dma_outb(count & 0xff,
			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
		dma_outb((count >> 8) & 0xff,
			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
	} else {
		dma_outb((count >> 1) & 0xff,
			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
		dma_outb((count >> 9) & 0xff,
			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
	}
}


/* Get DMA residue count. After a DMA transfer, this
 * should return zero. Reading this while a DMA transfer is
 * still in progress will return unpredictable results.
 * If called before the channel has been used, it may return 1.
 * Otherwise, it returns the number of _bytes_ left to transfer.
 *
 * Assumes DMA flip-flop is clear.
 */
static __inline__ int get_dma_residue(unsigned int dmanr)
{
	unsigned int io_port = (dmanr <= 3)
	    ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
	    : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;

	/* using short to get 16-bit wrap around */
	unsigned short count;

	count = 1 + dma_inb(io_port);
	count += dma_inb(io_port) << 8;

	return (dmanr <= 3) ? count : (count << 1);
}

/* These are in kernel/dma.c: */

/* reserve a DMA channel */
extern int request_dma(unsigned int dmanr, const char *device_id);
/* release it again */
extern void free_dma(unsigned int dmanr);

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy	(0)
#endif

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_DMA_H */
Commit	Line	Data
b8f114db JL	1	#ifndef _ASM_POWERPC_DMA_H
b8f114db JL	2	#define _ASM_POWERPC_DMA_H
88ced031	3	#ifdef __KERNEL__
b8f114db	4
1da177e4	5	/*
b8f114db	6	* Defines for using and allocating dma channels.
1da177e4 LT	7	* Written by Hennus Bergman, 1992.
	8	* High DMA channel support & info by Hannu Savolainen
	9	* and John Boyd, Nov. 1992.
	10	* Changes for ppc sound by Christoph Nadig
	11	*/
	12
1da177e4 LT	13	/*
	14	* Note: Adapted for PowerPC by Gary Thomas
	15	* Modified by Cort Dougan <cort@cs.nmt.edu>
	16	*
	17	* None of this really applies for Power Macintoshes. There is
	18	* basically just enough here to get kernel/dma.c to compile.
1da177e4 LT	19	*/
1da177e4 LT	20
b8f114db JL	21	#include <asm/io.h>
b8f114db JL	22	#include <linux/spinlock.h>
1da177e4 LT	23
	24	#ifndef MAX_DMA_CHANNELS
	25	#define MAX_DMA_CHANNELS 8
	26	#endif
	27
	28	/* The maximum address that we can perform a DMA transfer to on this platform */
	29	/* Doesn't really apply... */
b8f114db	30	#define MAX_DMA_ADDRESS (~0UL)
1da177e4	31
1da177e4 LT	32	#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
	33	#define dma_outb outb_p
	34	#else
	35	#define dma_outb outb
	36	#endif
	37
	38	#define dma_inb inb
	39
	40	/*
	41	* NOTES about DMA transfers:
	42	*
	43	* controller 1: channels 0-3, byte operations, ports 00-1F
	44	* controller 2: channels 4-7, word operations, ports C0-DF
	45	*
	46	* - ALL registers are 8 bits only, regardless of transfer size
	47	* - channel 4 is not used - cascades 1 into 2.
	48	* - channels 0-3 are byte - addresses/counts are for physical bytes
	49	* - channels 5-7 are word - addresses/counts are for physical words
	50	* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
	51	* - transfer count loaded to registers is 1 less than actual count
	52	* - controller 2 offsets are all even (2x offsets for controller 1)
	53	* - page registers for 5-7 don't use data bit 0, represent 128K pages
	54	* - page registers for 0-3 use bit 0, represent 64K pages
	55	*
1da177e4 LT	56	* On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
	57	* Note that addresses loaded into registers must be _physical_ addresses,
	58	* not logical addresses (which may differ if paging is active).
	59	*
	60	* Address mapping for channels 0-3:
	61	*
	62	* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
	63	* \| ... \| \| ... \| \| ... \|
	64	* \| ... \| \| ... \| \| ... \|
	65	* \| ... \| \| ... \| \| ... \|
	66	* P7 ... P0 A7 ... A0 A7 ... A0
	67	* \| Page \| Addr MSB \| Addr LSB \| (DMA registers)
	68	*
	69	* Address mapping for channels 5-7:
	70	*
	71	* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
	72	* \| ... \| \ \ ... \ \ \ ... \ \
	73	* \| ... \| \ \ ... \ \ \ ... \ (not used)
	74	* \| ... \| \ \ ... \ \ \ ... \
	75	* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
	76	* \| Page \| Addr MSB \| Addr LSB \| (DMA registers)
	77	*
	78	* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
	79	* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
	80	* the hardware level, so odd-byte transfers aren't possible).
	81	*
	82	* Transfer count (_not # bytes_) is limited to 64K, represented as actual
	83	* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
	84	* and up to 128K bytes may be transferred on channels 5-7 in one operation.
	85	*
	86	*/
	87
1da177e4 LT	88	/* 8237 DMA controllers */
	89	#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
	90	#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
	91
	92	/* DMA controller registers */
	93	#define DMA1_CMD_REG 0x08 /* command register (w) */
	94	#define DMA1_STAT_REG 0x08 /* status register (r) */
	95	#define DMA1_REQ_REG 0x09 /* request register (w) */
	96	#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
	97	#define DMA1_MODE_REG 0x0B /* mode register (w) */
	98	#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
	99	#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
	100	#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
	101	#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
	102	#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
	103
	104	#define DMA2_CMD_REG 0xD0 /* command register (w) */
	105	#define DMA2_STAT_REG 0xD0 /* status register (r) */
	106	#define DMA2_REQ_REG 0xD2 /* request register (w) */
	107	#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
	108	#define DMA2_MODE_REG 0xD6 /* mode register (w) */
	109	#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
	110	#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
	111	#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
	112	#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
	113	#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
	114
	115	#define DMA_ADDR_0 0x00 /* DMA address registers */
	116	#define DMA_ADDR_1 0x02
	117	#define DMA_ADDR_2 0x04
	118	#define DMA_ADDR_3 0x06
	119	#define DMA_ADDR_4 0xC0
	120	#define DMA_ADDR_5 0xC4
	121	#define DMA_ADDR_6 0xC8
	122	#define DMA_ADDR_7 0xCC
	123
	124	#define DMA_CNT_0 0x01 /* DMA count registers */
	125	#define DMA_CNT_1 0x03
	126	#define DMA_CNT_2 0x05
	127	#define DMA_CNT_3 0x07
	128	#define DMA_CNT_4 0xC2
	129	#define DMA_CNT_5 0xC6
	130	#define DMA_CNT_6 0xCA
	131	#define DMA_CNT_7 0xCE
	132
	133	#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
	134	#define DMA_LO_PAGE_1 0x83
	135	#define DMA_LO_PAGE_2 0x81
	136	#define DMA_LO_PAGE_3 0x82
	137	#define DMA_LO_PAGE_5 0x8B
	138	#define DMA_LO_PAGE_6 0x89
	139	#define DMA_LO_PAGE_7 0x8A
	140
	141	#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
	142	#define DMA_HI_PAGE_1 0x483
	143	#define DMA_HI_PAGE_2 0x481
	144	#define DMA_HI_PAGE_3 0x482
	145	#define DMA_HI_PAGE_5 0x48B
	146	#define DMA_HI_PAGE_6 0x489
	147	#define DMA_HI_PAGE_7 0x48A
	148
	149	#define DMA1_EXT_REG 0x40B
	150	#define DMA2_EXT_REG 0x4D6
	151
b8f114db JL	152	#ifndef __powerpc64__
	153	/* in arch/ppc/kernel/setup.c -- Cort */
	154	extern unsigned int DMA_MODE_WRITE;
	155	extern unsigned int DMA_MODE_READ;
	156	extern unsigned long ISA_DMA_THRESHOLD;
	157	#else
	158	#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
	159	#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
	160	#endif
	161
1da177e4	162	#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
b8f114db	163
1da177e4 LT	164	#define DMA_AUTOINIT 0x10
	165
	166	extern spinlock_t dma_spin_lock;
	167
	168	static __inline__ unsigned long claim_dma_lock(void)
	169	{
	170	unsigned long flags;
	171	spin_lock_irqsave(&dma_spin_lock, flags);
	172	return flags;
	173	}
	174
	175	static __inline__ void release_dma_lock(unsigned long flags)
	176	{
	177	spin_unlock_irqrestore(&dma_spin_lock, flags);
	178	}
	179
	180	/* enable/disable a specific DMA channel */
	181	static __inline__ void enable_dma(unsigned int dmanr)
	182	{
	183	unsigned char ucDmaCmd = 0x00;
	184
	185	if (dmanr != 4) {
	186	dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
	187	dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
	188	}
	189	if (dmanr <= 3) {
	190	dma_outb(dmanr, DMA1_MASK_REG);
	191	dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
b8f114db	192	} else {
1da177e4	193	dma_outb(dmanr & 3, DMA2_MASK_REG);
b8f114db	194	}
1da177e4 LT	195	}
	196
	197	static __inline__ void disable_dma(unsigned int dmanr)
	198	{
	199	if (dmanr <= 3)
	200	dma_outb(dmanr \| 4, DMA1_MASK_REG);
	201	else
	202	dma_outb((dmanr & 3) \| 4, DMA2_MASK_REG);
	203	}
	204
	205	/* Clear the 'DMA Pointer Flip Flop'.
	206	* Write 0 for LSB/MSB, 1 for MSB/LSB access.
	207	* Use this once to initialize the FF to a known state.
	208	* After that, keep track of it. :-)
	209	* --- In order to do that, the DMA routines below should ---
	210	* --- only be used while interrupts are disabled! ---
	211	*/
	212	static __inline__ void clear_dma_ff(unsigned int dmanr)
	213	{
	214	if (dmanr <= 3)
	215	dma_outb(0, DMA1_CLEAR_FF_REG);
	216	else
	217	dma_outb(0, DMA2_CLEAR_FF_REG);
	218	}
	219
	220	/* set mode (above) for a specific DMA channel */
	221	static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
	222	{
	223	if (dmanr <= 3)
	224	dma_outb(mode \| dmanr, DMA1_MODE_REG);
	225	else
	226	dma_outb(mode \| (dmanr & 3), DMA2_MODE_REG);
	227	}
	228
	229	/* Set only the page register bits of the transfer address.
	230	* This is used for successive transfers when we know the contents of
	231	* the lower 16 bits of the DMA current address register, but a 64k boundary
	232	* may have been crossed.
	233	*/
	234	static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
	235	{
	236	switch (dmanr) {
	237	case 0:
	238	dma_outb(pagenr, DMA_LO_PAGE_0);
	239	dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
	240	break;
	241	case 1:
	242	dma_outb(pagenr, DMA_LO_PAGE_1);
	243	dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
	244	break;
	245	case 2:
	246	dma_outb(pagenr, DMA_LO_PAGE_2);
	247	dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
	248	break;
	249	case 3:
	250	dma_outb(pagenr, DMA_LO_PAGE_3);
	251	dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
	252	break;
	253	case 5:
83bad1d7	254	dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
1da177e4 LT	255	dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
	256	break;
	257	case 6:
83bad1d7	258	dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
1da177e4 LT	259	dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
	260	break;
	261	case 7:
83bad1d7	262	dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
1da177e4 LT	263	dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
	264	break;
	265	}
	266	}
	267
	268	/* Set transfer address & page bits for specific DMA channel.
	269	* Assumes dma flipflop is clear.
	270	*/
	271	static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
	272	{
	273	if (dmanr <= 3) {
b8f114db JL	274	dma_outb(phys & 0xff,
	275	((dmanr & 3) << 1) + IO_DMA1_BASE);
	276	dma_outb((phys >> 8) & 0xff,
	277	((dmanr & 3) << 1) + IO_DMA1_BASE);
1da177e4	278	} else {
b8f114db JL	279	dma_outb((phys >> 1) & 0xff,
	280	((dmanr & 3) << 2) + IO_DMA2_BASE);
	281	dma_outb((phys >> 9) & 0xff,
	282	((dmanr & 3) << 2) + IO_DMA2_BASE);
1da177e4 LT	283	}
	284	set_dma_page(dmanr, phys >> 16);
	285	}
	286
b8f114db	287
1da177e4 LT	288	/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
	289	* a specific DMA channel.
	290	* You must ensure the parameters are valid.
	291	* NOTE: from a manual: "the number of transfers is one more
	292	* than the initial word count"! This is taken into account.
	293	* Assumes dma flip-flop is clear.
	294	* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
	295	*/
	296	static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
	297	{
	298	count--;
	299	if (dmanr <= 3) {
b8f114db JL	300	dma_outb(count & 0xff,
	301	((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
	302	dma_outb((count >> 8) & 0xff,
	303	((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
1da177e4	304	} else {
b8f114db JL	305	dma_outb((count >> 1) & 0xff,
	306	((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
	307	dma_outb((count >> 9) & 0xff,
	308	((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
1da177e4 LT	309	}
	310	}
	311
b8f114db	312
1da177e4 LT	313	/* Get DMA residue count. After a DMA transfer, this
	314	* should return zero. Reading this while a DMA transfer is
	315	* still in progress will return unpredictable results.
	316	* If called before the channel has been used, it may return 1.
	317	* Otherwise, it returns the number of _bytes_ left to transfer.
	318	*
	319	* Assumes DMA flip-flop is clear.
	320	*/
	321	static __inline__ int get_dma_residue(unsigned int dmanr)
	322	{
b8f114db JL	323	unsigned int io_port = (dmanr <= 3)
b8f114db JL	324	? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
1da177e4 LT	325	: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
	326
	327	/* using short to get 16-bit wrap around */
	328	unsigned short count;
	329
	330	count = 1 + dma_inb(io_port);
	331	count += dma_inb(io_port) << 8;
	332
83bad1d7	333	return (dmanr <= 3) ? count : (count << 1);
1da177e4 LT	334	}
	335
	336	/* These are in kernel/dma.c: */
	337
	338	/* reserve a DMA channel */
	339	extern int request_dma(unsigned int dmanr, const char *device_id);
	340	/* release it again */
	341	extern void free_dma(unsigned int dmanr);
	342
	343	#ifdef CONFIG_PCI
	344	extern int isa_dma_bridge_buggy;
	345	#else
	346	#define isa_dma_bridge_buggy (0)
	347	#endif
b8f114db	348
88ced031	349	#endif /* __KERNEL__ */
b8f114db	350	#endif /* _ASM_POWERPC_DMA_H */