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Commit | Line | Data |
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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
172ca926 | 2 | /* |
1da177e4 | 3 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. |
cb3bc9d0 | 4 | * Copyright 2001-2012 IBM Corporation. |
1da177e4 LT |
5 | */ |
6 | ||
8b8da358 BH |
7 | #ifndef _POWERPC_EEH_H |
8 | #define _POWERPC_EEH_H | |
88ced031 | 9 | #ifdef __KERNEL__ |
1da177e4 | 10 | |
1da177e4 LT |
11 | #include <linux/init.h> |
12 | #include <linux/list.h> | |
13 | #include <linux/string.h> | |
5a71978e | 14 | #include <linux/time.h> |
05ec424e | 15 | #include <linux/atomic.h> |
1da177e4 | 16 | |
ed3e81ff GS |
17 | #include <uapi/asm/eeh.h> |
18 | ||
1da177e4 | 19 | struct pci_dev; |
827c1a6c | 20 | struct pci_bus; |
e8e9b34c | 21 | struct pci_dn; |
1da177e4 LT |
22 | |
23 | #ifdef CONFIG_EEH | |
24 | ||
8a5ad356 | 25 | /* EEH subsystem flags */ |
ee8c446f MR |
26 | #define EEH_ENABLED 0x01 /* EEH enabled */ |
27 | #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ | |
28 | #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ | |
29 | #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ | |
30 | #define EEH_VALID_PE_ZERO 0x10 /* PE#0 is valid */ | |
31 | #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */ | |
32 | #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */ | |
8a5ad356 | 33 | |
26833a50 GS |
34 | /* |
35 | * Delay for PE reset, all in ms | |
36 | * | |
37 | * PCI specification has reset hold time of 100 milliseconds. | |
38 | * We have 250 milliseconds here. The PCI bus settlement time | |
39 | * is specified as 1.5 seconds and we have 1.8 seconds. | |
40 | */ | |
41 | #define EEH_PE_RST_HOLD_TIME 250 | |
42 | #define EEH_PE_RST_SETTLE_TIME 1800 | |
43 | ||
968f968f GS |
44 | /* |
45 | * The struct is used to trace PE related EEH functionality. | |
46 | * In theory, there will have one instance of the struct to | |
027dfac6 | 47 | * be created against particular PE. In nature, PEs correlate |
968f968f GS |
48 | * to each other. the struct has to reflect that hierarchy in |
49 | * order to easily pick up those affected PEs when one particular | |
50 | * PE has EEH errors. | |
51 | * | |
52 | * Also, one particular PE might be composed of PCI device, PCI | |
53 | * bus and its subordinate components. The struct also need ship | |
54 | * the information. Further more, one particular PE is only meaingful | |
55 | * in the corresponding PHB. Therefore, the root PEs should be created | |
56 | * against existing PHBs in on-to-one fashion. | |
57 | */ | |
5efc3ad7 GS |
58 | #define EEH_PE_INVALID (1 << 0) /* Invalid */ |
59 | #define EEH_PE_PHB (1 << 1) /* PHB PE */ | |
60 | #define EEH_PE_DEVICE (1 << 2) /* Device PE */ | |
61 | #define EEH_PE_BUS (1 << 3) /* Bus PE */ | |
c29fa27d | 62 | #define EEH_PE_VF (1 << 4) /* VF PE */ |
968f968f GS |
63 | |
64 | #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ | |
65 | #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ | |
8a6b3710 | 66 | #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ |
28bf36f9 | 67 | #define EEH_PE_RESET (1 << 3) /* PE reset in progress */ |
968f968f | 68 | |
807a827d | 69 | #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ |
b6541db1 | 70 | #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ |
432227e9 | 71 | #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */ |
05ba75f8 | 72 | #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */ |
807a827d | 73 | |
968f968f GS |
74 | struct eeh_pe { |
75 | int type; /* PE type: PHB/Bus/Device */ | |
76 | int state; /* PE EEH dependent mode */ | |
77 | int config_addr; /* Traditional PCI address */ | |
78 | int addr; /* PE configuration address */ | |
79 | struct pci_controller *phb; /* Associated PHB */ | |
8cdb2833 | 80 | struct pci_bus *bus; /* Top PCI bus for bus PE */ |
968f968f GS |
81 | int check_count; /* Times of ignored error */ |
82 | int freeze_count; /* Times of froze up */ | |
edfd17ff | 83 | time64_t tstamp; /* Time on first-time freeze */ |
968f968f | 84 | int false_positives; /* Times of reported #ff's */ |
05ec424e | 85 | atomic_t pass_dev_cnt; /* Count of passed through devs */ |
968f968f | 86 | struct eeh_pe *parent; /* Parent PE */ |
bb593c00 | 87 | void *data; /* PE auxillary data */ |
80e65b00 SB |
88 | struct list_head child_list; /* List of PEs below this PE */ |
89 | struct list_head child; /* Memb. child_list/eeh_phb_pe */ | |
90 | struct list_head edevs; /* List of eeh_dev in this PE */ | |
968f968f GS |
91 | }; |
92 | ||
9feed42e | 93 | #define eeh_pe_for_each_dev(pe, edev, tmp) \ |
80e65b00 | 94 | list_for_each_entry_safe(edev, tmp, &pe->edevs, entry) |
5b663529 | 95 | |
309ed3a7 SB |
96 | #define eeh_for_each_pe(root, pe) \ |
97 | for (pe = root; pe; pe = eeh_pe_next(pe, root)) | |
98 | ||
05ec424e GS |
99 | static inline bool eeh_pe_passed(struct eeh_pe *pe) |
100 | { | |
101 | return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; | |
102 | } | |
103 | ||
eb740b5f GS |
104 | /* |
105 | * The struct is used to trace EEH state for the associated | |
106 | * PCI device node or PCI device. In future, it might | |
107 | * represent PE as well so that the EEH device to form | |
108 | * another tree except the currently existing tree of PCI | |
109 | * buses and PCI devices | |
110 | */ | |
4b83bd45 GS |
111 | #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ |
112 | #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ | |
113 | #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ | |
114 | #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ | |
115 | #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ | |
eb740b5f | 116 | |
f26c7a03 GS |
117 | #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ |
118 | #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ | |
d2b0f6f7 | 119 | #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ |
ab55d218 | 120 | |
eb740b5f GS |
121 | struct eeh_dev { |
122 | int mode; /* EEH mode */ | |
123 | int class_code; /* Class code of the device */ | |
eb740b5f | 124 | int pe_config_addr; /* PE config address */ |
eb740b5f | 125 | u32 config_space[16]; /* Saved PCI config space */ |
2a18dfc6 GS |
126 | int pcix_cap; /* Saved PCIx capability */ |
127 | int pcie_cap; /* Saved PCIe capability */ | |
128 | int aer_cap; /* Saved AER capability */ | |
9312bc5b | 129 | int af_cap; /* Saved AF capability */ |
968f968f | 130 | struct eeh_pe *pe; /* Associated PE */ |
80e65b00 SB |
131 | struct list_head entry; /* Membership in eeh_pe.edevs */ |
132 | struct list_head rmv_entry; /* Membership in rmv_list */ | |
e8e9b34c | 133 | struct pci_dn *pdn; /* Associated PCI device node */ |
eb740b5f | 134 | struct pci_dev *pdev; /* Associated PCI device */ |
67086e32 | 135 | bool in_error; /* Error flag for edev */ |
39218cd0 | 136 | struct pci_dev *physfn; /* Associated SRIOV PF */ |
eb740b5f GS |
137 | }; |
138 | ||
e8e9b34c GS |
139 | static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev) |
140 | { | |
141 | return edev ? edev->pdn : NULL; | |
142 | } | |
143 | ||
eb740b5f GS |
144 | static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) |
145 | { | |
2d5c1216 | 146 | return edev ? edev->pdev : NULL; |
eb740b5f GS |
147 | } |
148 | ||
2a58222f WY |
149 | static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) |
150 | { | |
151 | return edev ? edev->pe : NULL; | |
152 | } | |
153 | ||
7e4e7867 GS |
154 | /* Return values from eeh_ops::next_error */ |
155 | enum { | |
156 | EEH_NEXT_ERR_NONE = 0, | |
157 | EEH_NEXT_ERR_INF, | |
158 | EEH_NEXT_ERR_FROZEN_PE, | |
159 | EEH_NEXT_ERR_FENCED_PHB, | |
160 | EEH_NEXT_ERR_DEAD_PHB, | |
161 | EEH_NEXT_ERR_DEAD_IOC | |
162 | }; | |
163 | ||
aa1e6374 GS |
164 | /* |
165 | * The struct is used to trace the registered EEH operation | |
166 | * callback functions. Actually, those operation callback | |
167 | * functions are heavily platform dependent. That means the | |
168 | * platform should register its own EEH operation callback | |
169 | * functions before any EEH further operations. | |
170 | */ | |
8fb8f709 GS |
171 | #define EEH_OPT_DISABLE 0 /* EEH disable */ |
172 | #define EEH_OPT_ENABLE 1 /* EEH enable */ | |
173 | #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ | |
174 | #define EEH_OPT_THAW_DMA 3 /* DMA enable */ | |
0d5ee520 | 175 | #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ |
eb594a47 GS |
176 | #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ |
177 | #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ | |
178 | #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ | |
179 | #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ | |
180 | #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ | |
181 | #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ | |
182 | #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ | |
2652481f GS |
183 | #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ |
184 | #define EEH_RESET_HOT 1 /* Hot reset */ | |
185 | #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ | |
8d633291 GS |
186 | #define EEH_LOG_TEMP 1 /* EEH temporary error log */ |
187 | #define EEH_LOG_PERM 2 /* EEH permanent error log */ | |
eb594a47 | 188 | |
aa1e6374 GS |
189 | struct eeh_ops { |
190 | char *name; | |
191 | int (*init)(void); | |
ff57b454 | 192 | void* (*probe)(struct pci_dn *pdn, void *data); |
371a395d GS |
193 | int (*set_option)(struct eeh_pe *pe, int option); |
194 | int (*get_pe_addr)(struct eeh_pe *pe); | |
fef7f905 | 195 | int (*get_state)(struct eeh_pe *pe, int *delay); |
371a395d | 196 | int (*reset)(struct eeh_pe *pe, int option); |
371a395d GS |
197 | int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); |
198 | int (*configure_bridge)(struct eeh_pe *pe); | |
131c123a GS |
199 | int (*err_inject)(struct eeh_pe *pe, int type, int func, |
200 | unsigned long addr, unsigned long mask); | |
0bd78587 GS |
201 | int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val); |
202 | int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val); | |
8a6b1bc7 | 203 | int (*next_error)(struct eeh_pe **pe); |
0bd78587 | 204 | int (*restore_config)(struct pci_dn *pdn); |
67923cfc | 205 | int (*notify_resume)(struct pci_dn *pdn); |
aa1e6374 GS |
206 | }; |
207 | ||
8a5ad356 | 208 | extern int eeh_subsystem_flags; |
46ee7c3c | 209 | extern u32 eeh_max_freezes; |
6b493f60 | 210 | extern bool eeh_debugfs_no_recover; |
aa1e6374 | 211 | extern struct eeh_ops *eeh_ops; |
4907581d | 212 | extern raw_spinlock_t confirm_error_lock; |
d7bb8862 | 213 | |
05b1721d | 214 | static inline void eeh_add_flag(int flag) |
2ec5a0ad | 215 | { |
05b1721d | 216 | eeh_subsystem_flags |= flag; |
2ec5a0ad GS |
217 | } |
218 | ||
05b1721d | 219 | static inline void eeh_clear_flag(int flag) |
2ec5a0ad | 220 | { |
05b1721d | 221 | eeh_subsystem_flags &= ~flag; |
2ec5a0ad GS |
222 | } |
223 | ||
05b1721d | 224 | static inline bool eeh_has_flag(int flag) |
d7bb8862 | 225 | { |
05b1721d | 226 | return !!(eeh_subsystem_flags & flag); |
d7bb8862 GS |
227 | } |
228 | ||
05b1721d | 229 | static inline bool eeh_enabled(void) |
d7bb8862 | 230 | { |
54644927 | 231 | return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED); |
d7bb8862 | 232 | } |
646a8499 | 233 | |
4907581d GS |
234 | static inline void eeh_serialize_lock(unsigned long *flags) |
235 | { | |
236 | raw_spin_lock_irqsave(&confirm_error_lock, *flags); | |
237 | } | |
238 | ||
239 | static inline void eeh_serialize_unlock(unsigned long flags) | |
240 | { | |
241 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); | |
242 | } | |
243 | ||
34a286a4 SB |
244 | static inline bool eeh_state_active(int state) |
245 | { | |
246 | return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) | |
247 | == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); | |
248 | } | |
249 | ||
d6c4932f SB |
250 | typedef void *(*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag); |
251 | typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag); | |
bb593c00 | 252 | void eeh_set_pe_aux_size(int size); |
cad5cef6 | 253 | int eeh_phb_pe_create(struct pci_controller *phb); |
fef7f905 | 254 | int eeh_wait_state(struct eeh_pe *pe, int max_wait); |
9ff67433 | 255 | struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); |
309ed3a7 | 256 | struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root); |
8bae6a23 AK |
257 | struct eeh_pe *eeh_pe_get(struct pci_controller *phb, |
258 | int pe_no, int config_addr); | |
9b84348c | 259 | int eeh_add_to_parent_pe(struct eeh_dev *edev); |
807a827d | 260 | int eeh_rmv_from_parent_pe(struct eeh_dev *edev); |
5a71978e | 261 | void eeh_pe_update_time_stamp(struct eeh_pe *pe); |
f5c57710 | 262 | void *eeh_pe_traverse(struct eeh_pe *root, |
d6c4932f | 263 | eeh_pe_traverse_func fn, void *flag); |
9e6d2cf6 | 264 | void *eeh_pe_dev_traverse(struct eeh_pe *root, |
d6c4932f | 265 | eeh_edev_traverse_func fn, void *flag); |
9e6d2cf6 | 266 | void eeh_pe_restore_bars(struct eeh_pe *pe); |
357b2f3d | 267 | const char *eeh_pe_loc_get(struct eeh_pe *pe); |
9b3c76f0 | 268 | struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); |
55037d17 | 269 | |
8cc7581c | 270 | struct eeh_dev *eeh_dev_init(struct pci_dn *pdn); |
cad5cef6 | 271 | void eeh_dev_phb_init_dynamic(struct pci_controller *phb); |
b9fde58d | 272 | void eeh_probe_devices(void); |
aa1e6374 GS |
273 | int __init eeh_ops_register(struct eeh_ops *ops); |
274 | int __exit eeh_ops_unregister(const char *name); | |
3e938052 | 275 | int eeh_check_failure(const volatile void __iomem *token); |
f8f7d63f | 276 | int eeh_dev_check_failure(struct eeh_dev *edev); |
eeb6361f | 277 | void eeh_addr_cache_build(void); |
ff57b454 GS |
278 | void eeh_add_device_early(struct pci_dn *); |
279 | void eeh_add_device_tree_early(struct pci_dn *); | |
f2856491 | 280 | void eeh_add_device_late(struct pci_dev *); |
827c1a6c | 281 | void eeh_add_device_tree_late(struct pci_bus *); |
6a040ce7 | 282 | void eeh_add_sysfs_files(struct pci_bus *); |
807a827d | 283 | void eeh_remove_device(struct pci_dev *); |
188fdea6 | 284 | int eeh_unfreeze_pe(struct eeh_pe *pe); |
5cfb20b9 | 285 | int eeh_pe_reset_and_recover(struct eeh_pe *pe); |
212d16cd GS |
286 | int eeh_dev_open(struct pci_dev *pdev); |
287 | void eeh_dev_release(struct pci_dev *pdev); | |
288 | struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); | |
289 | int eeh_pe_set_option(struct eeh_pe *pe, int option); | |
290 | int eeh_pe_get_state(struct eeh_pe *pe); | |
1ef52073 | 291 | int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed); |
212d16cd | 292 | int eeh_pe_configure(struct eeh_pe *pe); |
ec33d36e GS |
293 | int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, |
294 | unsigned long addr, unsigned long mask); | |
64ba3dc7 | 295 | int eeh_restore_vf_config(struct pci_dn *pdn); |
e2a296ee | 296 | |
1da177e4 LT |
297 | /** |
298 | * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. | |
299 | * | |
300 | * If this macro yields TRUE, the caller relays to eeh_check_failure() | |
301 | * which does further tests out of line. | |
302 | */ | |
2ec5a0ad | 303 | #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) |
1da177e4 LT |
304 | |
305 | /* | |
306 | * Reads from a device which has been isolated by EEH will return | |
307 | * all 1s. This macro gives an all-1s value of the given size (in | |
308 | * bytes: 1, 2, or 4) for comparing with the result of a read. | |
309 | */ | |
310 | #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) | |
311 | ||
312 | #else /* !CONFIG_EEH */ | |
eb740b5f | 313 | |
2ec5a0ad GS |
314 | static inline bool eeh_enabled(void) |
315 | { | |
316 | return false; | |
317 | } | |
318 | ||
b9fde58d | 319 | static inline void eeh_probe_devices(void) { } |
51fb5f56 | 320 | |
e8e9b34c | 321 | static inline void *eeh_dev_init(struct pci_dn *pdn, void *data) |
eb740b5f GS |
322 | { |
323 | return NULL; | |
324 | } | |
325 | ||
326 | static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } | |
327 | ||
3e938052 | 328 | static inline int eeh_check_failure(const volatile void __iomem *token) |
1da177e4 | 329 | { |
3e938052 | 330 | return 0; |
1da177e4 LT |
331 | } |
332 | ||
f8f7d63f | 333 | #define eeh_dev_check_failure(x) (0) |
1da177e4 | 334 | |
3ab96a02 | 335 | static inline void eeh_addr_cache_build(void) { } |
1da177e4 | 336 | |
ff57b454 | 337 | static inline void eeh_add_device_early(struct pci_dn *pdn) { } |
f2856491 | 338 | |
ff57b454 | 339 | static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { } |
022930eb | 340 | |
f2856491 GS |
341 | static inline void eeh_add_device_late(struct pci_dev *dev) { } |
342 | ||
827c1a6c JR |
343 | static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } |
344 | ||
6a040ce7 TLSC |
345 | static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } |
346 | ||
807a827d | 347 | static inline void eeh_remove_device(struct pci_dev *dev) { } |
646a8499 | 348 | |
1da177e4 LT |
349 | #define EEH_POSSIBLE_ERROR(val, type) (0) |
350 | #define EEH_IO_ERROR_VALUE(size) (-1UL) | |
351 | #endif /* CONFIG_EEH */ | |
352 | ||
8b8da358 | 353 | #ifdef CONFIG_PPC64 |
172ca926 | 354 | /* |
1da177e4 LT |
355 | * MMIO read/write operations with EEH support. |
356 | */ | |
357 | static inline u8 eeh_readb(const volatile void __iomem *addr) | |
358 | { | |
359 | u8 val = in_8(addr); | |
360 | if (EEH_POSSIBLE_ERROR(val, u8)) | |
3e938052 | 361 | eeh_check_failure(addr); |
1da177e4 LT |
362 | return val; |
363 | } | |
1da177e4 LT |
364 | |
365 | static inline u16 eeh_readw(const volatile void __iomem *addr) | |
366 | { | |
367 | u16 val = in_le16(addr); | |
368 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
3e938052 | 369 | eeh_check_failure(addr); |
1da177e4 LT |
370 | return val; |
371 | } | |
1da177e4 LT |
372 | |
373 | static inline u32 eeh_readl(const volatile void __iomem *addr) | |
374 | { | |
375 | u32 val = in_le32(addr); | |
376 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
3e938052 | 377 | eeh_check_failure(addr); |
1da177e4 LT |
378 | return val; |
379 | } | |
4cb3cee0 BH |
380 | |
381 | static inline u64 eeh_readq(const volatile void __iomem *addr) | |
1da177e4 | 382 | { |
4cb3cee0 BH |
383 | u64 val = in_le64(addr); |
384 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
3e938052 | 385 | eeh_check_failure(addr); |
1da177e4 LT |
386 | return val; |
387 | } | |
1da177e4 | 388 | |
4cb3cee0 | 389 | static inline u16 eeh_readw_be(const volatile void __iomem *addr) |
1da177e4 | 390 | { |
4cb3cee0 BH |
391 | u16 val = in_be16(addr); |
392 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
3e938052 | 393 | eeh_check_failure(addr); |
1da177e4 LT |
394 | return val; |
395 | } | |
4cb3cee0 BH |
396 | |
397 | static inline u32 eeh_readl_be(const volatile void __iomem *addr) | |
1da177e4 | 398 | { |
4cb3cee0 BH |
399 | u32 val = in_be32(addr); |
400 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
3e938052 | 401 | eeh_check_failure(addr); |
4cb3cee0 | 402 | return val; |
1da177e4 | 403 | } |
4cb3cee0 BH |
404 | |
405 | static inline u64 eeh_readq_be(const volatile void __iomem *addr) | |
1da177e4 LT |
406 | { |
407 | u64 val = in_be64(addr); | |
408 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
3e938052 | 409 | eeh_check_failure(addr); |
1da177e4 LT |
410 | return val; |
411 | } | |
1da177e4 | 412 | |
68a64357 BH |
413 | static inline void eeh_memcpy_fromio(void *dest, const |
414 | volatile void __iomem *src, | |
1da177e4 LT |
415 | unsigned long n) |
416 | { | |
68a64357 | 417 | _memcpy_fromio(dest, src, n); |
1da177e4 LT |
418 | |
419 | /* Look for ffff's here at dest[n]. Assume that at least 4 bytes | |
420 | * were copied. Check all four bytes. | |
421 | */ | |
68a64357 | 422 | if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) |
3e938052 | 423 | eeh_check_failure(src); |
1da177e4 LT |
424 | } |
425 | ||
1da177e4 | 426 | /* in-string eeh macros */ |
4cb3cee0 BH |
427 | static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, |
428 | int ns) | |
1da177e4 | 429 | { |
4cb3cee0 | 430 | _insb(addr, buf, ns); |
1da177e4 | 431 | if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) |
3e938052 | 432 | eeh_check_failure(addr); |
1da177e4 LT |
433 | } |
434 | ||
4cb3cee0 BH |
435 | static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, |
436 | int ns) | |
1da177e4 | 437 | { |
4cb3cee0 | 438 | _insw(addr, buf, ns); |
1da177e4 | 439 | if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) |
3e938052 | 440 | eeh_check_failure(addr); |
1da177e4 LT |
441 | } |
442 | ||
4cb3cee0 BH |
443 | static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, |
444 | int nl) | |
1da177e4 | 445 | { |
4cb3cee0 | 446 | _insl(addr, buf, nl); |
1da177e4 | 447 | if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) |
3e938052 | 448 | eeh_check_failure(addr); |
1da177e4 LT |
449 | } |
450 | ||
5ca85ae6 OH |
451 | |
452 | void eeh_cache_debugfs_init(void); | |
453 | ||
8b8da358 | 454 | #endif /* CONFIG_PPC64 */ |
88ced031 | 455 | #endif /* __KERNEL__ */ |
8b8da358 | 456 | #endif /* _POWERPC_EEH_H */ |