]>
Commit | Line | Data |
---|---|---|
172ca926 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. |
cb3bc9d0 | 3 | * Copyright 2001-2012 IBM Corporation. |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
172ca926 | 9 | * |
1da177e4 LT |
10 | * This program is distributed in the hope that it will be useful, |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
172ca926 | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
8b8da358 BH |
20 | #ifndef _POWERPC_EEH_H |
21 | #define _POWERPC_EEH_H | |
88ced031 | 22 | #ifdef __KERNEL__ |
1da177e4 | 23 | |
1da177e4 LT |
24 | #include <linux/init.h> |
25 | #include <linux/list.h> | |
26 | #include <linux/string.h> | |
5a71978e | 27 | #include <linux/time.h> |
1da177e4 LT |
28 | |
29 | struct pci_dev; | |
827c1a6c | 30 | struct pci_bus; |
1da177e4 | 31 | struct device_node; |
1da177e4 LT |
32 | |
33 | #ifdef CONFIG_EEH | |
34 | ||
8a5ad356 GS |
35 | /* EEH subsystem flags */ |
36 | #define EEH_ENABLED 0x1 /* EEH enabled */ | |
37 | #define EEH_FORCE_DISABLED 0x2 /* EEH disabled */ | |
38 | #define EEH_PROBE_MODE_DEV 0x4 /* From PCI device */ | |
39 | #define EEH_PROBE_MODE_DEVTREE 0x8 /* From device tree */ | |
40 | ||
26833a50 GS |
41 | /* |
42 | * Delay for PE reset, all in ms | |
43 | * | |
44 | * PCI specification has reset hold time of 100 milliseconds. | |
45 | * We have 250 milliseconds here. The PCI bus settlement time | |
46 | * is specified as 1.5 seconds and we have 1.8 seconds. | |
47 | */ | |
48 | #define EEH_PE_RST_HOLD_TIME 250 | |
49 | #define EEH_PE_RST_SETTLE_TIME 1800 | |
50 | ||
968f968f GS |
51 | /* |
52 | * The struct is used to trace PE related EEH functionality. | |
53 | * In theory, there will have one instance of the struct to | |
54 | * be created against particular PE. In nature, PEs corelate | |
55 | * to each other. the struct has to reflect that hierarchy in | |
56 | * order to easily pick up those affected PEs when one particular | |
57 | * PE has EEH errors. | |
58 | * | |
59 | * Also, one particular PE might be composed of PCI device, PCI | |
60 | * bus and its subordinate components. The struct also need ship | |
61 | * the information. Further more, one particular PE is only meaingful | |
62 | * in the corresponding PHB. Therefore, the root PEs should be created | |
63 | * against existing PHBs in on-to-one fashion. | |
64 | */ | |
5efc3ad7 GS |
65 | #define EEH_PE_INVALID (1 << 0) /* Invalid */ |
66 | #define EEH_PE_PHB (1 << 1) /* PHB PE */ | |
67 | #define EEH_PE_DEVICE (1 << 2) /* Device PE */ | |
68 | #define EEH_PE_BUS (1 << 3) /* Bus PE */ | |
968f968f GS |
69 | |
70 | #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ | |
71 | #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ | |
d0914f50 | 72 | #define EEH_PE_RESET (1 << 2) /* PE reset in progress */ |
968f968f | 73 | |
807a827d GS |
74 | #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ |
75 | ||
968f968f GS |
76 | struct eeh_pe { |
77 | int type; /* PE type: PHB/Bus/Device */ | |
78 | int state; /* PE EEH dependent mode */ | |
79 | int config_addr; /* Traditional PCI address */ | |
80 | int addr; /* PE configuration address */ | |
81 | struct pci_controller *phb; /* Associated PHB */ | |
8cdb2833 | 82 | struct pci_bus *bus; /* Top PCI bus for bus PE */ |
968f968f GS |
83 | int check_count; /* Times of ignored error */ |
84 | int freeze_count; /* Times of froze up */ | |
5a71978e | 85 | struct timeval tstamp; /* Time on first-time freeze */ |
968f968f GS |
86 | int false_positives; /* Times of reported #ff's */ |
87 | struct eeh_pe *parent; /* Parent PE */ | |
88 | struct list_head child_list; /* Link PE to the child list */ | |
89 | struct list_head edevs; /* Link list of EEH devices */ | |
90 | struct list_head child; /* Child PEs */ | |
91 | }; | |
92 | ||
9feed42e GS |
93 | #define eeh_pe_for_each_dev(pe, edev, tmp) \ |
94 | list_for_each_entry_safe(edev, tmp, &pe->edevs, list) | |
5b663529 | 95 | |
eb740b5f GS |
96 | /* |
97 | * The struct is used to trace EEH state for the associated | |
98 | * PCI device node or PCI device. In future, it might | |
99 | * represent PE as well so that the EEH device to form | |
100 | * another tree except the currently existing tree of PCI | |
101 | * buses and PCI devices | |
102 | */ | |
4b83bd45 GS |
103 | #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ |
104 | #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ | |
105 | #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ | |
106 | #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ | |
107 | #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ | |
eb740b5f | 108 | |
f26c7a03 GS |
109 | #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ |
110 | #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ | |
d2b0f6f7 | 111 | #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ |
ab55d218 | 112 | |
eb740b5f GS |
113 | struct eeh_dev { |
114 | int mode; /* EEH mode */ | |
115 | int class_code; /* Class code of the device */ | |
116 | int config_addr; /* Config address */ | |
117 | int pe_config_addr; /* PE config address */ | |
eb740b5f | 118 | u32 config_space[16]; /* Saved PCI config space */ |
2a18dfc6 GS |
119 | int pcix_cap; /* Saved PCIx capability */ |
120 | int pcie_cap; /* Saved PCIe capability */ | |
121 | int aer_cap; /* Saved AER capability */ | |
968f968f GS |
122 | struct eeh_pe *pe; /* Associated PE */ |
123 | struct list_head list; /* Form link list in the PE */ | |
eb740b5f GS |
124 | struct pci_controller *phb; /* Associated PHB */ |
125 | struct device_node *dn; /* Associated device node */ | |
126 | struct pci_dev *pdev; /* Associated PCI device */ | |
f5c57710 | 127 | struct pci_bus *bus; /* PCI bus for partial hotplug */ |
eb740b5f GS |
128 | }; |
129 | ||
130 | static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) | |
131 | { | |
2d5c1216 | 132 | return edev ? edev->dn : NULL; |
eb740b5f GS |
133 | } |
134 | ||
135 | static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) | |
136 | { | |
2d5c1216 | 137 | return edev ? edev->pdev : NULL; |
eb740b5f GS |
138 | } |
139 | ||
7e4e7867 GS |
140 | /* Return values from eeh_ops::next_error */ |
141 | enum { | |
142 | EEH_NEXT_ERR_NONE = 0, | |
143 | EEH_NEXT_ERR_INF, | |
144 | EEH_NEXT_ERR_FROZEN_PE, | |
145 | EEH_NEXT_ERR_FENCED_PHB, | |
146 | EEH_NEXT_ERR_DEAD_PHB, | |
147 | EEH_NEXT_ERR_DEAD_IOC | |
148 | }; | |
149 | ||
aa1e6374 GS |
150 | /* |
151 | * The struct is used to trace the registered EEH operation | |
152 | * callback functions. Actually, those operation callback | |
153 | * functions are heavily platform dependent. That means the | |
154 | * platform should register its own EEH operation callback | |
155 | * functions before any EEH further operations. | |
156 | */ | |
8fb8f709 GS |
157 | #define EEH_OPT_DISABLE 0 /* EEH disable */ |
158 | #define EEH_OPT_ENABLE 1 /* EEH enable */ | |
159 | #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ | |
160 | #define EEH_OPT_THAW_DMA 3 /* DMA enable */ | |
eb594a47 GS |
161 | #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ |
162 | #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ | |
163 | #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ | |
164 | #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ | |
165 | #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ | |
166 | #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ | |
167 | #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ | |
2652481f GS |
168 | #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ |
169 | #define EEH_RESET_HOT 1 /* Hot reset */ | |
170 | #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ | |
8d633291 GS |
171 | #define EEH_LOG_TEMP 1 /* EEH temporary error log */ |
172 | #define EEH_LOG_PERM 2 /* EEH permanent error log */ | |
eb594a47 | 173 | |
aa1e6374 GS |
174 | struct eeh_ops { |
175 | char *name; | |
176 | int (*init)(void); | |
21fd21f5 | 177 | int (*post_init)(void); |
d7bb8862 | 178 | void* (*of_probe)(struct device_node *dn, void *flag); |
51fb5f56 | 179 | int (*dev_probe)(struct pci_dev *dev, void *flag); |
371a395d GS |
180 | int (*set_option)(struct eeh_pe *pe, int option); |
181 | int (*get_pe_addr)(struct eeh_pe *pe); | |
182 | int (*get_state)(struct eeh_pe *pe, int *state); | |
183 | int (*reset)(struct eeh_pe *pe, int option); | |
184 | int (*wait_state)(struct eeh_pe *pe, int max_wait); | |
185 | int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); | |
186 | int (*configure_bridge)(struct eeh_pe *pe); | |
3780444c GS |
187 | int (*read_config)(struct device_node *dn, int where, int size, u32 *val); |
188 | int (*write_config)(struct device_node *dn, int where, int size, u32 val); | |
8a6b1bc7 | 189 | int (*next_error)(struct eeh_pe **pe); |
1d350544 | 190 | int (*restore_config)(struct device_node *dn); |
aa1e6374 GS |
191 | }; |
192 | ||
8a5ad356 | 193 | extern int eeh_subsystem_flags; |
aa1e6374 | 194 | extern struct eeh_ops *eeh_ops; |
4907581d | 195 | extern raw_spinlock_t confirm_error_lock; |
d7bb8862 | 196 | |
2ec5a0ad GS |
197 | static inline bool eeh_enabled(void) |
198 | { | |
8a5ad356 GS |
199 | if ((eeh_subsystem_flags & EEH_FORCE_DISABLED) || |
200 | !(eeh_subsystem_flags & EEH_ENABLED)) | |
201 | return false; | |
202 | ||
203 | return true; | |
2ec5a0ad GS |
204 | } |
205 | ||
206 | static inline void eeh_set_enable(bool mode) | |
207 | { | |
8a5ad356 GS |
208 | if (mode) |
209 | eeh_subsystem_flags |= EEH_ENABLED; | |
210 | else | |
211 | eeh_subsystem_flags &= ~EEH_ENABLED; | |
2ec5a0ad GS |
212 | } |
213 | ||
d7bb8862 GS |
214 | static inline void eeh_probe_mode_set(int flag) |
215 | { | |
8a5ad356 | 216 | eeh_subsystem_flags |= flag; |
d7bb8862 GS |
217 | } |
218 | ||
219 | static inline int eeh_probe_mode_devtree(void) | |
220 | { | |
8a5ad356 | 221 | return (eeh_subsystem_flags & EEH_PROBE_MODE_DEVTREE); |
d7bb8862 GS |
222 | } |
223 | ||
224 | static inline int eeh_probe_mode_dev(void) | |
225 | { | |
8a5ad356 | 226 | return (eeh_subsystem_flags & EEH_PROBE_MODE_DEV); |
d7bb8862 | 227 | } |
646a8499 | 228 | |
4907581d GS |
229 | static inline void eeh_serialize_lock(unsigned long *flags) |
230 | { | |
231 | raw_spin_lock_irqsave(&confirm_error_lock, *flags); | |
232 | } | |
233 | ||
234 | static inline void eeh_serialize_unlock(unsigned long flags) | |
235 | { | |
236 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); | |
237 | } | |
238 | ||
cb3bc9d0 GS |
239 | /* |
240 | * Max number of EEH freezes allowed before we consider the device | |
241 | * to be permanently disabled. | |
242 | */ | |
172ca926 LV |
243 | #define EEH_MAX_ALLOWED_FREEZES 5 |
244 | ||
22f4ab12 | 245 | typedef void *(*eeh_traverse_func)(void *data, void *flag); |
cad5cef6 | 246 | int eeh_phb_pe_create(struct pci_controller *phb); |
9ff67433 | 247 | struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); |
01566808 | 248 | struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); |
9b84348c | 249 | int eeh_add_to_parent_pe(struct eeh_dev *edev); |
807a827d | 250 | int eeh_rmv_from_parent_pe(struct eeh_dev *edev); |
5a71978e | 251 | void eeh_pe_update_time_stamp(struct eeh_pe *pe); |
f5c57710 GS |
252 | void *eeh_pe_traverse(struct eeh_pe *root, |
253 | eeh_traverse_func fn, void *flag); | |
9e6d2cf6 GS |
254 | void *eeh_pe_dev_traverse(struct eeh_pe *root, |
255 | eeh_traverse_func fn, void *flag); | |
256 | void eeh_pe_restore_bars(struct eeh_pe *pe); | |
357b2f3d | 257 | const char *eeh_pe_loc_get(struct eeh_pe *pe); |
9b3c76f0 | 258 | struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); |
55037d17 | 259 | |
cad5cef6 GKH |
260 | void *eeh_dev_init(struct device_node *dn, void *data); |
261 | void eeh_dev_phb_init_dynamic(struct pci_controller *phb); | |
eeb6361f | 262 | int eeh_init(void); |
aa1e6374 GS |
263 | int __init eeh_ops_register(struct eeh_ops *ops); |
264 | int __exit eeh_ops_unregister(const char *name); | |
1da177e4 LT |
265 | unsigned long eeh_check_failure(const volatile void __iomem *token, |
266 | unsigned long val); | |
f8f7d63f | 267 | int eeh_dev_check_failure(struct eeh_dev *edev); |
eeb6361f | 268 | void eeh_addr_cache_build(void); |
f2856491 | 269 | void eeh_add_device_early(struct device_node *); |
e2a296ee | 270 | void eeh_add_device_tree_early(struct device_node *); |
f2856491 | 271 | void eeh_add_device_late(struct pci_dev *); |
827c1a6c | 272 | void eeh_add_device_tree_late(struct pci_bus *); |
6a040ce7 | 273 | void eeh_add_sysfs_files(struct pci_bus *); |
807a827d | 274 | void eeh_remove_device(struct pci_dev *); |
e2a296ee | 275 | |
1da177e4 LT |
276 | /** |
277 | * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. | |
278 | * | |
279 | * If this macro yields TRUE, the caller relays to eeh_check_failure() | |
280 | * which does further tests out of line. | |
281 | */ | |
2ec5a0ad | 282 | #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) |
1da177e4 LT |
283 | |
284 | /* | |
285 | * Reads from a device which has been isolated by EEH will return | |
286 | * all 1s. This macro gives an all-1s value of the given size (in | |
287 | * bytes: 1, 2, or 4) for comparing with the result of a read. | |
288 | */ | |
289 | #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) | |
290 | ||
291 | #else /* !CONFIG_EEH */ | |
eb740b5f | 292 | |
2ec5a0ad GS |
293 | static inline bool eeh_enabled(void) |
294 | { | |
295 | return false; | |
296 | } | |
297 | ||
298 | static inline void eeh_set_enable(bool mode) { } | |
299 | ||
51fb5f56 GS |
300 | static inline int eeh_init(void) |
301 | { | |
302 | return 0; | |
303 | } | |
304 | ||
eb740b5f GS |
305 | static inline void *eeh_dev_init(struct device_node *dn, void *data) |
306 | { | |
307 | return NULL; | |
308 | } | |
309 | ||
310 | static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } | |
311 | ||
1da177e4 LT |
312 | static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) |
313 | { | |
314 | return val; | |
315 | } | |
316 | ||
f8f7d63f | 317 | #define eeh_dev_check_failure(x) (0) |
1da177e4 | 318 | |
3ab96a02 | 319 | static inline void eeh_addr_cache_build(void) { } |
1da177e4 | 320 | |
f2856491 GS |
321 | static inline void eeh_add_device_early(struct device_node *dn) { } |
322 | ||
022930eb HM |
323 | static inline void eeh_add_device_tree_early(struct device_node *dn) { } |
324 | ||
f2856491 GS |
325 | static inline void eeh_add_device_late(struct pci_dev *dev) { } |
326 | ||
827c1a6c JR |
327 | static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } |
328 | ||
6a040ce7 TLSC |
329 | static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } |
330 | ||
807a827d | 331 | static inline void eeh_remove_device(struct pci_dev *dev) { } |
646a8499 | 332 | |
1da177e4 LT |
333 | #define EEH_POSSIBLE_ERROR(val, type) (0) |
334 | #define EEH_IO_ERROR_VALUE(size) (-1UL) | |
335 | #endif /* CONFIG_EEH */ | |
336 | ||
8b8da358 | 337 | #ifdef CONFIG_PPC64 |
172ca926 | 338 | /* |
1da177e4 LT |
339 | * MMIO read/write operations with EEH support. |
340 | */ | |
341 | static inline u8 eeh_readb(const volatile void __iomem *addr) | |
342 | { | |
343 | u8 val = in_8(addr); | |
344 | if (EEH_POSSIBLE_ERROR(val, u8)) | |
345 | return eeh_check_failure(addr, val); | |
346 | return val; | |
347 | } | |
1da177e4 LT |
348 | |
349 | static inline u16 eeh_readw(const volatile void __iomem *addr) | |
350 | { | |
351 | u16 val = in_le16(addr); | |
352 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
353 | return eeh_check_failure(addr, val); | |
354 | return val; | |
355 | } | |
1da177e4 LT |
356 | |
357 | static inline u32 eeh_readl(const volatile void __iomem *addr) | |
358 | { | |
359 | u32 val = in_le32(addr); | |
360 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
361 | return eeh_check_failure(addr, val); | |
362 | return val; | |
363 | } | |
4cb3cee0 BH |
364 | |
365 | static inline u64 eeh_readq(const volatile void __iomem *addr) | |
1da177e4 | 366 | { |
4cb3cee0 BH |
367 | u64 val = in_le64(addr); |
368 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
1da177e4 LT |
369 | return eeh_check_failure(addr, val); |
370 | return val; | |
371 | } | |
1da177e4 | 372 | |
4cb3cee0 | 373 | static inline u16 eeh_readw_be(const volatile void __iomem *addr) |
1da177e4 | 374 | { |
4cb3cee0 BH |
375 | u16 val = in_be16(addr); |
376 | if (EEH_POSSIBLE_ERROR(val, u16)) | |
1da177e4 LT |
377 | return eeh_check_failure(addr, val); |
378 | return val; | |
379 | } | |
4cb3cee0 BH |
380 | |
381 | static inline u32 eeh_readl_be(const volatile void __iomem *addr) | |
1da177e4 | 382 | { |
4cb3cee0 BH |
383 | u32 val = in_be32(addr); |
384 | if (EEH_POSSIBLE_ERROR(val, u32)) | |
385 | return eeh_check_failure(addr, val); | |
386 | return val; | |
1da177e4 | 387 | } |
4cb3cee0 BH |
388 | |
389 | static inline u64 eeh_readq_be(const volatile void __iomem *addr) | |
1da177e4 LT |
390 | { |
391 | u64 val = in_be64(addr); | |
392 | if (EEH_POSSIBLE_ERROR(val, u64)) | |
393 | return eeh_check_failure(addr, val); | |
394 | return val; | |
395 | } | |
1da177e4 | 396 | |
68a64357 BH |
397 | static inline void eeh_memcpy_fromio(void *dest, const |
398 | volatile void __iomem *src, | |
1da177e4 LT |
399 | unsigned long n) |
400 | { | |
68a64357 | 401 | _memcpy_fromio(dest, src, n); |
1da177e4 LT |
402 | |
403 | /* Look for ffff's here at dest[n]. Assume that at least 4 bytes | |
404 | * were copied. Check all four bytes. | |
405 | */ | |
68a64357 BH |
406 | if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) |
407 | eeh_check_failure(src, *((u32 *)(dest + n - 4))); | |
1da177e4 LT |
408 | } |
409 | ||
1da177e4 | 410 | /* in-string eeh macros */ |
4cb3cee0 BH |
411 | static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, |
412 | int ns) | |
1da177e4 | 413 | { |
4cb3cee0 | 414 | _insb(addr, buf, ns); |
1da177e4 | 415 | if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) |
4cb3cee0 | 416 | eeh_check_failure(addr, *(u8*)buf); |
1da177e4 LT |
417 | } |
418 | ||
4cb3cee0 BH |
419 | static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, |
420 | int ns) | |
1da177e4 | 421 | { |
4cb3cee0 | 422 | _insw(addr, buf, ns); |
1da177e4 | 423 | if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) |
4cb3cee0 | 424 | eeh_check_failure(addr, *(u16*)buf); |
1da177e4 LT |
425 | } |
426 | ||
4cb3cee0 BH |
427 | static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, |
428 | int nl) | |
1da177e4 | 429 | { |
4cb3cee0 | 430 | _insl(addr, buf, nl); |
1da177e4 | 431 | if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) |
4cb3cee0 | 432 | eeh_check_failure(addr, *(u32*)buf); |
1da177e4 LT |
433 | } |
434 | ||
8b8da358 | 435 | #endif /* CONFIG_PPC64 */ |
88ced031 | 436 | #endif /* __KERNEL__ */ |
8b8da358 | 437 | #endif /* _POWERPC_EEH_H */ |