[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / include / asm / eeh.h

/*
 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
 * Copyright 2001-2012 IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef _POWERPC_EEH_H
#define _POWERPC_EEH_H
#ifdef __KERNEL__

#include <linux/init.h>
#include <linux/list.h>
#include <linux/string.h>

struct pci_dev;
struct pci_bus;
struct device_node;

#ifdef CONFIG_EEH

/*
 * The struct is used to trace PE related EEH functionality.
 * In theory, there will have one instance of the struct to
 * be created against particular PE. In nature, PEs corelate
 * to each other. the struct has to reflect that hierarchy in
 * order to easily pick up those affected PEs when one particular
 * PE has EEH errors.
 *
 * Also, one particular PE might be composed of PCI device, PCI
 * bus and its subordinate components. The struct also need ship
 * the information. Further more, one particular PE is only meaingful
 * in the corresponding PHB. Therefore, the root PEs should be created
 * against existing PHBs in on-to-one fashion.
 */
#define EEH_PE_PHB	1	/* PHB PE    */
#define EEH_PE_DEVICE 	2	/* Device PE */
#define EEH_PE_BUS	3	/* Bus PE    */

#define EEH_PE_ISOLATED		(1 << 0)	/* Isolated PE		*/
#define EEH_PE_RECOVERING	(1 << 1)	/* Recovering PE	*/

struct eeh_pe {
	int type;			/* PE type: PHB/Bus/Device	*/
	int state;			/* PE EEH dependent mode	*/
	int config_addr;		/* Traditional PCI address	*/
	int addr;			/* PE configuration address	*/
	struct pci_controller *phb;	/* Associated PHB		*/
	int check_count;		/* Times of ignored error	*/
	int freeze_count;		/* Times of froze up		*/
	int false_positives;		/* Times of reported #ff's	*/
	struct eeh_pe *parent;		/* Parent PE			*/
	struct list_head child_list;	/* Link PE to the child list	*/
	struct list_head edevs;		/* Link list of EEH devices	*/
	struct list_head child;		/* Child PEs			*/
};

/*
 * The struct is used to trace EEH state for the associated
 * PCI device node or PCI device. In future, it might
 * represent PE as well so that the EEH device to form
 * another tree except the currently existing tree of PCI
 * buses and PCI devices
 */
#define EEH_MODE_SUPPORTED	(1<<0)	/* EEH supported on the device	*/
#define EEH_MODE_NOCHECK	(1<<1)	/* EEH check should be skipped	*/
#define EEH_MODE_ISOLATED	(1<<2)	/* The device has been isolated	*/
#define EEH_MODE_RECOVERING	(1<<3)	/* Recovering the device	*/
#define EEH_MODE_IRQ_DISABLED	(1<<4)	/* Interrupt disabled		*/

struct eeh_dev {
	int mode;			/* EEH mode			*/
	int class_code;			/* Class code of the device	*/
	int config_addr;		/* Config address		*/
	int pe_config_addr;		/* PE config address		*/
	int check_count;		/* Times of ignored error	*/
	int freeze_count;		/* Times of froze up		*/
	int false_positives;		/* Times of reported #ff's	*/
	u32 config_space[16];		/* Saved PCI config space	*/
	struct eeh_pe *pe;		/* Associated PE		*/
	struct list_head list;		/* Form link list in the PE	*/
	struct pci_controller *phb;	/* Associated PHB		*/
	struct device_node *dn;		/* Associated device node	*/
	struct pci_dev *pdev;		/* Associated PCI device	*/
};

static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
{
	return edev->dn;
}

static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
{
	return edev->pdev;
}

/*
 * The struct is used to trace the registered EEH operation
 * callback functions. Actually, those operation callback
 * functions are heavily platform dependent. That means the
 * platform should register its own EEH operation callback
 * functions before any EEH further operations.
 */
#define EEH_OPT_DISABLE		0	/* EEH disable	*/
#define EEH_OPT_ENABLE		1	/* EEH enable	*/
#define EEH_OPT_THAW_MMIO	2	/* MMIO enable	*/
#define EEH_OPT_THAW_DMA	3	/* DMA enable	*/
#define EEH_STATE_UNAVAILABLE	(1 << 0)	/* State unavailable	*/
#define EEH_STATE_NOT_SUPPORT	(1 << 1)	/* EEH not supported	*/
#define EEH_STATE_RESET_ACTIVE	(1 << 2)	/* Active reset		*/
#define EEH_STATE_MMIO_ACTIVE	(1 << 3)	/* Active MMIO		*/
#define EEH_STATE_DMA_ACTIVE	(1 << 4)	/* Active DMA		*/
#define EEH_STATE_MMIO_ENABLED	(1 << 5)	/* MMIO enabled		*/
#define EEH_STATE_DMA_ENABLED	(1 << 6)	/* DMA enabled		*/
#define EEH_RESET_DEACTIVATE	0	/* Deactivate the PE reset	*/
#define EEH_RESET_HOT		1	/* Hot reset			*/
#define EEH_RESET_FUNDAMENTAL	3	/* Fundamental reset		*/
#define EEH_LOG_TEMP		1	/* EEH temporary error log	*/
#define EEH_LOG_PERM		2	/* EEH permanent error log	*/

struct eeh_ops {
	char *name;
	int (*init)(void);
	int (*set_option)(struct device_node *dn, int option);
	int (*get_pe_addr)(struct device_node *dn);
	int (*get_state)(struct device_node *dn, int *state);
	int (*reset)(struct device_node *dn, int option);
	int (*wait_state)(struct device_node *dn, int max_wait);
	int (*get_log)(struct device_node *dn, int severity, char *drv_log, unsigned long len);
	int (*configure_bridge)(struct device_node *dn);
	int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
	int (*write_config)(struct device_node *dn, int where, int size, u32 val);
};

extern struct eeh_ops *eeh_ops;
extern int eeh_subsystem_enabled;
extern struct mutex eeh_mutex;

static inline void eeh_lock(void)
{
	mutex_lock(&eeh_mutex);
}

static inline void eeh_unlock(void)
{
	mutex_unlock(&eeh_mutex);
}

/*
 * Max number of EEH freezes allowed before we consider the device
 * to be permanently disabled.
 */
#define EEH_MAX_ALLOWED_FREEZES 5

int __devinit eeh_phb_pe_create(struct pci_controller *phb);

void * __devinit eeh_dev_init(struct device_node *dn, void *data);
void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
int __init eeh_ops_register(struct eeh_ops *ops);
int __exit eeh_ops_unregister(const char *name);
unsigned long eeh_check_failure(const volatile void __iomem *token,
				unsigned long val);
int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
void __init pci_addr_cache_build(void);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_tree_late(struct pci_bus *);
void eeh_remove_bus_device(struct pci_dev *);

/**
 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 *
 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 * which does further tests out of line.
 */
#define EEH_POSSIBLE_ERROR(val, type)	((val) == (type)~0 && eeh_subsystem_enabled)

/*
 * Reads from a device which has been isolated by EEH will return
 * all 1s.  This macro gives an all-1s value of the given size (in
 * bytes: 1, 2, or 4) for comparing with the result of a read.
 */
#define EEH_IO_ERROR_VALUE(size)	(~0U >> ((4 - (size)) * 8))

#else /* !CONFIG_EEH */

static inline void *eeh_dev_init(struct device_node *dn, void *data)
{
	return NULL;
}

static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }

static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
{
	return val;
}

static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
{
	return 0;
}

static inline void pci_addr_cache_build(void) { }

static inline void eeh_add_device_tree_early(struct device_node *dn) { }

static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }

static inline void eeh_remove_bus_device(struct pci_dev *dev) { }

static inline void eeh_lock(void) { }
static inline void eeh_unlock(void) { }

#define EEH_POSSIBLE_ERROR(val, type) (0)
#define EEH_IO_ERROR_VALUE(size) (-1UL)
#endif /* CONFIG_EEH */

#ifdef CONFIG_PPC64
/*
 * MMIO read/write operations with EEH support.
 */
static inline u8 eeh_readb(const volatile void __iomem *addr)
{
	u8 val = in_8(addr);
	if (EEH_POSSIBLE_ERROR(val, u8))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u16 eeh_readw(const volatile void __iomem *addr)
{
	u16 val = in_le16(addr);
	if (EEH_POSSIBLE_ERROR(val, u16))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u32 eeh_readl(const volatile void __iomem *addr)
{
	u32 val = in_le32(addr);
	if (EEH_POSSIBLE_ERROR(val, u32))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u64 eeh_readq(const volatile void __iomem *addr)
{
	u64 val = in_le64(addr);
	if (EEH_POSSIBLE_ERROR(val, u64))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u16 eeh_readw_be(const volatile void __iomem *addr)
{
	u16 val = in_be16(addr);
	if (EEH_POSSIBLE_ERROR(val, u16))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u32 eeh_readl_be(const volatile void __iomem *addr)
{
	u32 val = in_be32(addr);
	if (EEH_POSSIBLE_ERROR(val, u32))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u64 eeh_readq_be(const volatile void __iomem *addr)
{
	u64 val = in_be64(addr);
	if (EEH_POSSIBLE_ERROR(val, u64))
		return eeh_check_failure(addr, val);
	return val;
}

static inline void eeh_memcpy_fromio(void *dest, const
				     volatile void __iomem *src,
				     unsigned long n)
{
	_memcpy_fromio(dest, src, n);

	/* Look for ffff's here at dest[n].  Assume that at least 4 bytes
	 * were copied. Check all four bytes.
	 */
	if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
		eeh_check_failure(src, *((u32 *)(dest + n - 4)));
}

/* in-string eeh macros */
static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
			      int ns)
{
	_insb(addr, buf, ns);
	if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
		eeh_check_failure(addr, *(u8*)buf);
}

static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
			      int ns)
{
	_insw(addr, buf, ns);
	if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
		eeh_check_failure(addr, *(u16*)buf);
}

static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
			      int nl)
{
	_insl(addr, buf, nl);
	if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
		eeh_check_failure(addr, *(u32*)buf);
}

#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _POWERPC_EEH_H */
Commit	Line	Data
172ca926	1	/*
1da177e4	2	* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
cb3bc9d0	3	* Copyright 2001-2012 IBM Corporation.
1da177e4 LT	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
172ca926	9	*
1da177e4 LT	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
172ca926	14	*
1da177e4 LT	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
8b8da358 BH	20	#ifndef _POWERPC_EEH_H
8b8da358 BH	21	#define _POWERPC_EEH_H
88ced031	22	#ifdef __KERNEL__
1da177e4	23
1da177e4 LT	24	#include <linux/init.h>
	25	#include <linux/list.h>
	26	#include <linux/string.h>
	27
	28	struct pci_dev;
827c1a6c	29	struct pci_bus;
1da177e4	30	struct device_node;
1da177e4 LT	31
	32	#ifdef CONFIG_EEH
	33
968f968f GS	34	/*
	35	* The struct is used to trace PE related EEH functionality.
	36	* In theory, there will have one instance of the struct to
	37	* be created against particular PE. In nature, PEs corelate
	38	* to each other. the struct has to reflect that hierarchy in
	39	* order to easily pick up those affected PEs when one particular
	40	* PE has EEH errors.
	41	*
	42	* Also, one particular PE might be composed of PCI device, PCI
	43	* bus and its subordinate components. The struct also need ship
	44	* the information. Further more, one particular PE is only meaingful
	45	* in the corresponding PHB. Therefore, the root PEs should be created
	46	* against existing PHBs in on-to-one fashion.
	47	*/
	48	#define EEH_PE_PHB 1 /* PHB PE */
	49	#define EEH_PE_DEVICE 2 /* Device PE */
	50	#define EEH_PE_BUS 3 /* Bus PE */
	51
	52	#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
	53	#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
	54
	55	struct eeh_pe {
	56	int type; /* PE type: PHB/Bus/Device */
	57	int state; /* PE EEH dependent mode */
	58	int config_addr; /* Traditional PCI address */
	59	int addr; /* PE configuration address */
	60	struct pci_controller phb; / Associated PHB */
	61	int check_count; /* Times of ignored error */
	62	int freeze_count; /* Times of froze up */
	63	int false_positives; /* Times of reported #ff's */
	64	struct eeh_pe parent; / Parent PE */
	65	struct list_head child_list; /* Link PE to the child list */
	66	struct list_head edevs; /* Link list of EEH devices */
	67	struct list_head child; /* Child PEs */
	68	};
	69
eb740b5f GS	70	/*
	71	* The struct is used to trace EEH state for the associated
	72	* PCI device node or PCI device. In future, it might
	73	* represent PE as well so that the EEH device to form
	74	* another tree except the currently existing tree of PCI
	75	* buses and PCI devices
	76	*/
	77	#define EEH_MODE_SUPPORTED (1<<0) /* EEH supported on the device */
	78	#define EEH_MODE_NOCHECK (1<<1) /* EEH check should be skipped */
	79	#define EEH_MODE_ISOLATED (1<<2) /* The device has been isolated */
	80	#define EEH_MODE_RECOVERING (1<<3) /* Recovering the device */
	81	#define EEH_MODE_IRQ_DISABLED (1<<4) /* Interrupt disabled */
	82
	83	struct eeh_dev {
	84	int mode; /* EEH mode */
	85	int class_code; /* Class code of the device */
	86	int config_addr; /* Config address */
	87	int pe_config_addr; /* PE config address */
	88	int check_count; /* Times of ignored error */
	89	int freeze_count; /* Times of froze up */
	90	int false_positives; /* Times of reported #ff's */
	91	u32 config_space[16]; /* Saved PCI config space */
968f968f GS	92	struct eeh_pe pe; / Associated PE */
968f968f GS	93	struct list_head list; /* Form link list in the PE */
eb740b5f GS	94	struct pci_controller phb; / Associated PHB */
	95	struct device_node dn; / Associated device node */
	96	struct pci_dev pdev; / Associated PCI device */
	97	};
	98
	99	static inline struct device_node eeh_dev_to_of_node(struct eeh_dev edev)
	100	{
	101	return edev->dn;
	102	}
	103
	104	static inline struct pci_dev eeh_dev_to_pci_dev(struct eeh_dev edev)
	105	{
	106	return edev->pdev;
	107	}
	108
aa1e6374 GS	109	/*
	110	* The struct is used to trace the registered EEH operation
	111	* callback functions. Actually, those operation callback
	112	* functions are heavily platform dependent. That means the
	113	* platform should register its own EEH operation callback
	114	* functions before any EEH further operations.
	115	*/
8fb8f709 GS	116	#define EEH_OPT_DISABLE 0 /* EEH disable */
	117	#define EEH_OPT_ENABLE 1 /* EEH enable */
	118	#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
	119	#define EEH_OPT_THAW_DMA 3 /* DMA enable */
eb594a47 GS	120	#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
	121	#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
	122	#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
	123	#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
	124	#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
	125	#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
	126	#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
2652481f GS	127	#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
	128	#define EEH_RESET_HOT 1 /* Hot reset */
	129	#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
8d633291 GS	130	#define EEH_LOG_TEMP 1 /* EEH temporary error log */
8d633291 GS	131	#define EEH_LOG_PERM 2 /* EEH permanent error log */
eb594a47	132
aa1e6374 GS	133	struct eeh_ops {
	134	char *name;
	135	int (*init)(void);
	136	int (set_option)(struct device_node dn, int option);
	137	int (get_pe_addr)(struct device_node dn);
	138	int (get_state)(struct device_node dn, int *state);
	139	int (reset)(struct device_node dn, int option);
	140	int (wait_state)(struct device_node dn, int max_wait);
	141	int (get_log)(struct device_node dn, int severity, char *drv_log, unsigned long len);
	142	int (configure_bridge)(struct device_node dn);
3780444c GS	143	int (read_config)(struct device_node dn, int where, int size, u32 *val);
3780444c GS	144	int (write_config)(struct device_node dn, int where, int size, u32 val);
aa1e6374 GS	145	};
	146
	147	extern struct eeh_ops *eeh_ops;
1e28a7dd	148	extern int eeh_subsystem_enabled;
646a8499 GS	149	extern struct mutex eeh_mutex;
	150
	151	static inline void eeh_lock(void)
	152	{
	153	mutex_lock(&eeh_mutex);
	154	}
	155
	156	static inline void eeh_unlock(void)
	157	{
	158	mutex_unlock(&eeh_mutex);
	159	}
1e28a7dd	160
cb3bc9d0 GS	161	/*
	162	* Max number of EEH freezes allowed before we consider the device
	163	* to be permanently disabled.
	164	*/
172ca926 LV	165	#define EEH_MAX_ALLOWED_FREEZES 5
172ca926 LV	166
55037d17 GS	167	int __devinit eeh_phb_pe_create(struct pci_controller *phb);
55037d17 GS	168
eb740b5f GS	169	void * __devinit eeh_dev_init(struct device_node dn, void data);
eb740b5f GS	170	void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
aa1e6374 GS	171	int __init eeh_ops_register(struct eeh_ops *ops);
aa1e6374 GS	172	int __exit eeh_ops_unregister(const char *name);
1da177e4 LT	173	unsigned long eeh_check_failure(const volatile void __iomem *token,
	174	unsigned long val);
	175	int eeh_dn_check_failure(struct device_node dn, struct pci_dev dev);
	176	void __init pci_addr_cache_build(void);
e2a296ee	177	void eeh_add_device_tree_early(struct device_node *);
827c1a6c	178	void eeh_add_device_tree_late(struct pci_bus *);
e2a296ee LV	179	void eeh_remove_bus_device(struct pci_dev *);
e2a296ee LV	180
1da177e4 LT	181	/**
	182	* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
	183	*
	184	* If this macro yields TRUE, the caller relays to eeh_check_failure()
	185	* which does further tests out of line.
	186	*/
1e28a7dd	187	#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
1da177e4 LT	188
	189	/*
	190	* Reads from a device which has been isolated by EEH will return
	191	* all 1s. This macro gives an all-1s value of the given size (in
	192	* bytes: 1, 2, or 4) for comparing with the result of a read.
	193	*/
	194	#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
	195
	196	#else /* !CONFIG_EEH */
eb740b5f GS	197
	198	static inline void eeh_dev_init(struct device_node dn, void *data)
	199	{
	200	return NULL;
	201	}
	202
	203	static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
	204
1da177e4 LT	205	static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
	206	{
	207	return val;
	208	}
	209
	210	static inline int eeh_dn_check_failure(struct device_node dn, struct pci_dev dev)
	211	{
	212	return 0;
	213	}
	214
	215	static inline void pci_addr_cache_build(void) { }
	216
022930eb HM	217	static inline void eeh_add_device_tree_early(struct device_node *dn) { }
022930eb HM	218
827c1a6c JR	219	static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
827c1a6c JR	220
022930eb	221	static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
646a8499 GS	222
	223	static inline void eeh_lock(void) { }
	224	static inline void eeh_unlock(void) { }
	225
1da177e4 LT	226	#define EEH_POSSIBLE_ERROR(val, type) (0)
	227	#define EEH_IO_ERROR_VALUE(size) (-1UL)
	228	#endif /* CONFIG_EEH */
	229
8b8da358	230	#ifdef CONFIG_PPC64
172ca926	231	/*
1da177e4 LT	232	* MMIO read/write operations with EEH support.
	233	*/
	234	static inline u8 eeh_readb(const volatile void __iomem *addr)
	235	{
	236	u8 val = in_8(addr);
	237	if (EEH_POSSIBLE_ERROR(val, u8))
	238	return eeh_check_failure(addr, val);
	239	return val;
	240	}
1da177e4 LT	241
	242	static inline u16 eeh_readw(const volatile void __iomem *addr)
	243	{
	244	u16 val = in_le16(addr);
	245	if (EEH_POSSIBLE_ERROR(val, u16))
	246	return eeh_check_failure(addr, val);
	247	return val;
	248	}
1da177e4 LT	249
	250	static inline u32 eeh_readl(const volatile void __iomem *addr)
	251	{
	252	u32 val = in_le32(addr);
	253	if (EEH_POSSIBLE_ERROR(val, u32))
	254	return eeh_check_failure(addr, val);
	255	return val;
	256	}
4cb3cee0 BH	257
4cb3cee0 BH	258	static inline u64 eeh_readq(const volatile void __iomem *addr)
1da177e4	259	{
4cb3cee0 BH	260	u64 val = in_le64(addr);
4cb3cee0 BH	261	if (EEH_POSSIBLE_ERROR(val, u64))
1da177e4 LT	262	return eeh_check_failure(addr, val);
	263	return val;
	264	}
1da177e4	265
4cb3cee0	266	static inline u16 eeh_readw_be(const volatile void __iomem *addr)
1da177e4	267	{
4cb3cee0 BH	268	u16 val = in_be16(addr);
4cb3cee0 BH	269	if (EEH_POSSIBLE_ERROR(val, u16))
1da177e4 LT	270	return eeh_check_failure(addr, val);
	271	return val;
	272	}
4cb3cee0 BH	273
4cb3cee0 BH	274	static inline u32 eeh_readl_be(const volatile void __iomem *addr)
1da177e4	275	{
4cb3cee0 BH	276	u32 val = in_be32(addr);
	277	if (EEH_POSSIBLE_ERROR(val, u32))
	278	return eeh_check_failure(addr, val);
	279	return val;
1da177e4	280	}
4cb3cee0 BH	281
4cb3cee0 BH	282	static inline u64 eeh_readq_be(const volatile void __iomem *addr)
1da177e4 LT	283	{
	284	u64 val = in_be64(addr);
	285	if (EEH_POSSIBLE_ERROR(val, u64))
	286	return eeh_check_failure(addr, val);
	287	return val;
	288	}
1da177e4	289
68a64357 BH	290	static inline void eeh_memcpy_fromio(void *dest, const
68a64357 BH	291	volatile void __iomem *src,
1da177e4 LT	292	unsigned long n)
1da177e4 LT	293	{
68a64357	294	_memcpy_fromio(dest, src, n);
1da177e4 LT	295
	296	/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
	297	* were copied. Check all four bytes.
	298	*/
68a64357 BH	299	if (n >= 4 && EEH_POSSIBLE_ERROR(((u32 )(dest + n - 4)), u32))
68a64357 BH	300	eeh_check_failure(src, ((u32 )(dest + n - 4)));
1da177e4 LT	301	}
1da177e4 LT	302
1da177e4	303	/* in-string eeh macros */
4cb3cee0 BH	304	static inline void eeh_readsb(const volatile void __iomem addr, void buf,
4cb3cee0 BH	305	int ns)
1da177e4	306	{
4cb3cee0	307	_insb(addr, buf, ns);
1da177e4	308	if (EEH_POSSIBLE_ERROR(((((u8)buf)+ns-1)), u8))
4cb3cee0	309	eeh_check_failure(addr, (u8)buf);
1da177e4 LT	310	}
1da177e4 LT	311
4cb3cee0 BH	312	static inline void eeh_readsw(const volatile void __iomem addr, void buf,
4cb3cee0 BH	313	int ns)
1da177e4	314	{
4cb3cee0	315	_insw(addr, buf, ns);
1da177e4	316	if (EEH_POSSIBLE_ERROR(((((u16)buf)+ns-1)), u16))
4cb3cee0	317	eeh_check_failure(addr, (u16)buf);
1da177e4 LT	318	}
1da177e4 LT	319
4cb3cee0 BH	320	static inline void eeh_readsl(const volatile void __iomem addr, void buf,
4cb3cee0 BH	321	int nl)
1da177e4	322	{
4cb3cee0	323	_insl(addr, buf, nl);
1da177e4	324	if (EEH_POSSIBLE_ERROR(((((u32)buf)+nl-1)), u32))
4cb3cee0	325	eeh_check_failure(addr, (u32)buf);
1da177e4 LT	326	}
1da177e4 LT	327
8b8da358	328	#endif /* CONFIG_PPC64 */
88ced031	329	#endif /* __KERNEL__ */
8b8da358	330	#endif /* _POWERPC_EEH_H */