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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
1da177e4 | 4 | */ |
b671ad2b KG |
5 | #ifndef _ASM_POWERPC_HW_IRQ_H |
6 | #define _ASM_POWERPC_HW_IRQ_H | |
7 | ||
1da177e4 | 8 | #ifdef __KERNEL__ |
1da177e4 | 9 | |
1da177e4 | 10 | #include <linux/errno.h> |
d04c56f7 | 11 | #include <linux/compiler.h> |
b671ad2b KG |
12 | #include <asm/ptrace.h> |
13 | #include <asm/processor.h> | |
1da177e4 | 14 | |
7230c564 BH |
15 | #ifdef CONFIG_PPC64 |
16 | ||
17 | /* | |
18 | * PACA flags in paca->irq_happened. | |
19 | * | |
20 | * This bits are set when interrupts occur while soft-disabled | |
21 | * and allow a proper replay. Additionally, PACA_IRQ_HARD_DIS | |
22 | * is set whenever we manually hard disable. | |
23 | */ | |
24 | #define PACA_IRQ_HARD_DIS 0x01 | |
25 | #define PACA_IRQ_DBELL 0x02 | |
26 | #define PACA_IRQ_EE 0x04 | |
27 | #define PACA_IRQ_DEC 0x08 /* Or FIT */ | |
28 | #define PACA_IRQ_EE_EDGE 0x10 /* BookE only */ | |
0869b6fd | 29 | #define PACA_IRQ_HMI 0x20 |
f442d004 | 30 | #define PACA_IRQ_PMI 0x40 |
7230c564 | 31 | |
6cc3f91b NP |
32 | /* |
33 | * Some soft-masked interrupts must be hard masked until they are replayed | |
34 | * (e.g., because the soft-masked handler does not clear the exception). | |
35 | */ | |
36 | #ifdef CONFIG_PPC_BOOK3S | |
37 | #define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE|PACA_IRQ_PMI) | |
38 | #else | |
39 | #define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE) | |
40 | #endif | |
41 | ||
c2e480ba | 42 | /* |
4e26bc4a | 43 | * flags for paca->irq_soft_mask |
c2e480ba | 44 | */ |
01417c6c | 45 | #define IRQS_ENABLED 0 |
f442d004 MS |
46 | #define IRQS_DISABLED 1 /* local_irq_disable() interrupts */ |
47 | #define IRQS_PMI_DISABLED 2 | |
48 | #define IRQS_ALL_DISABLED (IRQS_DISABLED | IRQS_PMI_DISABLED) | |
c2e480ba | 49 | |
7230c564 BH |
50 | #endif /* CONFIG_PPC64 */ |
51 | ||
52 | #ifndef __ASSEMBLY__ | |
53 | ||
6de6638b | 54 | extern void replay_system_reset(void); |
7230c564 BH |
55 | extern void __replay_interrupt(unsigned int vector); |
56 | ||
c7aeffc4 | 57 | extern void timer_interrupt(struct pt_regs *); |
3f984620 | 58 | extern void timer_broadcast_interrupt(void); |
7cc1e8ee | 59 | extern void performance_monitor_exception(struct pt_regs *regs); |
6328e593 BB |
60 | extern void WatchdogException(struct pt_regs *regs); |
61 | extern void unknown_exception(struct pt_regs *regs); | |
1da177e4 | 62 | |
d04c56f7 PM |
63 | #ifdef CONFIG_PPC64 |
64 | #include <asm/paca.h> | |
65 | ||
4e26bc4a | 66 | static inline notrace unsigned long irq_soft_mask_return(void) |
e0b5687b MS |
67 | { |
68 | unsigned long flags; | |
69 | ||
70 | asm volatile( | |
71 | "lbz %0,%1(13)" | |
72 | : "=r" (flags) | |
4e26bc4a | 73 | : "i" (offsetof(struct paca_struct, irq_soft_mask))); |
e0b5687b MS |
74 | |
75 | return flags; | |
76 | } | |
77 | ||
0b63acf4 MS |
78 | /* |
79 | * The "memory" clobber acts as both a compiler barrier | |
80 | * for the critical section and as a clobber because | |
4e26bc4a | 81 | * we changed paca->irq_soft_mask |
0b63acf4 | 82 | */ |
4e26bc4a | 83 | static inline notrace void irq_soft_mask_set(unsigned long mask) |
0b63acf4 | 84 | { |
9aa88188 | 85 | #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG |
01417c6c | 86 | /* |
4e26bc4a MS |
87 | * The irq mask must always include the STD bit if any are set. |
88 | * | |
89 | * and interrupts don't get replayed until the standard | |
90 | * interrupt (local_irq_disable()) is unmasked. | |
91 | * | |
92 | * Other masks must only provide additional masking beyond | |
93 | * the standard, and they are also not replayed until the | |
94 | * standard interrupt becomes unmasked. | |
95 | * | |
96 | * This could be changed, but it will require partial | |
97 | * unmasks to be replayed, among other things. For now, take | |
98 | * the simple approach. | |
01417c6c MS |
99 | */ |
100 | WARN_ON(mask && !(mask & IRQS_DISABLED)); | |
101 | #endif | |
102 | ||
0b63acf4 MS |
103 | asm volatile( |
104 | "stb %0,%1(13)" | |
105 | : | |
4e26bc4a MS |
106 | : "r" (mask), |
107 | "i" (offsetof(struct paca_struct, irq_soft_mask)) | |
0b63acf4 MS |
108 | : "memory"); |
109 | } | |
110 | ||
4e26bc4a | 111 | static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask) |
a67c543a MS |
112 | { |
113 | unsigned long flags; | |
114 | ||
9aa88188 | 115 | #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG |
01417c6c MS |
116 | WARN_ON(mask && !(mask & IRQS_DISABLED)); |
117 | #endif | |
118 | ||
a67c543a MS |
119 | asm volatile( |
120 | "lbz %0,%1(13); stb %2,%1(13)" | |
121 | : "=&r" (flags) | |
4e26bc4a | 122 | : "i" (offsetof(struct paca_struct, irq_soft_mask)), |
01417c6c | 123 | "r" (mask) |
a67c543a MS |
124 | : "memory"); |
125 | ||
126 | return flags; | |
127 | } | |
128 | ||
c6424382 MS |
129 | static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask) |
130 | { | |
131 | unsigned long flags, tmp; | |
132 | ||
133 | asm volatile( | |
134 | "lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)" | |
135 | : "=&r" (flags), "=r" (tmp) | |
136 | : "i" (offsetof(struct paca_struct, irq_soft_mask)), | |
137 | "r" (mask) | |
138 | : "memory"); | |
139 | ||
140 | #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG | |
141 | WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED)); | |
142 | #endif | |
143 | ||
144 | return flags; | |
145 | } | |
146 | ||
df9ee292 | 147 | static inline unsigned long arch_local_save_flags(void) |
d04c56f7 | 148 | { |
4e26bc4a | 149 | return irq_soft_mask_return(); |
d04c56f7 PM |
150 | } |
151 | ||
b5c1bd62 | 152 | static inline void arch_local_irq_disable(void) |
d04c56f7 | 153 | { |
4e26bc4a | 154 | irq_soft_mask_set(IRQS_DISABLED); |
d04c56f7 | 155 | } |
1da177e4 | 156 | |
df9ee292 | 157 | extern void arch_local_irq_restore(unsigned long); |
1da177e4 | 158 | |
df9ee292 DH |
159 | static inline void arch_local_irq_enable(void) |
160 | { | |
c2e480ba | 161 | arch_local_irq_restore(IRQS_ENABLED); |
df9ee292 DH |
162 | } |
163 | ||
164 | static inline unsigned long arch_local_irq_save(void) | |
165 | { | |
4e26bc4a | 166 | return irq_soft_mask_set_return(IRQS_DISABLED); |
df9ee292 DH |
167 | } |
168 | ||
169 | static inline bool arch_irqs_disabled_flags(unsigned long flags) | |
170 | { | |
01417c6c | 171 | return flags & IRQS_DISABLED; |
df9ee292 | 172 | } |
1da177e4 | 173 | |
df9ee292 DH |
174 | static inline bool arch_irqs_disabled(void) |
175 | { | |
176 | return arch_irqs_disabled_flags(arch_local_save_flags()); | |
177 | } | |
1da177e4 | 178 | |
c6424382 MS |
179 | #ifdef CONFIG_PPC_BOOK3S |
180 | /* | |
181 | * To support disabling and enabling of irq with PMI, set of | |
182 | * new powerpc_local_irq_pmu_save() and powerpc_local_irq_restore() | |
183 | * functions are added. These macros are implemented using generic | |
184 | * linux local_irq_* code from include/linux/irqflags.h. | |
185 | */ | |
186 | #define raw_local_irq_pmu_save(flags) \ | |
187 | do { \ | |
188 | typecheck(unsigned long, flags); \ | |
189 | flags = irq_soft_mask_or_return(IRQS_DISABLED | \ | |
190 | IRQS_PMI_DISABLED); \ | |
191 | } while(0) | |
192 | ||
193 | #define raw_local_irq_pmu_restore(flags) \ | |
194 | do { \ | |
195 | typecheck(unsigned long, flags); \ | |
196 | arch_local_irq_restore(flags); \ | |
197 | } while(0) | |
198 | ||
199 | #ifdef CONFIG_TRACE_IRQFLAGS | |
200 | #define powerpc_local_irq_pmu_save(flags) \ | |
201 | do { \ | |
202 | raw_local_irq_pmu_save(flags); \ | |
203 | trace_hardirqs_off(); \ | |
204 | } while(0) | |
205 | #define powerpc_local_irq_pmu_restore(flags) \ | |
206 | do { \ | |
207 | if (raw_irqs_disabled_flags(flags)) { \ | |
208 | raw_local_irq_pmu_restore(flags); \ | |
209 | trace_hardirqs_off(); \ | |
210 | } else { \ | |
211 | trace_hardirqs_on(); \ | |
212 | raw_local_irq_pmu_restore(flags); \ | |
213 | } \ | |
214 | } while(0) | |
215 | #else | |
216 | #define powerpc_local_irq_pmu_save(flags) \ | |
217 | do { \ | |
218 | raw_local_irq_pmu_save(flags); \ | |
219 | } while(0) | |
220 | #define powerpc_local_irq_pmu_restore(flags) \ | |
221 | do { \ | |
222 | raw_local_irq_pmu_restore(flags); \ | |
223 | } while (0) | |
224 | #endif /* CONFIG_TRACE_IRQFLAGS */ | |
225 | ||
226 | #endif /* CONFIG_PPC_BOOK3S */ | |
227 | ||
2d27cfd3 | 228 | #ifdef CONFIG_PPC_BOOK3E |
21b2de34 BH |
229 | #define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory") |
230 | #define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory") | |
2d27cfd3 | 231 | #else |
54071e41 NP |
232 | #define __hard_irq_enable() __mtmsrd(MSR_EE|MSR_RI, 1) |
233 | #define __hard_irq_disable() __mtmsrd(MSR_RI, 1) | |
2d27cfd3 | 234 | #endif |
e1fa2e13 | 235 | |
f442d004 MS |
236 | #define hard_irq_disable() do { \ |
237 | unsigned long flags; \ | |
238 | __hard_irq_disable(); \ | |
239 | flags = irq_soft_mask_set_return(IRQS_ALL_DISABLED); \ | |
240 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; \ | |
7b08729c ME |
241 | if (!arch_irqs_disabled_flags(flags)) { \ |
242 | asm ("stdx %%r1, 0, %1 ;" \ | |
243 | : "=m" (local_paca->saved_r1) \ | |
244 | : "b" (&local_paca->saved_r1)); \ | |
f442d004 | 245 | trace_hardirqs_off(); \ |
7b08729c | 246 | } \ |
5737789c | 247 | } while(0) |
f948501b | 248 | |
0b17ba72 AB |
249 | static inline bool lazy_irq_pending(void) |
250 | { | |
251 | return !!(get_paca()->irq_happened & ~PACA_IRQ_HARD_DIS); | |
252 | } | |
253 | ||
7230c564 BH |
254 | /* |
255 | * This is called by asynchronous interrupts to conditionally | |
9b81c021 NP |
256 | * re-enable hard interrupts after having cleared the source |
257 | * of the interrupt. They are kept disabled if there is a different | |
258 | * soft-masked interrupt pending that requires hard masking. | |
7230c564 BH |
259 | */ |
260 | static inline void may_hard_irq_enable(void) | |
261 | { | |
9b81c021 NP |
262 | if (!(get_paca()->irq_happened & PACA_IRQ_MUST_HARD_MASK)) { |
263 | get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS; | |
7230c564 | 264 | __hard_irq_enable(); |
9b81c021 | 265 | } |
7230c564 | 266 | } |
d04c56f7 | 267 | |
a546498f BH |
268 | static inline bool arch_irq_disabled_regs(struct pt_regs *regs) |
269 | { | |
01417c6c | 270 | return (regs->softe & IRQS_DISABLED); |
a546498f BH |
271 | } |
272 | ||
be2cf20a | 273 | extern bool prep_irq_for_idle(void); |
2201f994 | 274 | extern bool prep_irq_for_idle_irqsoff(void); |
771d4304 | 275 | extern void irq_set_pending_from_srr1(unsigned long srr1); |
2201f994 NP |
276 | |
277 | #define fini_irq_for_idle_irqsoff() trace_hardirqs_off(); | |
be2cf20a | 278 | |
1d607bb3 BH |
279 | extern void force_external_irq_replay(void); |
280 | ||
df9ee292 | 281 | #else /* CONFIG_PPC64 */ |
1da177e4 | 282 | |
b671ad2b | 283 | #define SET_MSR_EE(x) mtmsr(x) |
df9ee292 DH |
284 | |
285 | static inline unsigned long arch_local_save_flags(void) | |
286 | { | |
287 | return mfmsr(); | |
288 | } | |
289 | ||
290 | static inline void arch_local_irq_restore(unsigned long flags) | |
291 | { | |
292 | #if defined(CONFIG_BOOKE) | |
293 | asm volatile("wrtee %0" : : "r" (flags) : "memory"); | |
b671ad2b | 294 | #else |
df9ee292 | 295 | mtmsr(flags); |
b671ad2b | 296 | #endif |
df9ee292 | 297 | } |
1da177e4 | 298 | |
df9ee292 | 299 | static inline unsigned long arch_local_irq_save(void) |
1da177e4 | 300 | { |
df9ee292 | 301 | unsigned long flags = arch_local_save_flags(); |
b671ad2b | 302 | #ifdef CONFIG_BOOKE |
df9ee292 | 303 | asm volatile("wrteei 0" : : : "memory"); |
834e5a69 CL |
304 | #elif defined(CONFIG_PPC_8xx) |
305 | wrtspr(SPRN_EID); | |
b671ad2b | 306 | #else |
df9ee292 | 307 | SET_MSR_EE(flags & ~MSR_EE); |
b671ad2b | 308 | #endif |
df9ee292 | 309 | return flags; |
1da177e4 LT |
310 | } |
311 | ||
df9ee292 | 312 | static inline void arch_local_irq_disable(void) |
1da177e4 | 313 | { |
b671ad2b | 314 | #ifdef CONFIG_BOOKE |
df9ee292 | 315 | asm volatile("wrteei 0" : : : "memory"); |
834e5a69 CL |
316 | #elif defined(CONFIG_PPC_8xx) |
317 | wrtspr(SPRN_EID); | |
b671ad2b | 318 | #else |
df9ee292 | 319 | arch_local_irq_save(); |
b671ad2b | 320 | #endif |
1da177e4 LT |
321 | } |
322 | ||
df9ee292 | 323 | static inline void arch_local_irq_enable(void) |
1da177e4 | 324 | { |
b671ad2b | 325 | #ifdef CONFIG_BOOKE |
df9ee292 | 326 | asm volatile("wrteei 1" : : : "memory"); |
834e5a69 CL |
327 | #elif defined(CONFIG_PPC_8xx) |
328 | wrtspr(SPRN_EIE); | |
b671ad2b | 329 | #else |
df9ee292 DH |
330 | unsigned long msr = mfmsr(); |
331 | SET_MSR_EE(msr | MSR_EE); | |
b671ad2b | 332 | #endif |
1da177e4 LT |
333 | } |
334 | ||
df9ee292 | 335 | static inline bool arch_irqs_disabled_flags(unsigned long flags) |
e0eca07b SR |
336 | { |
337 | return (flags & MSR_EE) == 0; | |
338 | } | |
339 | ||
df9ee292 DH |
340 | static inline bool arch_irqs_disabled(void) |
341 | { | |
342 | return arch_irqs_disabled_flags(arch_local_save_flags()); | |
343 | } | |
344 | ||
345 | #define hard_irq_disable() arch_local_irq_disable() | |
346 | ||
a546498f BH |
347 | static inline bool arch_irq_disabled_regs(struct pt_regs *regs) |
348 | { | |
349 | return !(regs->msr & MSR_EE); | |
350 | } | |
351 | ||
7230c564 BH |
352 | static inline void may_hard_irq_enable(void) { } |
353 | ||
d04c56f7 | 354 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 355 | |
089fb442 TG |
356 | #define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST |
357 | ||
c0ad90a3 IM |
358 | /* |
359 | * interrupt-retrigger: should we handle this via lost interrupts and IPIs | |
360 | * or should we not care like we do now ? --BenH. | |
1da177e4 | 361 | */ |
353bca5e | 362 | struct irq_chip; |
b671ad2b | 363 | |
7230c564 | 364 | #endif /* __ASSEMBLY__ */ |
b671ad2b KG |
365 | #endif /* __KERNEL__ */ |
366 | #endif /* _ASM_POWERPC_HW_IRQ_H */ |