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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
edc424f8 DS |
2 | /* |
3 | * ICSWX api | |
4 | * | |
5 | * Copyright (C) 2015 IBM Corp. | |
6 | * | |
edc424f8 DS |
7 | * This provides the Initiate Coprocessor Store Word Indexed (ICSWX) |
8 | * instruction. This instruction is used to communicate with PowerPC | |
9 | * coprocessors. This also provides definitions of the structures used | |
10 | * to communicate with the coprocessor. | |
11 | * | |
12 | * The RFC02130: Coprocessor Architecture document is the reference for | |
13 | * everything in this file unless otherwise noted. | |
14 | */ | |
15 | #ifndef _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ | |
16 | #define _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ | |
17 | ||
18 | #include <asm/ppc-opcode.h> /* for PPC_ICSWX */ | |
19 | ||
20 | /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */ | |
21 | ||
22 | #define CCB_VALUE (0x3fffffffffffffff) | |
23 | #define CCB_ADDRESS (0xfffffffffffffff8) | |
24 | #define CCB_CM (0x0000000000000007) | |
25 | #define CCB_CM0 (0x0000000000000004) | |
26 | #define CCB_CM12 (0x0000000000000003) | |
27 | ||
28 | #define CCB_CM0_ALL_COMPLETIONS (0x0) | |
29 | #define CCB_CM0_LAST_IN_CHAIN (0x4) | |
30 | #define CCB_CM12_STORE (0x0) | |
31 | #define CCB_CM12_INTERRUPT (0x1) | |
32 | ||
33 | #define CCB_SIZE (0x10) | |
34 | #define CCB_ALIGN CCB_SIZE | |
35 | ||
36 | struct coprocessor_completion_block { | |
37 | __be64 value; | |
38 | __be64 address; | |
39 | } __packed __aligned(CCB_ALIGN); | |
40 | ||
41 | ||
42 | /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */ | |
43 | ||
44 | #define CSB_V (0x80) | |
45 | #define CSB_F (0x04) | |
46 | #define CSB_CH (0x03) | |
47 | #define CSB_CE_INCOMPLETE (0x80) | |
48 | #define CSB_CE_TERMINATION (0x40) | |
49 | #define CSB_CE_TPBC (0x20) | |
50 | ||
51 | #define CSB_CC_SUCCESS (0) | |
52 | #define CSB_CC_INVALID_ALIGN (1) | |
53 | #define CSB_CC_OPERAND_OVERLAP (2) | |
54 | #define CSB_CC_DATA_LENGTH (3) | |
55 | #define CSB_CC_TRANSLATION (5) | |
56 | #define CSB_CC_PROTECTION (6) | |
57 | #define CSB_CC_RD_EXTERNAL (7) | |
58 | #define CSB_CC_INVALID_OPERAND (8) | |
59 | #define CSB_CC_PRIVILEGE (9) | |
60 | #define CSB_CC_INTERNAL (10) | |
61 | #define CSB_CC_WR_EXTERNAL (12) | |
62 | #define CSB_CC_NOSPC (13) | |
63 | #define CSB_CC_EXCESSIVE_DDE (14) | |
64 | #define CSB_CC_WR_TRANSLATION (15) | |
65 | #define CSB_CC_WR_PROTECTION (16) | |
66 | #define CSB_CC_UNKNOWN_CODE (17) | |
67 | #define CSB_CC_ABORT (18) | |
146e9f1b | 68 | #define CSB_CC_EXCEED_BYTE_COUNT (19) /* P9 or later */ |
edc424f8 | 69 | #define CSB_CC_TRANSPORT (20) |
146e9f1b HM |
70 | #define CSB_CC_INVALID_CRB (21) /* P9 or later */ |
71 | #define CSB_CC_INVALID_DDE (30) /* P9 or later */ | |
edc424f8 DS |
72 | #define CSB_CC_SEGMENTED_DDL (31) |
73 | #define CSB_CC_PROGRESS_POINT (32) | |
74 | #define CSB_CC_DDE_OVERFLOW (33) | |
75 | #define CSB_CC_SESSION (34) | |
76 | #define CSB_CC_PROVISION (36) | |
77 | #define CSB_CC_CHAIN (37) | |
78 | #define CSB_CC_SEQUENCE (38) | |
79 | #define CSB_CC_HW (39) | |
80 | ||
81 | #define CSB_SIZE (0x10) | |
82 | #define CSB_ALIGN CSB_SIZE | |
83 | ||
84 | struct coprocessor_status_block { | |
85 | u8 flags; | |
86 | u8 cs; | |
87 | u8 cc; | |
88 | u8 ce; | |
89 | __be32 count; | |
90 | __be64 address; | |
91 | } __packed __aligned(CSB_ALIGN); | |
92 | ||
93 | ||
94 | /* Chapter 6.5.10 Data-Descriptor List (DDL) | |
95 | * each list contains one or more Data-Descriptor Entries (DDE) | |
96 | */ | |
97 | ||
98 | #define DDE_P (0x8000) | |
99 | ||
100 | #define DDE_SIZE (0x10) | |
101 | #define DDE_ALIGN DDE_SIZE | |
102 | ||
103 | struct data_descriptor_entry { | |
104 | __be16 flags; | |
105 | u8 count; | |
106 | u8 index; | |
107 | __be32 length; | |
108 | __be64 address; | |
109 | } __packed __aligned(DDE_ALIGN); | |
110 | ||
111 | ||
112 | /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */ | |
113 | ||
114 | #define CRB_SIZE (0x80) | |
115 | #define CRB_ALIGN (0x100) /* Errata: requires 256 alignment */ | |
116 | ||
117 | /* Coprocessor Status Block field | |
118 | * ADDRESS address of CSB | |
119 | * C CCB is valid | |
120 | * AT 0 = addrs are virtual, 1 = addrs are phys | |
121 | * M enable perf monitor | |
122 | */ | |
123 | #define CRB_CSB_ADDRESS (0xfffffffffffffff0) | |
124 | #define CRB_CSB_C (0x0000000000000008) | |
125 | #define CRB_CSB_AT (0x0000000000000002) | |
126 | #define CRB_CSB_M (0x0000000000000001) | |
127 | ||
128 | struct coprocessor_request_block { | |
129 | __be32 ccw; | |
130 | __be32 flags; | |
131 | __be64 csb_addr; | |
132 | ||
133 | struct data_descriptor_entry source; | |
134 | struct data_descriptor_entry target; | |
135 | ||
136 | struct coprocessor_completion_block ccb; | |
137 | ||
138 | u8 reserved[48]; | |
139 | ||
140 | struct coprocessor_status_block csb; | |
141 | } __packed __aligned(CRB_ALIGN); | |
142 | ||
143 | ||
144 | /* RFC02167 Initiate Coprocessor Instructions document | |
145 | * Chapter 8.2.1.1.1 RS | |
146 | * Chapter 8.2.3 Coprocessor Directive | |
147 | * Chapter 8.2.4 Execution | |
148 | * | |
149 | * The CCW must be converted to BE before passing to icswx() | |
150 | */ | |
151 | ||
152 | #define CCW_PS (0xff000000) | |
153 | #define CCW_CT (0x00ff0000) | |
154 | #define CCW_CD (0x0000ffff) | |
155 | #define CCW_CL (0x0000c000) | |
156 | ||
157 | ||
158 | /* RFC02167 Initiate Coprocessor Instructions document | |
159 | * Chapter 8.2.1 Initiate Coprocessor Store Word Indexed (ICSWX) | |
160 | * Chapter 8.2.4.1 Condition Register 0 | |
161 | */ | |
162 | ||
163 | #define ICSWX_INITIATED (0x8) | |
164 | #define ICSWX_BUSY (0x4) | |
165 | #define ICSWX_REJECTED (0x2) | |
6333ed8f | 166 | #define ICSWX_XERS0 (0x1) /* undefined or set from XERSO. */ |
edc424f8 DS |
167 | |
168 | static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb) | |
169 | { | |
170 | __be64 ccw_reg = ccw; | |
171 | u32 cr; | |
172 | ||
173 | __asm__ __volatile__( | |
174 | PPC_ICSWX(%1,0,%2) "\n" | |
175 | "mfcr %0\n" | |
176 | : "=r" (cr) | |
177 | : "r" (ccw_reg), "r" (crb) | |
178 | : "cr0", "memory"); | |
179 | ||
180 | return (int)((cr >> 28) & 0xf); | |
181 | } | |
182 | ||
183 | ||
184 | #endif /* _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ */ |