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047ea784 PM |
1 | #ifndef _ASM_POWERPC_IO_H |
2 | #define _ASM_POWERPC_IO_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
1da177e4 | 4 | |
be135f40 | 5 | #define ARCH_HAS_IOREMAP_WC |
86c391bd CL |
6 | #ifdef CONFIG_PPC32 |
7 | #define ARCH_HAS_IOREMAP_WT | |
8 | #endif | |
be135f40 | 9 | |
b41e5fff | 10 | /* |
1da177e4 LT |
11 | * This program is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
1269277a DW |
17 | /* Check of existence of legacy devices */ |
18 | extern int check_legacy_ioport(unsigned long base_port); | |
8d8a0241 OH |
19 | #define I8042_DATA_REG 0x60 |
20 | #define FDC_BASE 0x3f0 | |
1269277a | 21 | |
e1612de9 HM |
22 | #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) |
23 | extern struct pci_dev *isa_bridge_pcidev; | |
24 | /* | |
25 | * has legacy ISA devices ? | |
26 | */ | |
ac237b65 | 27 | #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) |
e1612de9 HM |
28 | #endif |
29 | ||
b41e5fff | 30 | #include <linux/device.h> |
1da177e4 | 31 | #include <linux/compiler.h> |
6bf752da | 32 | #include <linux/mm.h> |
1da177e4 LT |
33 | #include <asm/page.h> |
34 | #include <asm/byteorder.h> | |
feaf7cf1 | 35 | #include <asm/synch.h> |
1da177e4 | 36 | #include <asm/delay.h> |
68a64357 | 37 | #include <asm/mmu.h> |
24bfa6a9 | 38 | #include <asm/ppc_asm.h> |
6bf752da | 39 | #include <asm/pgtable.h> |
1da177e4 | 40 | |
68a64357 BH |
41 | #ifdef CONFIG_PPC64 |
42 | #include <asm/paca.h> | |
43 | #endif | |
44 | ||
1da177e4 LT |
45 | #define SIO_CONFIG_RA 0x398 |
46 | #define SIO_CONFIG_RD 0x399 | |
47 | ||
48 | #define SLOW_DOWN_IO | |
49 | ||
68a64357 BH |
50 | /* 32 bits uses slightly different variables for the various IO |
51 | * bases. Most of this file only uses _IO_BASE though which we | |
52 | * define properly based on the platform | |
53 | */ | |
54 | #ifndef CONFIG_PCI | |
55 | #define _IO_BASE 0 | |
56 | #define _ISA_MEM_BASE 0 | |
57 | #define PCI_DRAM_OFFSET 0 | |
58 | #elif defined(CONFIG_PPC32) | |
59 | #define _IO_BASE isa_io_base | |
60 | #define _ISA_MEM_BASE isa_mem_base | |
61 | #define PCI_DRAM_OFFSET pci_dram_offset | |
62 | #else | |
63 | #define _IO_BASE pci_io_base | |
25e81f92 | 64 | #define _ISA_MEM_BASE isa_mem_base |
68a64357 BH |
65 | #define PCI_DRAM_OFFSET 0 |
66 | #endif | |
67 | ||
68 | extern unsigned long isa_io_base; | |
68a64357 BH |
69 | extern unsigned long pci_io_base; |
70 | extern unsigned long pci_dram_offset; | |
71 | ||
25e81f92 BH |
72 | extern resource_size_t isa_mem_base; |
73 | ||
3fafe9c2 BH |
74 | /* Boolean set by platform if PIO accesses are suppored while _IO_BASE |
75 | * is not set or addresses cannot be translated to MMIO. This is typically | |
76 | * set when the platform supports "special" PIO accesses via a non memory | |
77 | * mapped mechanism, and allows things like the early udbg UART code to | |
78 | * function. | |
79 | */ | |
80 | extern bool isa_io_special; | |
81 | ||
ecd73cc5 BH |
82 | #ifdef CONFIG_PPC32 |
83 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) | |
84 | #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits | |
85 | #endif | |
68a64357 BH |
86 | #endif |
87 | ||
4cb3cee0 BH |
88 | /* |
89 | * | |
90 | * Low level MMIO accessors | |
91 | * | |
92 | * This provides the non-bus specific accessors to MMIO. Those are PowerPC | |
93 | * specific and thus shouldn't be used in generic code. The accessors | |
94 | * provided here are: | |
95 | * | |
96 | * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 | |
97 | * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 | |
98 | * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns | |
99 | * | |
100 | * Those operate directly on a kernel virtual address. Note that the prototype | |
101 | * for the out_* accessors has the arguments in opposite order from the usual | |
102 | * linux PCI accessors. Unlike those, they take the address first and the value | |
103 | * next. | |
104 | * | |
105 | * Note: I might drop the _ns suffix on the stream operations soon as it is | |
106 | * simply normal for stream operations to not swap in the first place. | |
107 | * | |
108 | */ | |
109 | ||
68a64357 | 110 | #ifdef CONFIG_PPC64 |
048c8bc9 | 111 | #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) |
68a64357 BH |
112 | #else |
113 | #define IO_SET_SYNC_FLAG() | |
114 | #endif | |
4cb3cee0 | 115 | |
15cba23e | 116 | #define DEF_MMIO_IN_X(name, size, insn) \ |
0f3d6bcd TP |
117 | static inline u##size name(const volatile u##size __iomem *addr) \ |
118 | { \ | |
119 | u##size ret; \ | |
120 | __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ | |
121 | : "=r" (ret) : "Z" (*addr) : "memory"); \ | |
122 | return ret; \ | |
123 | } | |
124 | ||
15cba23e | 125 | #define DEF_MMIO_OUT_X(name, size, insn) \ |
0f3d6bcd TP |
126 | static inline void name(volatile u##size __iomem *addr, u##size val) \ |
127 | { \ | |
128 | __asm__ __volatile__("sync;"#insn" %1,%y0" \ | |
129 | : "=Z" (*addr) : "r" (val) : "memory"); \ | |
130 | IO_SET_SYNC_FLAG(); \ | |
131 | } | |
4cb3cee0 | 132 | |
15cba23e | 133 | #define DEF_MMIO_IN_D(name, size, insn) \ |
0f3d6bcd TP |
134 | static inline u##size name(const volatile u##size __iomem *addr) \ |
135 | { \ | |
136 | u##size ret; \ | |
137 | __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ | |
138 | : "=r" (ret) : "m" (*addr) : "memory"); \ | |
139 | return ret; \ | |
140 | } | |
4cb3cee0 | 141 | |
15cba23e | 142 | #define DEF_MMIO_OUT_D(name, size, insn) \ |
0f3d6bcd TP |
143 | static inline void name(volatile u##size __iomem *addr, u##size val) \ |
144 | { \ | |
145 | __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ | |
146 | : "=m" (*addr) : "r" (val) : "memory"); \ | |
147 | IO_SET_SYNC_FLAG(); \ | |
148 | } | |
4cb3cee0 | 149 | |
15cba23e IM |
150 | DEF_MMIO_IN_D(in_8, 8, lbz); |
151 | DEF_MMIO_OUT_D(out_8, 8, stb); | |
4cb3cee0 | 152 | |
15cba23e IM |
153 | #ifdef __BIG_ENDIAN__ |
154 | DEF_MMIO_IN_D(in_be16, 16, lhz); | |
155 | DEF_MMIO_IN_D(in_be32, 32, lwz); | |
156 | DEF_MMIO_IN_X(in_le16, 16, lhbrx); | |
157 | DEF_MMIO_IN_X(in_le32, 32, lwbrx); | |
4cb3cee0 | 158 | |
15cba23e IM |
159 | DEF_MMIO_OUT_D(out_be16, 16, sth); |
160 | DEF_MMIO_OUT_D(out_be32, 32, stw); | |
161 | DEF_MMIO_OUT_X(out_le16, 16, sthbrx); | |
162 | DEF_MMIO_OUT_X(out_le32, 32, stwbrx); | |
163 | #else | |
164 | DEF_MMIO_IN_X(in_be16, 16, lhbrx); | |
165 | DEF_MMIO_IN_X(in_be32, 32, lwbrx); | |
166 | DEF_MMIO_IN_D(in_le16, 16, lhz); | |
167 | DEF_MMIO_IN_D(in_le32, 32, lwz); | |
168 | ||
169 | DEF_MMIO_OUT_X(out_be16, 16, sthbrx); | |
170 | DEF_MMIO_OUT_X(out_be32, 32, stwbrx); | |
171 | DEF_MMIO_OUT_D(out_le16, 16, sth); | |
172 | DEF_MMIO_OUT_D(out_le32, 32, stw); | |
173 | ||
174 | #endif /* __BIG_ENDIAN */ | |
4cb3cee0 | 175 | |
68a64357 | 176 | #ifdef __powerpc64__ |
15cba23e IM |
177 | |
178 | #ifdef __BIG_ENDIAN__ | |
179 | DEF_MMIO_OUT_D(out_be64, 64, std); | |
180 | DEF_MMIO_IN_D(in_be64, 64, ld); | |
68a64357 | 181 | |
4cb3cee0 BH |
182 | /* There is no asm instructions for 64 bits reverse loads and stores */ |
183 | static inline u64 in_le64(const volatile u64 __iomem *addr) | |
184 | { | |
bda76dd1 | 185 | return swab64(in_be64(addr)); |
4cb3cee0 BH |
186 | } |
187 | ||
188 | static inline void out_le64(volatile u64 __iomem *addr, u64 val) | |
189 | { | |
bda76dd1 | 190 | out_be64(addr, swab64(val)); |
4cb3cee0 | 191 | } |
15cba23e IM |
192 | #else |
193 | DEF_MMIO_OUT_D(out_le64, 64, std); | |
194 | DEF_MMIO_IN_D(in_le64, 64, ld); | |
195 | ||
196 | /* There is no asm instructions for 64 bits reverse loads and stores */ | |
197 | static inline u64 in_be64(const volatile u64 __iomem *addr) | |
198 | { | |
199 | return swab64(in_le64(addr)); | |
200 | } | |
201 | ||
202 | static inline void out_be64(volatile u64 __iomem *addr, u64 val) | |
203 | { | |
204 | out_le64(addr, swab64(val)); | |
205 | } | |
206 | ||
207 | #endif | |
68a64357 | 208 | #endif /* __powerpc64__ */ |
4cb3cee0 BH |
209 | |
210 | /* | |
211 | * Low level IO stream instructions are defined out of line for now | |
212 | */ | |
213 | extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); | |
214 | extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); | |
215 | extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); | |
216 | extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); | |
217 | extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); | |
218 | extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); | |
219 | ||
220 | /* The _ns naming is historical and will be removed. For now, just #define | |
221 | * the non _ns equivalent names | |
222 | */ | |
223 | #define _insw _insw_ns | |
224 | #define _insl _insl_ns | |
225 | #define _outsw _outsw_ns | |
226 | #define _outsl _outsl_ns | |
227 | ||
68a64357 BH |
228 | |
229 | /* | |
230 | * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line | |
231 | */ | |
232 | ||
233 | extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); | |
234 | extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, | |
235 | unsigned long n); | |
236 | extern void _memcpy_toio(volatile void __iomem *dest, const void *src, | |
237 | unsigned long n); | |
238 | ||
4cb3cee0 BH |
239 | /* |
240 | * | |
241 | * PCI and standard ISA accessors | |
242 | * | |
243 | * Those are globally defined linux accessors for devices on PCI or ISA | |
244 | * busses. They follow the Linux defined semantics. The current implementation | |
245 | * for PowerPC is as close as possible to the x86 version of these, and thus | |
246 | * provides fairly heavy weight barriers for the non-raw versions | |
247 | * | |
ecd73cc5 BH |
248 | * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO |
249 | * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its | |
250 | * own implementation of some or all of the accessors. | |
4cb3cee0 BH |
251 | */ |
252 | ||
68a64357 BH |
253 | /* |
254 | * Include the EEH definitions when EEH is enabled only so they don't get | |
255 | * in the way when building for 32 bits | |
256 | */ | |
257 | #ifdef CONFIG_EEH | |
4cb3cee0 | 258 | #include <asm/eeh.h> |
68a64357 | 259 | #endif |
4cb3cee0 BH |
260 | |
261 | /* Shortcut to the MMIO argument pointer */ | |
262 | #define PCI_IO_ADDR volatile void __iomem * | |
263 | ||
264 | /* Indirect IO address tokens: | |
265 | * | |
ecd73cc5 BH |
266 | * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks |
267 | * on all MMIOs. (Note that this is all 64 bits only for now) | |
4cb3cee0 | 268 | * |
446957ba | 269 | * To help platforms who may need to differentiate MMIO addresses in |
4cb3cee0 BH |
270 | * their hooks, a bitfield is reserved for use by the platform near the |
271 | * top of MMIO addresses (not PIO, those have to cope the hard way). | |
272 | * | |
43c6494f | 273 | * The highest address in the kernel virtual space are: |
4cb3cee0 | 274 | * |
43c6494f ME |
275 | * d0003fffffffffff # with Hash MMU |
276 | * c00fffffffffffff # with Radix MMU | |
4cb3cee0 | 277 | * |
43c6494f ME |
278 | * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits |
279 | * that can be used for the field. | |
4cb3cee0 BH |
280 | * |
281 | * The direct IO mapping operations will then mask off those bits | |
282 | * before doing the actual access, though that only happen when | |
ecd73cc5 | 283 | * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that |
4cb3cee0 | 284 | * mechanism |
ecd73cc5 BH |
285 | * |
286 | * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes | |
287 | * all PIO functions call through a hook. | |
4cb3cee0 BH |
288 | */ |
289 | ||
ecd73cc5 | 290 | #ifdef CONFIG_PPC_INDIRECT_MMIO |
43c6494f ME |
291 | #define PCI_IO_IND_TOKEN_SHIFT 52 |
292 | #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT) | |
4cb3cee0 BH |
293 | #define PCI_FIX_ADDR(addr) \ |
294 | ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) | |
295 | #define PCI_GET_ADDR_TOKEN(addr) \ | |
296 | (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ | |
297 | PCI_IO_IND_TOKEN_SHIFT) | |
298 | #define PCI_SET_ADDR_TOKEN(addr, token) \ | |
299 | do { \ | |
300 | unsigned long __a = (unsigned long)(addr); \ | |
301 | __a &= ~PCI_IO_IND_TOKEN_MASK; \ | |
302 | __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ | |
303 | (addr) = (void __iomem *)__a; \ | |
304 | } while(0) | |
305 | #else | |
306 | #define PCI_FIX_ADDR(addr) (addr) | |
307 | #endif | |
308 | ||
757db1ed BH |
309 | |
310 | /* | |
311 | * Non ordered and non-swapping "raw" accessors | |
312 | */ | |
313 | ||
314 | static inline unsigned char __raw_readb(const volatile void __iomem *addr) | |
315 | { | |
316 | return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); | |
317 | } | |
318 | static inline unsigned short __raw_readw(const volatile void __iomem *addr) | |
319 | { | |
320 | return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); | |
321 | } | |
322 | static inline unsigned int __raw_readl(const volatile void __iomem *addr) | |
323 | { | |
324 | return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); | |
325 | } | |
326 | static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) | |
327 | { | |
328 | *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; | |
329 | } | |
330 | static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) | |
331 | { | |
332 | *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; | |
333 | } | |
334 | static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) | |
335 | { | |
336 | *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; | |
337 | } | |
338 | ||
339 | #ifdef __powerpc64__ | |
340 | static inline unsigned long __raw_readq(const volatile void __iomem *addr) | |
341 | { | |
342 | return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); | |
343 | } | |
344 | static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) | |
345 | { | |
346 | *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; | |
347 | } | |
a84bf321 | 348 | |
8056fe28 ME |
349 | static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) |
350 | { | |
351 | __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); | |
352 | } | |
353 | ||
a84bf321 | 354 | /* |
d381d7ca BH |
355 | * Real mode versions of the above. Those instructions are only supposed |
356 | * to be used in hypervisor real mode as per the architecture spec. | |
a84bf321 | 357 | */ |
d381d7ca BH |
358 | static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) |
359 | { | |
360 | __asm__ __volatile__("stbcix %0,0,%1" | |
361 | : : "r" (val), "r" (paddr) : "memory"); | |
362 | } | |
363 | ||
364 | static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) | |
365 | { | |
366 | __asm__ __volatile__("sthcix %0,0,%1" | |
367 | : : "r" (val), "r" (paddr) : "memory"); | |
368 | } | |
369 | ||
370 | static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) | |
371 | { | |
372 | __asm__ __volatile__("stwcix %0,0,%1" | |
373 | : : "r" (val), "r" (paddr) : "memory"); | |
374 | } | |
375 | ||
a84bf321 AP |
376 | static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) |
377 | { | |
378 | __asm__ __volatile__("stdcix %0,0,%1" | |
379 | : : "r" (val), "r" (paddr) : "memory"); | |
380 | } | |
381 | ||
8056fe28 ME |
382 | static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) |
383 | { | |
384 | __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); | |
385 | } | |
386 | ||
d381d7ca BH |
387 | static inline u8 __raw_rm_readb(volatile void __iomem *paddr) |
388 | { | |
389 | u8 ret; | |
390 | __asm__ __volatile__("lbzcix %0,0, %1" | |
391 | : "=r" (ret) : "r" (paddr) : "memory"); | |
392 | return ret; | |
393 | } | |
394 | ||
395 | static inline u16 __raw_rm_readw(volatile void __iomem *paddr) | |
396 | { | |
397 | u16 ret; | |
398 | __asm__ __volatile__("lhzcix %0,0, %1" | |
399 | : "=r" (ret) : "r" (paddr) : "memory"); | |
400 | return ret; | |
401 | } | |
402 | ||
403 | static inline u32 __raw_rm_readl(volatile void __iomem *paddr) | |
404 | { | |
405 | u32 ret; | |
406 | __asm__ __volatile__("lwzcix %0,0, %1" | |
407 | : "=r" (ret) : "r" (paddr) : "memory"); | |
408 | return ret; | |
409 | } | |
410 | ||
411 | static inline u64 __raw_rm_readq(volatile void __iomem *paddr) | |
412 | { | |
413 | u64 ret; | |
414 | __asm__ __volatile__("ldcix %0,0, %1" | |
415 | : "=r" (ret) : "r" (paddr) : "memory"); | |
416 | return ret; | |
417 | } | |
757db1ed BH |
418 | #endif /* __powerpc64__ */ |
419 | ||
68a64357 | 420 | /* |
757db1ed BH |
421 | * |
422 | * PCI PIO and MMIO accessors. | |
423 | * | |
424 | * | |
68a64357 BH |
425 | * On 32 bits, PIO operations have a recovery mechanism in case they trigger |
426 | * machine checks (which they occasionally do when probing non existing | |
427 | * IO ports on some platforms, like PowerMac and 8xx). | |
428 | * I always found it to be of dubious reliability and I am tempted to get | |
429 | * rid of it one of these days. So if you think it's important to keep it, | |
430 | * please voice up asap. We never had it for 64 bits and I do not intend | |
431 | * to port it over | |
432 | */ | |
433 | ||
434 | #ifdef CONFIG_PPC32 | |
435 | ||
436 | #define __do_in_asm(name, op) \ | |
4cfbdfff | 437 | static inline unsigned int name(unsigned int port) \ |
68a64357 BH |
438 | { \ |
439 | unsigned int x; \ | |
440 | __asm__ __volatile__( \ | |
441 | "sync\n" \ | |
442 | "0:" op " %0,0,%1\n" \ | |
443 | "1: twi 0,%0,0\n" \ | |
444 | "2: isync\n" \ | |
445 | "3: nop\n" \ | |
446 | "4:\n" \ | |
447 | ".section .fixup,\"ax\"\n" \ | |
448 | "5: li %0,-1\n" \ | |
449 | " b 4b\n" \ | |
450 | ".previous\n" \ | |
24bfa6a9 NP |
451 | EX_TABLE(0b, 5b) \ |
452 | EX_TABLE(1b, 5b) \ | |
453 | EX_TABLE(2b, 5b) \ | |
454 | EX_TABLE(3b, 5b) \ | |
68a64357 | 455 | : "=&r" (x) \ |
cfab3bdf BH |
456 | : "r" (port + _IO_BASE) \ |
457 | : "memory"); \ | |
68a64357 BH |
458 | return x; \ |
459 | } | |
460 | ||
461 | #define __do_out_asm(name, op) \ | |
4cfbdfff | 462 | static inline void name(unsigned int val, unsigned int port) \ |
68a64357 BH |
463 | { \ |
464 | __asm__ __volatile__( \ | |
465 | "sync\n" \ | |
466 | "0:" op " %0,0,%1\n" \ | |
467 | "1: sync\n" \ | |
468 | "2:\n" \ | |
24bfa6a9 NP |
469 | EX_TABLE(0b, 2b) \ |
470 | EX_TABLE(1b, 2b) \ | |
cfab3bdf BH |
471 | : : "r" (val), "r" (port + _IO_BASE) \ |
472 | : "memory"); \ | |
68a64357 BH |
473 | } |
474 | ||
475 | __do_in_asm(_rec_inb, "lbzx") | |
476 | __do_in_asm(_rec_inw, "lhbrx") | |
477 | __do_in_asm(_rec_inl, "lwbrx") | |
478 | __do_out_asm(_rec_outb, "stbx") | |
479 | __do_out_asm(_rec_outw, "sthbrx") | |
480 | __do_out_asm(_rec_outl, "stwbrx") | |
481 | ||
482 | #endif /* CONFIG_PPC32 */ | |
483 | ||
4cb3cee0 | 484 | /* The "__do_*" operations below provide the actual "base" implementation |
42b2aa86 | 485 | * for each of the defined accessors. Some of them use the out_* functions |
4cb3cee0 BH |
486 | * directly, some of them still use EEH, though we might change that in the |
487 | * future. Those macros below provide the necessary argument swapping and | |
488 | * handling of the IO base for PIO. | |
489 | * | |
490 | * They are themselves used by the macros that define the actual accessors | |
491 | * and can be used by the hooks if any. | |
492 | * | |
493 | * Note that PIO operations are always defined in terms of their corresonding | |
494 | * MMIO operations. That allows platforms like iSeries who want to modify the | |
495 | * behaviour of both to only hook on the MMIO version and get both. It's also | |
496 | * possible to hook directly at the toplevel PIO operation if they have to | |
497 | * be handled differently | |
498 | */ | |
499 | #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) | |
500 | #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) | |
501 | #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) | |
502 | #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) | |
503 | #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) | |
504 | #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) | |
505 | #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) | |
68a64357 BH |
506 | |
507 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
508 | #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) |
509 | #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) | |
510 | #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) | |
511 | #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) | |
512 | #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) | |
513 | #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) | |
514 | #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) | |
68a64357 BH |
515 | #else /* CONFIG_EEH */ |
516 | #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) | |
517 | #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) | |
518 | #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) | |
519 | #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) | |
520 | #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) | |
521 | #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) | |
522 | #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) | |
523 | #endif /* !defined(CONFIG_EEH) */ | |
524 | ||
525 | #ifdef CONFIG_PPC32 | |
526 | #define __do_outb(val, port) _rec_outb(val, port) | |
527 | #define __do_outw(val, port) _rec_outw(val, port) | |
528 | #define __do_outl(val, port) _rec_outl(val, port) | |
529 | #define __do_inb(port) _rec_inb(port) | |
530 | #define __do_inw(port) _rec_inw(port) | |
531 | #define __do_inl(port) _rec_inl(port) | |
532 | #else /* CONFIG_PPC32 */ | |
533 | #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); | |
534 | #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); | |
535 | #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); | |
536 | #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); | |
537 | #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); | |
538 | #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); | |
539 | #endif /* !CONFIG_PPC32 */ | |
540 | ||
541 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
542 | #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) |
543 | #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) | |
544 | #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) | |
68a64357 BH |
545 | #else /* CONFIG_EEH */ |
546 | #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) | |
547 | #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) | |
548 | #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) | |
549 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 BH |
550 | #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) |
551 | #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) | |
552 | #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) | |
553 | ||
68a64357 BH |
554 | #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) |
555 | #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
556 | #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
557 | #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
558 | #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
559 | #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
560 | ||
561 | #define __do_memset_io(addr, c, n) \ | |
562 | _memset_io(PCI_FIX_ADDR(addr), c, n) | |
563 | #define __do_memcpy_toio(dst, src, n) \ | |
564 | _memcpy_toio(PCI_FIX_ADDR(dst), src, n) | |
565 | ||
566 | #ifdef CONFIG_EEH | |
567 | #define __do_memcpy_fromio(dst, src, n) \ | |
568 | eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) | |
569 | #else /* CONFIG_EEH */ | |
570 | #define __do_memcpy_fromio(dst, src, n) \ | |
571 | _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) | |
572 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 | 573 | |
21176fed ME |
574 | #ifdef CONFIG_PPC_INDIRECT_PIO |
575 | #define DEF_PCI_HOOK_pio(x) x | |
576 | #else | |
577 | #define DEF_PCI_HOOK_pio(x) NULL | |
578 | #endif | |
579 | ||
580 | #ifdef CONFIG_PPC_INDIRECT_MMIO | |
581 | #define DEF_PCI_HOOK_mem(x) x | |
4cb3cee0 | 582 | #else |
21176fed | 583 | #define DEF_PCI_HOOK_mem(x) NULL |
4cb3cee0 BH |
584 | #endif |
585 | ||
586 | /* Structure containing all the hooks */ | |
587 | extern struct ppc_pci_io { | |
588 | ||
7cfb62a2 IK |
589 | #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; |
590 | #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; | |
4cb3cee0 BH |
591 | |
592 | #include <asm/io-defs.h> | |
593 | ||
594 | #undef DEF_PCI_AC_RET | |
595 | #undef DEF_PCI_AC_NORET | |
596 | ||
597 | } ppc_pci_io; | |
598 | ||
599 | /* The inline wrappers */ | |
7cfb62a2 | 600 | #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ |
4cb3cee0 BH |
601 | static inline ret name at \ |
602 | { \ | |
21176fed | 603 | if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ |
4cb3cee0 BH |
604 | return ppc_pci_io.name al; \ |
605 | return __do_##name al; \ | |
606 | } | |
607 | ||
7cfb62a2 | 608 | #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ |
4cb3cee0 BH |
609 | static inline void name at \ |
610 | { \ | |
21176fed | 611 | if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ |
4cb3cee0 BH |
612 | ppc_pci_io.name al; \ |
613 | else \ | |
614 | __do_##name al; \ | |
615 | } | |
616 | ||
617 | #include <asm/io-defs.h> | |
618 | ||
619 | #undef DEF_PCI_AC_RET | |
620 | #undef DEF_PCI_AC_NORET | |
621 | ||
622 | /* Some drivers check for the presence of readq & writeq with | |
623 | * a #ifdef, so we make them happy here. | |
624 | */ | |
68a64357 | 625 | #ifdef __powerpc64__ |
4cb3cee0 BH |
626 | #define readq readq |
627 | #define writeq writeq | |
68a64357 BH |
628 | #endif |
629 | ||
4cb3cee0 BH |
630 | /* |
631 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
632 | * access | |
633 | */ | |
634 | #define xlate_dev_mem_ptr(p) __va(p) | |
635 | ||
636 | /* | |
637 | * Convert a virtual cached pointer to an uncached pointer | |
638 | */ | |
639 | #define xlate_dev_kmem_ptr(p) p | |
caf81329 | 640 | |
4cb3cee0 BH |
641 | /* |
642 | * We don't do relaxed operations yet, at least not with this semantic | |
643 | */ | |
5da59057 WD |
644 | #define readb_relaxed(addr) readb(addr) |
645 | #define readw_relaxed(addr) readw(addr) | |
646 | #define readl_relaxed(addr) readl(addr) | |
647 | #define readq_relaxed(addr) readq(addr) | |
648 | #define writeb_relaxed(v, addr) writeb(v, addr) | |
649 | #define writew_relaxed(v, addr) writew(v, addr) | |
650 | #define writel_relaxed(v, addr) writel(v, addr) | |
651 | #define writeq_relaxed(v, addr) writeq(v, addr) | |
1da177e4 | 652 | |
ef237039 LG |
653 | #include <asm-generic/iomap.h> |
654 | ||
68a64357 BH |
655 | #ifdef CONFIG_PPC32 |
656 | #define mmiowb() | |
657 | #else | |
4cb3cee0 BH |
658 | /* |
659 | * Enforce synchronisation of stores vs. spin_unlock | |
c03983ac | 660 | * (this does it explicitly, though our implementation of spin_unlock |
4cb3cee0 BH |
661 | * does it implicitely too) |
662 | */ | |
f007cacf PM |
663 | static inline void mmiowb(void) |
664 | { | |
292f86f0 HD |
665 | unsigned long tmp; |
666 | ||
667 | __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" | |
668 | : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) | |
669 | : "memory"); | |
f007cacf | 670 | } |
68a64357 | 671 | #endif /* !CONFIG_PPC32 */ |
1da177e4 | 672 | |
4cb3cee0 BH |
673 | static inline void iosync(void) |
674 | { | |
675 | __asm__ __volatile__ ("sync" : : : "memory"); | |
676 | } | |
677 | ||
678 | /* Enforce in-order execution of data I/O. | |
679 | * No distinction between read/write on PPC; use eieio for all three. | |
680 | * Those are fairly week though. They don't provide a barrier between | |
681 | * MMIO and cacheable storage nor do they provide a barrier vs. locks, | |
682 | * they only provide barriers between 2 __raw MMIO operations and | |
683 | * possibly break write combining. | |
684 | */ | |
685 | #define iobarrier_rw() eieio() | |
686 | #define iobarrier_r() eieio() | |
687 | #define iobarrier_w() eieio() | |
688 | ||
689 | ||
1da177e4 LT |
690 | /* |
691 | * output pause versions need a delay at least for the | |
692 | * w83c105 ide controller in a p610. | |
693 | */ | |
694 | #define inb_p(port) inb(port) | |
695 | #define outb_p(val, port) (udelay(1), outb((val), (port))) | |
696 | #define inw_p(port) inw(port) | |
697 | #define outw_p(val, port) (udelay(1), outw((val), (port))) | |
698 | #define inl_p(port) inl(port) | |
699 | #define outl_p(val, port) (udelay(1), outl((val), (port))) | |
700 | ||
1da177e4 LT |
701 | |
702 | #define IO_SPACE_LIMIT ~(0UL) | |
703 | ||
704 | ||
1da177e4 LT |
705 | /** |
706 | * ioremap - map bus memory into CPU space | |
707 | * @address: bus address of the memory | |
708 | * @size: size of the resource to map | |
709 | * | |
710 | * ioremap performs a platform specific sequence of operations to | |
711 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
712 | * writew/writel functions and the other mmio helpers. The returned | |
713 | * address is not guaranteed to be usable directly as a virtual | |
714 | * address. | |
4cb3cee0 BH |
715 | * |
716 | * We provide a few variations of it: | |
717 | * | |
718 | * * ioremap is the standard one and provides non-cacheable guarded mappings | |
719 | * and can be hooked by the platform via ppc_md | |
720 | * | |
40f1ce7f AB |
721 | * * ioremap_prot allows to specify the page flags as an argument and can |
722 | * also be hooked by the platform via ppc_md. | |
4cb3cee0 BH |
723 | * |
724 | * * ioremap_nocache is identical to ioremap | |
725 | * | |
be135f40 AB |
726 | * * ioremap_wc enables write combining |
727 | * | |
86c391bd CL |
728 | * * ioremap_wt enables write through |
729 | * | |
730 | * * ioremap_coherent maps coherent cached memory | |
731 | * | |
4cb3cee0 BH |
732 | * * iounmap undoes such a mapping and can be hooked |
733 | * | |
3d5134ee BH |
734 | * * __ioremap_at (and the pending __iounmap_at) are low level functions to |
735 | * create hand-made mappings for use only by the PCI code and cannot | |
736 | * currently be hooked. Must be page aligned. | |
4cb3cee0 BH |
737 | * |
738 | * * __ioremap is the low level implementation used by ioremap and | |
40f1ce7f | 739 | * ioremap_prot and cannot be hooked (but can be used by a hook on one |
4cb3cee0 BH |
740 | * of the previous ones) |
741 | * | |
1cdab55d BH |
742 | * * __ioremap_caller is the same as above but takes an explicit caller |
743 | * reference rather than using __builtin_return_address(0) | |
744 | * | |
4cb3cee0 BH |
745 | * * __iounmap, is the low level implementation used by iounmap and cannot |
746 | * be hooked (but can be used by a hook on iounmap) | |
747 | * | |
1da177e4 | 748 | */ |
68a64357 | 749 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); |
40f1ce7f AB |
750 | extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, |
751 | unsigned long flags); | |
be135f40 | 752 | extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); |
86c391bd CL |
753 | void __iomem *ioremap_wt(phys_addr_t address, unsigned long size); |
754 | void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size); | |
1da177e4 | 755 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) |
4c73e892 | 756 | #define ioremap_uc(addr, size) ioremap((addr), (size)) |
f855b2f5 OH |
757 | #define ioremap_cache(addr, size) \ |
758 | ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) | |
a1f242ff | 759 | |
68a64357 | 760 | extern void iounmap(volatile void __iomem *addr); |
4cb3cee0 | 761 | |
68a64357 | 762 | extern void __iomem *__ioremap(phys_addr_t, unsigned long size, |
4cb3cee0 | 763 | unsigned long flags); |
1cdab55d | 764 | extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, |
c766ee72 | 765 | pgprot_t prot, void *caller); |
1cdab55d | 766 | |
68a64357 | 767 | extern void __iounmap(volatile void __iomem *addr); |
4cb3cee0 | 768 | |
3d5134ee | 769 | extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, |
c766ee72 | 770 | unsigned long size, pgprot_t prot); |
3d5134ee | 771 | extern void __iounmap_at(void *ea, unsigned long size); |
1da177e4 | 772 | |
4cb3cee0 | 773 | /* |
ecd73cc5 | 774 | * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation |
4cb3cee0 BH |
775 | * which needs some additional definitions here. They basically allow PIO |
776 | * space overall to be 1GB. This will work as long as we never try to use | |
777 | * iomap to map MMIO below 1GB which should be fine on ppc64 | |
778 | */ | |
779 | #define HAVE_ARCH_PIO_SIZE 1 | |
780 | #define PIO_OFFSET 0x00000000UL | |
3d5134ee BH |
781 | #define PIO_MASK (FULL_IO_SIZE - 1) |
782 | #define PIO_RESERVED (FULL_IO_SIZE) | |
4cb3cee0 BH |
783 | |
784 | #define mmio_read16be(addr) readw_be(addr) | |
785 | #define mmio_read32be(addr) readl_be(addr) | |
786 | #define mmio_write16be(val, addr) writew_be(val, addr) | |
787 | #define mmio_write32be(val, addr) writel_be(val, addr) | |
788 | #define mmio_insb(addr, dst, count) readsb(addr, dst, count) | |
789 | #define mmio_insw(addr, dst, count) readsw(addr, dst, count) | |
790 | #define mmio_insl(addr, dst, count) readsl(addr, dst, count) | |
791 | #define mmio_outsb(addr, src, count) writesb(addr, src, count) | |
792 | #define mmio_outsw(addr, src, count) writesw(addr, src, count) | |
793 | #define mmio_outsl(addr, src, count) writesl(addr, src, count) | |
794 | ||
1da177e4 LT |
795 | /** |
796 | * virt_to_phys - map virtual addresses to physical | |
797 | * @address: address to remap | |
798 | * | |
799 | * The returned physical address is the physical (CPU) mapping for | |
800 | * the memory address given. It is only valid to use this function on | |
801 | * addresses directly mapped or allocated via kmalloc. | |
802 | * | |
803 | * This function does not give bus mappings for DMA transfers. In | |
804 | * almost all conceivable cases a device driver should not be using | |
805 | * this function | |
806 | */ | |
807 | static inline unsigned long virt_to_phys(volatile void * address) | |
808 | { | |
6bf752da CL |
809 | WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address)); |
810 | ||
1da177e4 LT |
811 | return __pa((unsigned long)address); |
812 | } | |
813 | ||
814 | /** | |
815 | * phys_to_virt - map physical address to virtual | |
816 | * @address: address to remap | |
817 | * | |
818 | * The returned virtual address is a current CPU mapping for | |
819 | * the memory address given. It is only valid to use this function on | |
820 | * addresses that have a kernel mapping | |
821 | * | |
822 | * This function does not handle bus mappings for DMA transfers. In | |
823 | * almost all conceivable cases a device driver should not be using | |
824 | * this function | |
825 | */ | |
826 | static inline void * phys_to_virt(unsigned long address) | |
827 | { | |
828 | return (void *)__va(address); | |
829 | } | |
830 | ||
831 | /* | |
832 | * Change "struct page" to physical address. | |
833 | */ | |
6bf752da CL |
834 | static inline phys_addr_t page_to_phys(struct page *page) |
835 | { | |
836 | unsigned long pfn = page_to_pfn(page); | |
837 | ||
838 | WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn)); | |
839 | ||
840 | return PFN_PHYS(pfn); | |
841 | } | |
1da177e4 | 842 | |
68a64357 BH |
843 | /* |
844 | * 32 bits still uses virt_to_bus() for it's implementation of DMA | |
845 | * mappings se we have to keep it defined here. We also have some old | |
846 | * drivers (shame shame shame) that use bus_to_virt() and haven't been | |
847 | * fixed yet so I need to define it here. | |
848 | */ | |
849 | #ifdef CONFIG_PPC32 | |
850 | ||
851 | static inline unsigned long virt_to_bus(volatile void * address) | |
852 | { | |
853 | if (address == NULL) | |
854 | return 0; | |
855 | return __pa(address) + PCI_DRAM_OFFSET; | |
856 | } | |
857 | ||
858 | static inline void * bus_to_virt(unsigned long address) | |
859 | { | |
860 | if (address == 0) | |
861 | return NULL; | |
862 | return __va(address - PCI_DRAM_OFFSET); | |
863 | } | |
864 | ||
865 | #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) | |
866 | ||
867 | #endif /* CONFIG_PPC32 */ | |
868 | ||
5427828e VB |
869 | /* access ports */ |
870 | #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) | |
871 | #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) | |
872 | ||
873 | #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) | |
874 | #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) | |
68a64357 | 875 | |
12cdac34 SW |
876 | #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) |
877 | #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) | |
878 | ||
dc967d7f TT |
879 | /* Clear and set bits in one shot. These macros can be used to clear and |
880 | * set multiple bits in a register using a single read-modify-write. These | |
881 | * macros can also be used to set a multiple-bit bit pattern using a mask, | |
882 | * by specifying the mask in the 'clear' parameter and the new bit pattern | |
883 | * in the 'set' parameter. | |
884 | */ | |
885 | ||
886 | #define clrsetbits(type, addr, clear, set) \ | |
887 | out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) | |
888 | ||
889 | #ifdef __powerpc64__ | |
890 | #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) | |
891 | #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) | |
892 | #endif | |
893 | ||
894 | #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) | |
895 | #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) | |
896 | ||
897 | #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) | |
e2d75505 | 898 | #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) |
dc967d7f TT |
899 | |
900 | #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) | |
901 | ||
1da177e4 LT |
902 | #endif /* __KERNEL__ */ |
903 | ||
047ea784 | 904 | #endif /* _ASM_POWERPC_IO_H */ |