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047ea784 PM |
1 | #ifndef _ASM_POWERPC_IO_H |
2 | #define _ASM_POWERPC_IO_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
1da177e4 | 4 | |
be135f40 AB |
5 | #define ARCH_HAS_IOREMAP_WC |
6 | ||
b41e5fff | 7 | /* |
1da177e4 LT |
8 | * This program is free software; you can redistribute it and/or |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
1269277a DW |
14 | /* Check of existence of legacy devices */ |
15 | extern int check_legacy_ioport(unsigned long base_port); | |
8d8a0241 OH |
16 | #define I8042_DATA_REG 0x60 |
17 | #define FDC_BASE 0x3f0 | |
1269277a | 18 | |
e1612de9 HM |
19 | #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) |
20 | extern struct pci_dev *isa_bridge_pcidev; | |
21 | /* | |
22 | * has legacy ISA devices ? | |
23 | */ | |
ac237b65 | 24 | #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) |
e1612de9 HM |
25 | #endif |
26 | ||
b41e5fff | 27 | #include <linux/device.h> |
1da177e4 LT |
28 | #include <linux/compiler.h> |
29 | #include <asm/page.h> | |
30 | #include <asm/byteorder.h> | |
feaf7cf1 | 31 | #include <asm/synch.h> |
1da177e4 | 32 | #include <asm/delay.h> |
68a64357 | 33 | #include <asm/mmu.h> |
24bfa6a9 | 34 | #include <asm/ppc_asm.h> |
1da177e4 | 35 | |
68a64357 BH |
36 | #ifdef CONFIG_PPC64 |
37 | #include <asm/paca.h> | |
38 | #endif | |
39 | ||
1da177e4 LT |
40 | #define SIO_CONFIG_RA 0x398 |
41 | #define SIO_CONFIG_RD 0x399 | |
42 | ||
43 | #define SLOW_DOWN_IO | |
44 | ||
68a64357 BH |
45 | /* 32 bits uses slightly different variables for the various IO |
46 | * bases. Most of this file only uses _IO_BASE though which we | |
47 | * define properly based on the platform | |
48 | */ | |
49 | #ifndef CONFIG_PCI | |
50 | #define _IO_BASE 0 | |
51 | #define _ISA_MEM_BASE 0 | |
52 | #define PCI_DRAM_OFFSET 0 | |
53 | #elif defined(CONFIG_PPC32) | |
54 | #define _IO_BASE isa_io_base | |
55 | #define _ISA_MEM_BASE isa_mem_base | |
56 | #define PCI_DRAM_OFFSET pci_dram_offset | |
57 | #else | |
58 | #define _IO_BASE pci_io_base | |
25e81f92 | 59 | #define _ISA_MEM_BASE isa_mem_base |
68a64357 BH |
60 | #define PCI_DRAM_OFFSET 0 |
61 | #endif | |
62 | ||
63 | extern unsigned long isa_io_base; | |
68a64357 BH |
64 | extern unsigned long pci_io_base; |
65 | extern unsigned long pci_dram_offset; | |
66 | ||
25e81f92 BH |
67 | extern resource_size_t isa_mem_base; |
68 | ||
3fafe9c2 BH |
69 | /* Boolean set by platform if PIO accesses are suppored while _IO_BASE |
70 | * is not set or addresses cannot be translated to MMIO. This is typically | |
71 | * set when the platform supports "special" PIO accesses via a non memory | |
72 | * mapped mechanism, and allows things like the early udbg UART code to | |
73 | * function. | |
74 | */ | |
75 | extern bool isa_io_special; | |
76 | ||
ecd73cc5 BH |
77 | #ifdef CONFIG_PPC32 |
78 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) | |
79 | #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits | |
80 | #endif | |
68a64357 BH |
81 | #endif |
82 | ||
4cb3cee0 BH |
83 | /* |
84 | * | |
85 | * Low level MMIO accessors | |
86 | * | |
87 | * This provides the non-bus specific accessors to MMIO. Those are PowerPC | |
88 | * specific and thus shouldn't be used in generic code. The accessors | |
89 | * provided here are: | |
90 | * | |
91 | * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 | |
92 | * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 | |
93 | * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns | |
94 | * | |
95 | * Those operate directly on a kernel virtual address. Note that the prototype | |
96 | * for the out_* accessors has the arguments in opposite order from the usual | |
97 | * linux PCI accessors. Unlike those, they take the address first and the value | |
98 | * next. | |
99 | * | |
100 | * Note: I might drop the _ns suffix on the stream operations soon as it is | |
101 | * simply normal for stream operations to not swap in the first place. | |
102 | * | |
103 | */ | |
104 | ||
68a64357 | 105 | #ifdef CONFIG_PPC64 |
048c8bc9 | 106 | #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) |
68a64357 BH |
107 | #else |
108 | #define IO_SET_SYNC_FLAG() | |
109 | #endif | |
4cb3cee0 | 110 | |
0f3d6bcd TP |
111 | /* gcc 4.0 and older doesn't have 'Z' constraint */ |
112 | #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) | |
15cba23e | 113 | #define DEF_MMIO_IN_X(name, size, insn) \ |
0f3d6bcd | 114 | static inline u##size name(const volatile u##size __iomem *addr) \ |
4cb3cee0 | 115 | { \ |
0f3d6bcd TP |
116 | u##size ret; \ |
117 | __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ | |
cfab3bdf | 118 | : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ |
4cb3cee0 BH |
119 | return ret; \ |
120 | } | |
121 | ||
15cba23e | 122 | #define DEF_MMIO_OUT_X(name, size, insn) \ |
0f3d6bcd | 123 | static inline void name(volatile u##size __iomem *addr, u##size val) \ |
4cb3cee0 | 124 | { \ |
0f3d6bcd | 125 | __asm__ __volatile__("sync;"#insn" %1,0,%2" \ |
cfab3bdf BH |
126 | : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ |
127 | IO_SET_SYNC_FLAG(); \ | |
4cb3cee0 | 128 | } |
0f3d6bcd | 129 | #else /* newer gcc */ |
15cba23e | 130 | #define DEF_MMIO_IN_X(name, size, insn) \ |
0f3d6bcd TP |
131 | static inline u##size name(const volatile u##size __iomem *addr) \ |
132 | { \ | |
133 | u##size ret; \ | |
134 | __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ | |
135 | : "=r" (ret) : "Z" (*addr) : "memory"); \ | |
136 | return ret; \ | |
137 | } | |
138 | ||
15cba23e | 139 | #define DEF_MMIO_OUT_X(name, size, insn) \ |
0f3d6bcd TP |
140 | static inline void name(volatile u##size __iomem *addr, u##size val) \ |
141 | { \ | |
142 | __asm__ __volatile__("sync;"#insn" %1,%y0" \ | |
143 | : "=Z" (*addr) : "r" (val) : "memory"); \ | |
144 | IO_SET_SYNC_FLAG(); \ | |
145 | } | |
146 | #endif | |
4cb3cee0 | 147 | |
15cba23e | 148 | #define DEF_MMIO_IN_D(name, size, insn) \ |
0f3d6bcd TP |
149 | static inline u##size name(const volatile u##size __iomem *addr) \ |
150 | { \ | |
151 | u##size ret; \ | |
152 | __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ | |
153 | : "=r" (ret) : "m" (*addr) : "memory"); \ | |
154 | return ret; \ | |
155 | } | |
4cb3cee0 | 156 | |
15cba23e | 157 | #define DEF_MMIO_OUT_D(name, size, insn) \ |
0f3d6bcd TP |
158 | static inline void name(volatile u##size __iomem *addr, u##size val) \ |
159 | { \ | |
160 | __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ | |
161 | : "=m" (*addr) : "r" (val) : "memory"); \ | |
162 | IO_SET_SYNC_FLAG(); \ | |
163 | } | |
4cb3cee0 | 164 | |
15cba23e IM |
165 | DEF_MMIO_IN_D(in_8, 8, lbz); |
166 | DEF_MMIO_OUT_D(out_8, 8, stb); | |
4cb3cee0 | 167 | |
15cba23e IM |
168 | #ifdef __BIG_ENDIAN__ |
169 | DEF_MMIO_IN_D(in_be16, 16, lhz); | |
170 | DEF_MMIO_IN_D(in_be32, 32, lwz); | |
171 | DEF_MMIO_IN_X(in_le16, 16, lhbrx); | |
172 | DEF_MMIO_IN_X(in_le32, 32, lwbrx); | |
4cb3cee0 | 173 | |
15cba23e IM |
174 | DEF_MMIO_OUT_D(out_be16, 16, sth); |
175 | DEF_MMIO_OUT_D(out_be32, 32, stw); | |
176 | DEF_MMIO_OUT_X(out_le16, 16, sthbrx); | |
177 | DEF_MMIO_OUT_X(out_le32, 32, stwbrx); | |
178 | #else | |
179 | DEF_MMIO_IN_X(in_be16, 16, lhbrx); | |
180 | DEF_MMIO_IN_X(in_be32, 32, lwbrx); | |
181 | DEF_MMIO_IN_D(in_le16, 16, lhz); | |
182 | DEF_MMIO_IN_D(in_le32, 32, lwz); | |
183 | ||
184 | DEF_MMIO_OUT_X(out_be16, 16, sthbrx); | |
185 | DEF_MMIO_OUT_X(out_be32, 32, stwbrx); | |
186 | DEF_MMIO_OUT_D(out_le16, 16, sth); | |
187 | DEF_MMIO_OUT_D(out_le32, 32, stw); | |
188 | ||
189 | #endif /* __BIG_ENDIAN */ | |
4cb3cee0 | 190 | |
68a64357 | 191 | #ifdef __powerpc64__ |
15cba23e IM |
192 | |
193 | #ifdef __BIG_ENDIAN__ | |
194 | DEF_MMIO_OUT_D(out_be64, 64, std); | |
195 | DEF_MMIO_IN_D(in_be64, 64, ld); | |
68a64357 | 196 | |
4cb3cee0 BH |
197 | /* There is no asm instructions for 64 bits reverse loads and stores */ |
198 | static inline u64 in_le64(const volatile u64 __iomem *addr) | |
199 | { | |
bda76dd1 | 200 | return swab64(in_be64(addr)); |
4cb3cee0 BH |
201 | } |
202 | ||
203 | static inline void out_le64(volatile u64 __iomem *addr, u64 val) | |
204 | { | |
bda76dd1 | 205 | out_be64(addr, swab64(val)); |
4cb3cee0 | 206 | } |
15cba23e IM |
207 | #else |
208 | DEF_MMIO_OUT_D(out_le64, 64, std); | |
209 | DEF_MMIO_IN_D(in_le64, 64, ld); | |
210 | ||
211 | /* There is no asm instructions for 64 bits reverse loads and stores */ | |
212 | static inline u64 in_be64(const volatile u64 __iomem *addr) | |
213 | { | |
214 | return swab64(in_le64(addr)); | |
215 | } | |
216 | ||
217 | static inline void out_be64(volatile u64 __iomem *addr, u64 val) | |
218 | { | |
219 | out_le64(addr, swab64(val)); | |
220 | } | |
221 | ||
222 | #endif | |
68a64357 | 223 | #endif /* __powerpc64__ */ |
4cb3cee0 BH |
224 | |
225 | /* | |
226 | * Low level IO stream instructions are defined out of line for now | |
227 | */ | |
228 | extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); | |
229 | extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); | |
230 | extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); | |
231 | extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); | |
232 | extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); | |
233 | extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); | |
234 | ||
235 | /* The _ns naming is historical and will be removed. For now, just #define | |
236 | * the non _ns equivalent names | |
237 | */ | |
238 | #define _insw _insw_ns | |
239 | #define _insl _insl_ns | |
240 | #define _outsw _outsw_ns | |
241 | #define _outsl _outsl_ns | |
242 | ||
68a64357 BH |
243 | |
244 | /* | |
245 | * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line | |
246 | */ | |
247 | ||
248 | extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); | |
249 | extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, | |
250 | unsigned long n); | |
251 | extern void _memcpy_toio(volatile void __iomem *dest, const void *src, | |
252 | unsigned long n); | |
253 | ||
4cb3cee0 BH |
254 | /* |
255 | * | |
256 | * PCI and standard ISA accessors | |
257 | * | |
258 | * Those are globally defined linux accessors for devices on PCI or ISA | |
259 | * busses. They follow the Linux defined semantics. The current implementation | |
260 | * for PowerPC is as close as possible to the x86 version of these, and thus | |
261 | * provides fairly heavy weight barriers for the non-raw versions | |
262 | * | |
ecd73cc5 BH |
263 | * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO |
264 | * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its | |
265 | * own implementation of some or all of the accessors. | |
4cb3cee0 BH |
266 | */ |
267 | ||
68a64357 BH |
268 | /* |
269 | * Include the EEH definitions when EEH is enabled only so they don't get | |
270 | * in the way when building for 32 bits | |
271 | */ | |
272 | #ifdef CONFIG_EEH | |
4cb3cee0 | 273 | #include <asm/eeh.h> |
68a64357 | 274 | #endif |
4cb3cee0 BH |
275 | |
276 | /* Shortcut to the MMIO argument pointer */ | |
277 | #define PCI_IO_ADDR volatile void __iomem * | |
278 | ||
279 | /* Indirect IO address tokens: | |
280 | * | |
ecd73cc5 BH |
281 | * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks |
282 | * on all MMIOs. (Note that this is all 64 bits only for now) | |
4cb3cee0 | 283 | * |
446957ba | 284 | * To help platforms who may need to differentiate MMIO addresses in |
4cb3cee0 BH |
285 | * their hooks, a bitfield is reserved for use by the platform near the |
286 | * top of MMIO addresses (not PIO, those have to cope the hard way). | |
287 | * | |
288 | * This bit field is 12 bits and is at the top of the IO virtual | |
289 | * addresses PCI_IO_INDIRECT_TOKEN_MASK. | |
290 | * | |
291 | * The kernel virtual space is thus: | |
292 | * | |
293 | * 0xD000000000000000 : vmalloc | |
294 | * 0xD000080000000000 : PCI PHB IO space | |
295 | * 0xD000080080000000 : ioremap | |
296 | * 0xD0000fffffffffff : end of ioremap region | |
297 | * | |
298 | * Since the top 4 bits are reserved as the region ID, we use thus | |
299 | * the next 12 bits and keep 4 bits available for the future if the | |
300 | * virtual address space is ever to be extended. | |
301 | * | |
302 | * The direct IO mapping operations will then mask off those bits | |
303 | * before doing the actual access, though that only happen when | |
ecd73cc5 | 304 | * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that |
4cb3cee0 | 305 | * mechanism |
ecd73cc5 BH |
306 | * |
307 | * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes | |
308 | * all PIO functions call through a hook. | |
4cb3cee0 BH |
309 | */ |
310 | ||
ecd73cc5 | 311 | #ifdef CONFIG_PPC_INDIRECT_MMIO |
4cb3cee0 BH |
312 | #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul |
313 | #define PCI_IO_IND_TOKEN_SHIFT 48 | |
314 | #define PCI_FIX_ADDR(addr) \ | |
315 | ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) | |
316 | #define PCI_GET_ADDR_TOKEN(addr) \ | |
317 | (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ | |
318 | PCI_IO_IND_TOKEN_SHIFT) | |
319 | #define PCI_SET_ADDR_TOKEN(addr, token) \ | |
320 | do { \ | |
321 | unsigned long __a = (unsigned long)(addr); \ | |
322 | __a &= ~PCI_IO_IND_TOKEN_MASK; \ | |
323 | __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ | |
324 | (addr) = (void __iomem *)__a; \ | |
325 | } while(0) | |
326 | #else | |
327 | #define PCI_FIX_ADDR(addr) (addr) | |
328 | #endif | |
329 | ||
757db1ed BH |
330 | |
331 | /* | |
332 | * Non ordered and non-swapping "raw" accessors | |
333 | */ | |
334 | ||
335 | static inline unsigned char __raw_readb(const volatile void __iomem *addr) | |
336 | { | |
337 | return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); | |
338 | } | |
339 | static inline unsigned short __raw_readw(const volatile void __iomem *addr) | |
340 | { | |
341 | return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); | |
342 | } | |
343 | static inline unsigned int __raw_readl(const volatile void __iomem *addr) | |
344 | { | |
345 | return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); | |
346 | } | |
347 | static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) | |
348 | { | |
349 | *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; | |
350 | } | |
351 | static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) | |
352 | { | |
353 | *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; | |
354 | } | |
355 | static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) | |
356 | { | |
357 | *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; | |
358 | } | |
359 | ||
360 | #ifdef __powerpc64__ | |
361 | static inline unsigned long __raw_readq(const volatile void __iomem *addr) | |
362 | { | |
363 | return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); | |
364 | } | |
365 | static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) | |
366 | { | |
367 | *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; | |
368 | } | |
a84bf321 | 369 | |
8056fe28 ME |
370 | static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) |
371 | { | |
372 | __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); | |
373 | } | |
374 | ||
a84bf321 | 375 | /* |
d381d7ca BH |
376 | * Real mode versions of the above. Those instructions are only supposed |
377 | * to be used in hypervisor real mode as per the architecture spec. | |
a84bf321 | 378 | */ |
d381d7ca BH |
379 | static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) |
380 | { | |
381 | __asm__ __volatile__("stbcix %0,0,%1" | |
382 | : : "r" (val), "r" (paddr) : "memory"); | |
383 | } | |
384 | ||
385 | static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) | |
386 | { | |
387 | __asm__ __volatile__("sthcix %0,0,%1" | |
388 | : : "r" (val), "r" (paddr) : "memory"); | |
389 | } | |
390 | ||
391 | static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) | |
392 | { | |
393 | __asm__ __volatile__("stwcix %0,0,%1" | |
394 | : : "r" (val), "r" (paddr) : "memory"); | |
395 | } | |
396 | ||
a84bf321 AP |
397 | static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) |
398 | { | |
399 | __asm__ __volatile__("stdcix %0,0,%1" | |
400 | : : "r" (val), "r" (paddr) : "memory"); | |
401 | } | |
402 | ||
8056fe28 ME |
403 | static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) |
404 | { | |
405 | __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); | |
406 | } | |
407 | ||
d381d7ca BH |
408 | static inline u8 __raw_rm_readb(volatile void __iomem *paddr) |
409 | { | |
410 | u8 ret; | |
411 | __asm__ __volatile__("lbzcix %0,0, %1" | |
412 | : "=r" (ret) : "r" (paddr) : "memory"); | |
413 | return ret; | |
414 | } | |
415 | ||
416 | static inline u16 __raw_rm_readw(volatile void __iomem *paddr) | |
417 | { | |
418 | u16 ret; | |
419 | __asm__ __volatile__("lhzcix %0,0, %1" | |
420 | : "=r" (ret) : "r" (paddr) : "memory"); | |
421 | return ret; | |
422 | } | |
423 | ||
424 | static inline u32 __raw_rm_readl(volatile void __iomem *paddr) | |
425 | { | |
426 | u32 ret; | |
427 | __asm__ __volatile__("lwzcix %0,0, %1" | |
428 | : "=r" (ret) : "r" (paddr) : "memory"); | |
429 | return ret; | |
430 | } | |
431 | ||
432 | static inline u64 __raw_rm_readq(volatile void __iomem *paddr) | |
433 | { | |
434 | u64 ret; | |
435 | __asm__ __volatile__("ldcix %0,0, %1" | |
436 | : "=r" (ret) : "r" (paddr) : "memory"); | |
437 | return ret; | |
438 | } | |
757db1ed BH |
439 | #endif /* __powerpc64__ */ |
440 | ||
68a64357 | 441 | /* |
757db1ed BH |
442 | * |
443 | * PCI PIO and MMIO accessors. | |
444 | * | |
445 | * | |
68a64357 BH |
446 | * On 32 bits, PIO operations have a recovery mechanism in case they trigger |
447 | * machine checks (which they occasionally do when probing non existing | |
448 | * IO ports on some platforms, like PowerMac and 8xx). | |
449 | * I always found it to be of dubious reliability and I am tempted to get | |
450 | * rid of it one of these days. So if you think it's important to keep it, | |
451 | * please voice up asap. We never had it for 64 bits and I do not intend | |
452 | * to port it over | |
453 | */ | |
454 | ||
455 | #ifdef CONFIG_PPC32 | |
456 | ||
457 | #define __do_in_asm(name, op) \ | |
4cfbdfff | 458 | static inline unsigned int name(unsigned int port) \ |
68a64357 BH |
459 | { \ |
460 | unsigned int x; \ | |
461 | __asm__ __volatile__( \ | |
462 | "sync\n" \ | |
463 | "0:" op " %0,0,%1\n" \ | |
464 | "1: twi 0,%0,0\n" \ | |
465 | "2: isync\n" \ | |
466 | "3: nop\n" \ | |
467 | "4:\n" \ | |
468 | ".section .fixup,\"ax\"\n" \ | |
469 | "5: li %0,-1\n" \ | |
470 | " b 4b\n" \ | |
471 | ".previous\n" \ | |
24bfa6a9 NP |
472 | EX_TABLE(0b, 5b) \ |
473 | EX_TABLE(1b, 5b) \ | |
474 | EX_TABLE(2b, 5b) \ | |
475 | EX_TABLE(3b, 5b) \ | |
68a64357 | 476 | : "=&r" (x) \ |
cfab3bdf BH |
477 | : "r" (port + _IO_BASE) \ |
478 | : "memory"); \ | |
68a64357 BH |
479 | return x; \ |
480 | } | |
481 | ||
482 | #define __do_out_asm(name, op) \ | |
4cfbdfff | 483 | static inline void name(unsigned int val, unsigned int port) \ |
68a64357 BH |
484 | { \ |
485 | __asm__ __volatile__( \ | |
486 | "sync\n" \ | |
487 | "0:" op " %0,0,%1\n" \ | |
488 | "1: sync\n" \ | |
489 | "2:\n" \ | |
24bfa6a9 NP |
490 | EX_TABLE(0b, 2b) \ |
491 | EX_TABLE(1b, 2b) \ | |
cfab3bdf BH |
492 | : : "r" (val), "r" (port + _IO_BASE) \ |
493 | : "memory"); \ | |
68a64357 BH |
494 | } |
495 | ||
496 | __do_in_asm(_rec_inb, "lbzx") | |
497 | __do_in_asm(_rec_inw, "lhbrx") | |
498 | __do_in_asm(_rec_inl, "lwbrx") | |
499 | __do_out_asm(_rec_outb, "stbx") | |
500 | __do_out_asm(_rec_outw, "sthbrx") | |
501 | __do_out_asm(_rec_outl, "stwbrx") | |
502 | ||
503 | #endif /* CONFIG_PPC32 */ | |
504 | ||
4cb3cee0 | 505 | /* The "__do_*" operations below provide the actual "base" implementation |
42b2aa86 | 506 | * for each of the defined accessors. Some of them use the out_* functions |
4cb3cee0 BH |
507 | * directly, some of them still use EEH, though we might change that in the |
508 | * future. Those macros below provide the necessary argument swapping and | |
509 | * handling of the IO base for PIO. | |
510 | * | |
511 | * They are themselves used by the macros that define the actual accessors | |
512 | * and can be used by the hooks if any. | |
513 | * | |
514 | * Note that PIO operations are always defined in terms of their corresonding | |
515 | * MMIO operations. That allows platforms like iSeries who want to modify the | |
516 | * behaviour of both to only hook on the MMIO version and get both. It's also | |
517 | * possible to hook directly at the toplevel PIO operation if they have to | |
518 | * be handled differently | |
519 | */ | |
520 | #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) | |
521 | #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) | |
522 | #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) | |
523 | #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) | |
524 | #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) | |
525 | #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) | |
526 | #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) | |
68a64357 BH |
527 | |
528 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
529 | #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) |
530 | #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) | |
531 | #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) | |
532 | #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) | |
533 | #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) | |
534 | #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) | |
535 | #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) | |
68a64357 BH |
536 | #else /* CONFIG_EEH */ |
537 | #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) | |
538 | #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) | |
539 | #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) | |
540 | #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) | |
541 | #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) | |
542 | #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) | |
543 | #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) | |
544 | #endif /* !defined(CONFIG_EEH) */ | |
545 | ||
546 | #ifdef CONFIG_PPC32 | |
547 | #define __do_outb(val, port) _rec_outb(val, port) | |
548 | #define __do_outw(val, port) _rec_outw(val, port) | |
549 | #define __do_outl(val, port) _rec_outl(val, port) | |
550 | #define __do_inb(port) _rec_inb(port) | |
551 | #define __do_inw(port) _rec_inw(port) | |
552 | #define __do_inl(port) _rec_inl(port) | |
553 | #else /* CONFIG_PPC32 */ | |
554 | #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); | |
555 | #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); | |
556 | #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); | |
557 | #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); | |
558 | #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); | |
559 | #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); | |
560 | #endif /* !CONFIG_PPC32 */ | |
561 | ||
562 | #ifdef CONFIG_EEH | |
4cb3cee0 BH |
563 | #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) |
564 | #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) | |
565 | #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) | |
68a64357 BH |
566 | #else /* CONFIG_EEH */ |
567 | #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) | |
568 | #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) | |
569 | #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) | |
570 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 BH |
571 | #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) |
572 | #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) | |
573 | #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) | |
574 | ||
68a64357 BH |
575 | #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) |
576 | #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
577 | #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) | |
578 | #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
579 | #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
580 | #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) | |
581 | ||
582 | #define __do_memset_io(addr, c, n) \ | |
583 | _memset_io(PCI_FIX_ADDR(addr), c, n) | |
584 | #define __do_memcpy_toio(dst, src, n) \ | |
585 | _memcpy_toio(PCI_FIX_ADDR(dst), src, n) | |
586 | ||
587 | #ifdef CONFIG_EEH | |
588 | #define __do_memcpy_fromio(dst, src, n) \ | |
589 | eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) | |
590 | #else /* CONFIG_EEH */ | |
591 | #define __do_memcpy_fromio(dst, src, n) \ | |
592 | _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) | |
593 | #endif /* !CONFIG_EEH */ | |
4cb3cee0 | 594 | |
21176fed ME |
595 | #ifdef CONFIG_PPC_INDIRECT_PIO |
596 | #define DEF_PCI_HOOK_pio(x) x | |
597 | #else | |
598 | #define DEF_PCI_HOOK_pio(x) NULL | |
599 | #endif | |
600 | ||
601 | #ifdef CONFIG_PPC_INDIRECT_MMIO | |
602 | #define DEF_PCI_HOOK_mem(x) x | |
4cb3cee0 | 603 | #else |
21176fed | 604 | #define DEF_PCI_HOOK_mem(x) NULL |
4cb3cee0 BH |
605 | #endif |
606 | ||
607 | /* Structure containing all the hooks */ | |
608 | extern struct ppc_pci_io { | |
609 | ||
7cfb62a2 IK |
610 | #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; |
611 | #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; | |
4cb3cee0 BH |
612 | |
613 | #include <asm/io-defs.h> | |
614 | ||
615 | #undef DEF_PCI_AC_RET | |
616 | #undef DEF_PCI_AC_NORET | |
617 | ||
618 | } ppc_pci_io; | |
619 | ||
620 | /* The inline wrappers */ | |
7cfb62a2 | 621 | #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ |
4cb3cee0 BH |
622 | static inline ret name at \ |
623 | { \ | |
21176fed | 624 | if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ |
4cb3cee0 BH |
625 | return ppc_pci_io.name al; \ |
626 | return __do_##name al; \ | |
627 | } | |
628 | ||
7cfb62a2 | 629 | #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ |
4cb3cee0 BH |
630 | static inline void name at \ |
631 | { \ | |
21176fed | 632 | if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ |
4cb3cee0 BH |
633 | ppc_pci_io.name al; \ |
634 | else \ | |
635 | __do_##name al; \ | |
636 | } | |
637 | ||
638 | #include <asm/io-defs.h> | |
639 | ||
640 | #undef DEF_PCI_AC_RET | |
641 | #undef DEF_PCI_AC_NORET | |
642 | ||
643 | /* Some drivers check for the presence of readq & writeq with | |
644 | * a #ifdef, so we make them happy here. | |
645 | */ | |
68a64357 | 646 | #ifdef __powerpc64__ |
4cb3cee0 BH |
647 | #define readq readq |
648 | #define writeq writeq | |
68a64357 BH |
649 | #endif |
650 | ||
4cb3cee0 BH |
651 | /* |
652 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
653 | * access | |
654 | */ | |
655 | #define xlate_dev_mem_ptr(p) __va(p) | |
656 | ||
657 | /* | |
658 | * Convert a virtual cached pointer to an uncached pointer | |
659 | */ | |
660 | #define xlate_dev_kmem_ptr(p) p | |
caf81329 | 661 | |
4cb3cee0 BH |
662 | /* |
663 | * We don't do relaxed operations yet, at least not with this semantic | |
664 | */ | |
5da59057 WD |
665 | #define readb_relaxed(addr) readb(addr) |
666 | #define readw_relaxed(addr) readw(addr) | |
667 | #define readl_relaxed(addr) readl(addr) | |
668 | #define readq_relaxed(addr) readq(addr) | |
669 | #define writeb_relaxed(v, addr) writeb(v, addr) | |
670 | #define writew_relaxed(v, addr) writew(v, addr) | |
671 | #define writel_relaxed(v, addr) writel(v, addr) | |
672 | #define writeq_relaxed(v, addr) writeq(v, addr) | |
1da177e4 | 673 | |
ef237039 LG |
674 | #include <asm-generic/iomap.h> |
675 | ||
68a64357 BH |
676 | #ifdef CONFIG_PPC32 |
677 | #define mmiowb() | |
678 | #else | |
4cb3cee0 BH |
679 | /* |
680 | * Enforce synchronisation of stores vs. spin_unlock | |
c03983ac | 681 | * (this does it explicitly, though our implementation of spin_unlock |
4cb3cee0 BH |
682 | * does it implicitely too) |
683 | */ | |
f007cacf PM |
684 | static inline void mmiowb(void) |
685 | { | |
292f86f0 HD |
686 | unsigned long tmp; |
687 | ||
688 | __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" | |
689 | : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) | |
690 | : "memory"); | |
f007cacf | 691 | } |
68a64357 | 692 | #endif /* !CONFIG_PPC32 */ |
1da177e4 | 693 | |
4cb3cee0 BH |
694 | static inline void iosync(void) |
695 | { | |
696 | __asm__ __volatile__ ("sync" : : : "memory"); | |
697 | } | |
698 | ||
699 | /* Enforce in-order execution of data I/O. | |
700 | * No distinction between read/write on PPC; use eieio for all three. | |
701 | * Those are fairly week though. They don't provide a barrier between | |
702 | * MMIO and cacheable storage nor do they provide a barrier vs. locks, | |
703 | * they only provide barriers between 2 __raw MMIO operations and | |
704 | * possibly break write combining. | |
705 | */ | |
706 | #define iobarrier_rw() eieio() | |
707 | #define iobarrier_r() eieio() | |
708 | #define iobarrier_w() eieio() | |
709 | ||
710 | ||
1da177e4 LT |
711 | /* |
712 | * output pause versions need a delay at least for the | |
713 | * w83c105 ide controller in a p610. | |
714 | */ | |
715 | #define inb_p(port) inb(port) | |
716 | #define outb_p(val, port) (udelay(1), outb((val), (port))) | |
717 | #define inw_p(port) inw(port) | |
718 | #define outw_p(val, port) (udelay(1), outw((val), (port))) | |
719 | #define inl_p(port) inl(port) | |
720 | #define outl_p(val, port) (udelay(1), outl((val), (port))) | |
721 | ||
1da177e4 LT |
722 | |
723 | #define IO_SPACE_LIMIT ~(0UL) | |
724 | ||
725 | ||
1da177e4 LT |
726 | /** |
727 | * ioremap - map bus memory into CPU space | |
728 | * @address: bus address of the memory | |
729 | * @size: size of the resource to map | |
730 | * | |
731 | * ioremap performs a platform specific sequence of operations to | |
732 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
733 | * writew/writel functions and the other mmio helpers. The returned | |
734 | * address is not guaranteed to be usable directly as a virtual | |
735 | * address. | |
4cb3cee0 BH |
736 | * |
737 | * We provide a few variations of it: | |
738 | * | |
739 | * * ioremap is the standard one and provides non-cacheable guarded mappings | |
740 | * and can be hooked by the platform via ppc_md | |
741 | * | |
40f1ce7f AB |
742 | * * ioremap_prot allows to specify the page flags as an argument and can |
743 | * also be hooked by the platform via ppc_md. | |
4cb3cee0 BH |
744 | * |
745 | * * ioremap_nocache is identical to ioremap | |
746 | * | |
be135f40 AB |
747 | * * ioremap_wc enables write combining |
748 | * | |
4cb3cee0 BH |
749 | * * iounmap undoes such a mapping and can be hooked |
750 | * | |
3d5134ee BH |
751 | * * __ioremap_at (and the pending __iounmap_at) are low level functions to |
752 | * create hand-made mappings for use only by the PCI code and cannot | |
753 | * currently be hooked. Must be page aligned. | |
4cb3cee0 BH |
754 | * |
755 | * * __ioremap is the low level implementation used by ioremap and | |
40f1ce7f | 756 | * ioremap_prot and cannot be hooked (but can be used by a hook on one |
4cb3cee0 BH |
757 | * of the previous ones) |
758 | * | |
1cdab55d BH |
759 | * * __ioremap_caller is the same as above but takes an explicit caller |
760 | * reference rather than using __builtin_return_address(0) | |
761 | * | |
4cb3cee0 BH |
762 | * * __iounmap, is the low level implementation used by iounmap and cannot |
763 | * be hooked (but can be used by a hook on iounmap) | |
764 | * | |
1da177e4 | 765 | */ |
68a64357 | 766 | extern void __iomem *ioremap(phys_addr_t address, unsigned long size); |
40f1ce7f AB |
767 | extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, |
768 | unsigned long flags); | |
be135f40 | 769 | extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); |
1da177e4 | 770 | #define ioremap_nocache(addr, size) ioremap((addr), (size)) |
4c73e892 | 771 | #define ioremap_uc(addr, size) ioremap((addr), (size)) |
f855b2f5 OH |
772 | #define ioremap_cache(addr, size) \ |
773 | ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) | |
a1f242ff | 774 | |
68a64357 | 775 | extern void iounmap(volatile void __iomem *addr); |
4cb3cee0 | 776 | |
68a64357 | 777 | extern void __iomem *__ioremap(phys_addr_t, unsigned long size, |
4cb3cee0 | 778 | unsigned long flags); |
1cdab55d BH |
779 | extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, |
780 | unsigned long flags, void *caller); | |
781 | ||
68a64357 | 782 | extern void __iounmap(volatile void __iomem *addr); |
4cb3cee0 | 783 | |
3d5134ee BH |
784 | extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, |
785 | unsigned long size, unsigned long flags); | |
786 | extern void __iounmap_at(void *ea, unsigned long size); | |
1da177e4 | 787 | |
4cb3cee0 | 788 | /* |
ecd73cc5 | 789 | * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation |
4cb3cee0 BH |
790 | * which needs some additional definitions here. They basically allow PIO |
791 | * space overall to be 1GB. This will work as long as we never try to use | |
792 | * iomap to map MMIO below 1GB which should be fine on ppc64 | |
793 | */ | |
794 | #define HAVE_ARCH_PIO_SIZE 1 | |
795 | #define PIO_OFFSET 0x00000000UL | |
3d5134ee BH |
796 | #define PIO_MASK (FULL_IO_SIZE - 1) |
797 | #define PIO_RESERVED (FULL_IO_SIZE) | |
4cb3cee0 BH |
798 | |
799 | #define mmio_read16be(addr) readw_be(addr) | |
800 | #define mmio_read32be(addr) readl_be(addr) | |
801 | #define mmio_write16be(val, addr) writew_be(val, addr) | |
802 | #define mmio_write32be(val, addr) writel_be(val, addr) | |
803 | #define mmio_insb(addr, dst, count) readsb(addr, dst, count) | |
804 | #define mmio_insw(addr, dst, count) readsw(addr, dst, count) | |
805 | #define mmio_insl(addr, dst, count) readsl(addr, dst, count) | |
806 | #define mmio_outsb(addr, src, count) writesb(addr, src, count) | |
807 | #define mmio_outsw(addr, src, count) writesw(addr, src, count) | |
808 | #define mmio_outsl(addr, src, count) writesl(addr, src, count) | |
809 | ||
1da177e4 LT |
810 | /** |
811 | * virt_to_phys - map virtual addresses to physical | |
812 | * @address: address to remap | |
813 | * | |
814 | * The returned physical address is the physical (CPU) mapping for | |
815 | * the memory address given. It is only valid to use this function on | |
816 | * addresses directly mapped or allocated via kmalloc. | |
817 | * | |
818 | * This function does not give bus mappings for DMA transfers. In | |
819 | * almost all conceivable cases a device driver should not be using | |
820 | * this function | |
821 | */ | |
822 | static inline unsigned long virt_to_phys(volatile void * address) | |
823 | { | |
824 | return __pa((unsigned long)address); | |
825 | } | |
826 | ||
827 | /** | |
828 | * phys_to_virt - map physical address to virtual | |
829 | * @address: address to remap | |
830 | * | |
831 | * The returned virtual address is a current CPU mapping for | |
832 | * the memory address given. It is only valid to use this function on | |
833 | * addresses that have a kernel mapping | |
834 | * | |
835 | * This function does not handle bus mappings for DMA transfers. In | |
836 | * almost all conceivable cases a device driver should not be using | |
837 | * this function | |
838 | */ | |
839 | static inline void * phys_to_virt(unsigned long address) | |
840 | { | |
841 | return (void *)__va(address); | |
842 | } | |
843 | ||
844 | /* | |
845 | * Change "struct page" to physical address. | |
846 | */ | |
4ee7084e | 847 | #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) |
1da177e4 | 848 | |
68a64357 BH |
849 | /* |
850 | * 32 bits still uses virt_to_bus() for it's implementation of DMA | |
851 | * mappings se we have to keep it defined here. We also have some old | |
852 | * drivers (shame shame shame) that use bus_to_virt() and haven't been | |
853 | * fixed yet so I need to define it here. | |
854 | */ | |
855 | #ifdef CONFIG_PPC32 | |
856 | ||
857 | static inline unsigned long virt_to_bus(volatile void * address) | |
858 | { | |
859 | if (address == NULL) | |
860 | return 0; | |
861 | return __pa(address) + PCI_DRAM_OFFSET; | |
862 | } | |
863 | ||
864 | static inline void * bus_to_virt(unsigned long address) | |
865 | { | |
866 | if (address == 0) | |
867 | return NULL; | |
868 | return __va(address - PCI_DRAM_OFFSET); | |
869 | } | |
870 | ||
871 | #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) | |
872 | ||
873 | #endif /* CONFIG_PPC32 */ | |
874 | ||
5427828e VB |
875 | /* access ports */ |
876 | #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) | |
877 | #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) | |
878 | ||
879 | #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) | |
880 | #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) | |
68a64357 | 881 | |
12cdac34 SW |
882 | #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) |
883 | #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) | |
884 | ||
dc967d7f TT |
885 | /* Clear and set bits in one shot. These macros can be used to clear and |
886 | * set multiple bits in a register using a single read-modify-write. These | |
887 | * macros can also be used to set a multiple-bit bit pattern using a mask, | |
888 | * by specifying the mask in the 'clear' parameter and the new bit pattern | |
889 | * in the 'set' parameter. | |
890 | */ | |
891 | ||
892 | #define clrsetbits(type, addr, clear, set) \ | |
893 | out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) | |
894 | ||
895 | #ifdef __powerpc64__ | |
896 | #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) | |
897 | #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) | |
898 | #endif | |
899 | ||
900 | #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) | |
901 | #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) | |
902 | ||
903 | #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) | |
e2d75505 | 904 | #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) |
dc967d7f TT |
905 | |
906 | #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) | |
907 | ||
1da177e4 LT |
908 | #endif /* __KERNEL__ */ |
909 | ||
047ea784 | 910 | #endif /* _ASM_POWERPC_IO_H */ |