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8d2169e8 DG |
1 | #ifndef _ASM_POWERPC_MMU_HASH64_H_ |
2 | #define _ASM_POWERPC_MMU_HASH64_H_ | |
3 | /* | |
4 | * PowerPC64 memory management structures | |
5 | * | |
6 | * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> | |
7 | * PPC64 rework. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #include <asm/asm-compat.h> | |
16 | #include <asm/page.h> | |
17 | ||
78f1dbde AK |
18 | /* |
19 | * This is necessary to get the definition of PGTABLE_RANGE which we | |
20 | * need for various slices related matters. Note that this isn't the | |
21 | * complete pgtable.h but only a portion of it. | |
22 | */ | |
23 | #include <asm/pgtable-ppc64.h> | |
cf9427b8 | 24 | #include <asm/bug.h> |
dad6f37c | 25 | #include <asm/processor.h> |
78f1dbde | 26 | |
8d2169e8 DG |
27 | /* |
28 | * SLB | |
29 | */ | |
30 | ||
31 | #define SLB_NUM_BOLTED 3 | |
32 | #define SLB_CACHE_ENTRIES 8 | |
46db2f86 | 33 | #define SLB_MIN_SIZE 32 |
8d2169e8 DG |
34 | |
35 | /* Bits in the SLB ESID word */ | |
36 | #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ | |
37 | ||
38 | /* Bits in the SLB VSID word */ | |
39 | #define SLB_VSID_SHIFT 12 | |
1189be65 PM |
40 | #define SLB_VSID_SHIFT_1T 24 |
41 | #define SLB_VSID_SSIZE_SHIFT 62 | |
8d2169e8 DG |
42 | #define SLB_VSID_B ASM_CONST(0xc000000000000000) |
43 | #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) | |
44 | #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) | |
45 | #define SLB_VSID_KS ASM_CONST(0x0000000000000800) | |
46 | #define SLB_VSID_KP ASM_CONST(0x0000000000000400) | |
47 | #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ | |
48 | #define SLB_VSID_L ASM_CONST(0x0000000000000100) | |
49 | #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ | |
50 | #define SLB_VSID_LP ASM_CONST(0x0000000000000030) | |
51 | #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) | |
52 | #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) | |
53 | #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) | |
54 | #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) | |
55 | #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) | |
56 | ||
57 | #define SLB_VSID_KERNEL (SLB_VSID_KP) | |
58 | #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) | |
59 | ||
60 | #define SLBIE_C (0x08000000) | |
1189be65 | 61 | #define SLBIE_SSIZE_SHIFT 25 |
8d2169e8 DG |
62 | |
63 | /* | |
64 | * Hash table | |
65 | */ | |
66 | ||
67 | #define HPTES_PER_GROUP 8 | |
68 | ||
2454c7e9 | 69 | #define HPTE_V_SSIZE_SHIFT 62 |
8d2169e8 | 70 | #define HPTE_V_AVPN_SHIFT 7 |
2454c7e9 | 71 | #define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) |
8d2169e8 | 72 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) |
91bbbe22 | 73 | #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
8d2169e8 DG |
74 | #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
75 | #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) | |
76 | #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) | |
77 | #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) | |
78 | #define HPTE_V_VALID ASM_CONST(0x0000000000000001) | |
79 | ||
80 | #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) | |
81 | #define HPTE_R_TS ASM_CONST(0x4000000000000000) | |
de56a948 | 82 | #define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) |
8d2169e8 | 83 | #define HPTE_R_RPN_SHIFT 12 |
de56a948 | 84 | #define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) |
8d2169e8 DG |
85 | #define HPTE_R_PP ASM_CONST(0x0000000000000003) |
86 | #define HPTE_R_N ASM_CONST(0x0000000000000004) | |
de56a948 PM |
87 | #define HPTE_R_G ASM_CONST(0x0000000000000008) |
88 | #define HPTE_R_M ASM_CONST(0x0000000000000010) | |
89 | #define HPTE_R_I ASM_CONST(0x0000000000000020) | |
90 | #define HPTE_R_W ASM_CONST(0x0000000000000040) | |
91 | #define HPTE_R_WIMG ASM_CONST(0x0000000000000078) | |
8d2169e8 DG |
92 | #define HPTE_R_C ASM_CONST(0x0000000000000080) |
93 | #define HPTE_R_R ASM_CONST(0x0000000000000100) | |
de56a948 | 94 | #define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) |
8d2169e8 | 95 | |
b7abc5c5 SS |
96 | #define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) |
97 | #define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) | |
98 | ||
8d2169e8 | 99 | /* Values for PP (assumes Ks=0, Kp=1) */ |
8d2169e8 DG |
100 | #define PP_RWXX 0 /* Supervisor read/write, User none */ |
101 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | |
102 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | |
103 | #define PP_RXRX 3 /* Supervisor read, User read */ | |
697d3899 | 104 | #define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ |
8d2169e8 | 105 | |
b4072df4 PM |
106 | /* Fields for tlbiel instruction in architecture 2.06 */ |
107 | #define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ | |
108 | #define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ | |
109 | #define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ | |
110 | #define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ | |
111 | #define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ | |
112 | #define TLBIEL_INVAL_SET_SHIFT 12 | |
113 | ||
114 | #define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ | |
115 | ||
8d2169e8 DG |
116 | #ifndef __ASSEMBLY__ |
117 | ||
8e561e7e | 118 | struct hash_pte { |
12f04f2b AB |
119 | __be64 v; |
120 | __be64 r; | |
8e561e7e | 121 | }; |
8d2169e8 | 122 | |
8e561e7e | 123 | extern struct hash_pte *htab_address; |
8d2169e8 DG |
124 | extern unsigned long htab_size_bytes; |
125 | extern unsigned long htab_hash_mask; | |
126 | ||
127 | /* | |
128 | * Page size definition | |
129 | * | |
130 | * shift : is the "PAGE_SHIFT" value for that page size | |
131 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed | |
132 | * directly to a slbmte "vsid" value | |
133 | * penc : is the HPTE encoding mask for the "LP" field: | |
134 | * | |
135 | */ | |
136 | struct mmu_psize_def | |
137 | { | |
138 | unsigned int shift; /* number of bits */ | |
b1022fbd | 139 | int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ |
8d2169e8 DG |
140 | unsigned int tlbiel; /* tlbiel supported for that page size */ |
141 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ | |
142 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ | |
143 | }; | |
cf9427b8 AK |
144 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; |
145 | ||
146 | static inline int shift_to_mmu_psize(unsigned int shift) | |
147 | { | |
148 | int psize; | |
149 | ||
150 | for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) | |
151 | if (mmu_psize_defs[psize].shift == shift) | |
152 | return psize; | |
153 | return -1; | |
154 | } | |
155 | ||
156 | static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) | |
157 | { | |
158 | if (mmu_psize_defs[mmu_psize].shift) | |
159 | return mmu_psize_defs[mmu_psize].shift; | |
160 | BUG(); | |
161 | } | |
8d2169e8 DG |
162 | |
163 | #endif /* __ASSEMBLY__ */ | |
164 | ||
2454c7e9 PM |
165 | /* |
166 | * Segment sizes. | |
167 | * These are the values used by hardware in the B field of | |
168 | * SLB entries and the first dword of MMU hashtable entries. | |
169 | * The B field is 2 bits; the values 2 and 3 are unused and reserved. | |
170 | */ | |
171 | #define MMU_SEGSIZE_256M 0 | |
172 | #define MMU_SEGSIZE_1T 1 | |
173 | ||
5524a27d AK |
174 | /* |
175 | * encode page number shift. | |
176 | * in order to fit the 78 bit va in a 64 bit variable we shift the va by | |
177 | * 12 bits. This enable us to address upto 76 bit va. | |
178 | * For hpt hash from a va we can ignore the page size bits of va and for | |
179 | * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure | |
180 | * we work in all cases including 4k page size. | |
181 | */ | |
182 | #define VPN_SHIFT 12 | |
1189be65 | 183 | |
b1022fbd AK |
184 | /* |
185 | * HPTE Large Page (LP) details | |
186 | */ | |
187 | #define LP_SHIFT 12 | |
188 | #define LP_BITS 8 | |
189 | #define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) | |
190 | ||
8d2169e8 DG |
191 | #ifndef __ASSEMBLY__ |
192 | ||
73d16a6e IM |
193 | static inline int slb_vsid_shift(int ssize) |
194 | { | |
195 | if (ssize == MMU_SEGSIZE_256M) | |
196 | return SLB_VSID_SHIFT; | |
197 | return SLB_VSID_SHIFT_1T; | |
198 | } | |
199 | ||
5524a27d AK |
200 | static inline int segment_shift(int ssize) |
201 | { | |
202 | if (ssize == MMU_SEGSIZE_256M) | |
203 | return SID_SHIFT; | |
204 | return SID_SHIFT_1T; | |
205 | } | |
206 | ||
8d2169e8 | 207 | /* |
1189be65 | 208 | * The current system page and segment sizes |
8d2169e8 | 209 | */ |
8d2169e8 DG |
210 | extern int mmu_linear_psize; |
211 | extern int mmu_virtual_psize; | |
212 | extern int mmu_vmalloc_psize; | |
cec08e7a | 213 | extern int mmu_vmemmap_psize; |
8d2169e8 | 214 | extern int mmu_io_psize; |
1189be65 PM |
215 | extern int mmu_kernel_ssize; |
216 | extern int mmu_highuser_ssize; | |
584f8b71 | 217 | extern u16 mmu_slb_size; |
572fb578 | 218 | extern unsigned long tce_alloc_start, tce_alloc_end; |
8d2169e8 DG |
219 | |
220 | /* | |
221 | * If the processor supports 64k normal pages but not 64k cache | |
222 | * inhibited pages, we have to be prepared to switch processes | |
223 | * to use 4k pages when they create cache-inhibited mappings. | |
224 | * If this is the case, mmu_ci_restrictions will be set to 1. | |
225 | */ | |
226 | extern int mmu_ci_restrictions; | |
227 | ||
5524a27d AK |
228 | /* |
229 | * This computes the AVPN and B fields of the first dword of a HPTE, | |
230 | * for use when we want to match an existing PTE. The bottom 7 bits | |
231 | * of the returned value are zero. | |
232 | */ | |
233 | static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, | |
234 | int ssize) | |
235 | { | |
236 | unsigned long v; | |
237 | /* | |
238 | * The AVA field omits the low-order 23 bits of the 78 bits VA. | |
239 | * These bits are not needed in the PTE, because the | |
240 | * low-order b of these bits are part of the byte offset | |
241 | * into the virtual page and, if b < 23, the high-order | |
242 | * 23-b of these bits are always used in selecting the | |
243 | * PTEGs to be searched | |
244 | */ | |
245 | v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); | |
246 | v <<= HPTE_V_AVPN_SHIFT; | |
247 | v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; | |
248 | return v; | |
249 | } | |
250 | ||
8d2169e8 DG |
251 | /* |
252 | * This function sets the AVPN and L fields of the HPTE appropriately | |
b1022fbd | 253 | * using the base page size and actual page size. |
8d2169e8 | 254 | */ |
b1022fbd AK |
255 | static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, |
256 | int actual_psize, int ssize) | |
8d2169e8 | 257 | { |
1189be65 | 258 | unsigned long v; |
b1022fbd AK |
259 | v = hpte_encode_avpn(vpn, base_psize, ssize); |
260 | if (actual_psize != MMU_PAGE_4K) | |
8d2169e8 DG |
261 | v |= HPTE_V_LARGE; |
262 | return v; | |
263 | } | |
264 | ||
265 | /* | |
266 | * This function sets the ARPN, and LP fields of the HPTE appropriately | |
267 | * for the page size. We assume the pa is already "clean" that is properly | |
268 | * aligned for the requested page size | |
269 | */ | |
b1022fbd AK |
270 | static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, |
271 | int actual_psize) | |
8d2169e8 | 272 | { |
8d2169e8 | 273 | /* A 4K page needs no special encoding */ |
b1022fbd | 274 | if (actual_psize == MMU_PAGE_4K) |
8d2169e8 DG |
275 | return pa & HPTE_R_RPN; |
276 | else { | |
b1022fbd AK |
277 | unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; |
278 | unsigned int shift = mmu_psize_defs[actual_psize].shift; | |
279 | return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); | |
8d2169e8 | 280 | } |
8d2169e8 DG |
281 | } |
282 | ||
283 | /* | |
5524a27d | 284 | * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. |
8d2169e8 | 285 | */ |
5524a27d AK |
286 | static inline unsigned long hpt_vpn(unsigned long ea, |
287 | unsigned long vsid, int ssize) | |
1189be65 | 288 | { |
5524a27d AK |
289 | unsigned long mask; |
290 | int s_shift = segment_shift(ssize); | |
291 | ||
292 | mask = (1ul << (s_shift - VPN_SHIFT)) - 1; | |
293 | return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); | |
1189be65 | 294 | } |
8d2169e8 | 295 | |
1189be65 PM |
296 | /* |
297 | * This hashes a virtual address | |
298 | */ | |
5524a27d AK |
299 | static inline unsigned long hpt_hash(unsigned long vpn, |
300 | unsigned int shift, int ssize) | |
8d2169e8 | 301 | { |
5524a27d | 302 | int mask; |
1189be65 PM |
303 | unsigned long hash, vsid; |
304 | ||
5524a27d | 305 | /* VPN_SHIFT can be atmost 12 */ |
1189be65 | 306 | if (ssize == MMU_SEGSIZE_256M) { |
5524a27d AK |
307 | mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; |
308 | hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ | |
309 | ((vpn & mask) >> (shift - VPN_SHIFT)); | |
1189be65 | 310 | } else { |
5524a27d AK |
311 | mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; |
312 | vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); | |
313 | hash = vsid ^ (vsid << 25) ^ | |
314 | ((vpn & mask) >> (shift - VPN_SHIFT)) ; | |
1189be65 PM |
315 | } |
316 | return hash & 0x7fffffffffUL; | |
8d2169e8 DG |
317 | } |
318 | ||
aefa5688 AK |
319 | #define HPTE_LOCAL_UPDATE 0x1 |
320 | #define HPTE_NOHPTE_UPDATE 0x2 | |
321 | ||
8d2169e8 DG |
322 | extern int __hash_page_4K(unsigned long ea, unsigned long access, |
323 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 324 | unsigned long flags, int ssize, int subpage_prot); |
8d2169e8 DG |
325 | extern int __hash_page_64K(unsigned long ea, unsigned long access, |
326 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
aefa5688 | 327 | unsigned long flags, int ssize); |
8d2169e8 | 328 | struct mm_struct; |
0895ecda | 329 | unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); |
aefa5688 AK |
330 | extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
331 | unsigned long access, unsigned long trap, | |
332 | unsigned long flags); | |
333 | extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, | |
334 | unsigned long dsisr); | |
a4fe3ce7 | 335 | int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, |
aefa5688 AK |
336 | pte_t *ptep, unsigned long trap, unsigned long flags, |
337 | int ssize, unsigned int shift, unsigned int mmu_psize); | |
6d492ecc AK |
338 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
339 | extern int __hash_page_thp(unsigned long ea, unsigned long access, | |
340 | unsigned long vsid, pmd_t *pmdp, unsigned long trap, | |
aefa5688 | 341 | unsigned long flags, int ssize, unsigned int psize); |
6d492ecc AK |
342 | #else |
343 | static inline int __hash_page_thp(unsigned long ea, unsigned long access, | |
344 | unsigned long vsid, pmd_t *pmdp, | |
aefa5688 | 345 | unsigned long trap, unsigned long flags, |
6d492ecc AK |
346 | int ssize, unsigned int psize) |
347 | { | |
348 | BUG(); | |
ff1e7683 | 349 | return -1; |
6d492ecc AK |
350 | } |
351 | #endif | |
4b8692c0 BH |
352 | extern void hash_failure_debug(unsigned long ea, unsigned long access, |
353 | unsigned long vsid, unsigned long trap, | |
d8139ebf AK |
354 | int ssize, int psize, int lpsize, |
355 | unsigned long pte); | |
8d2169e8 | 356 | extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, |
bc033b63 | 357 | unsigned long pstart, unsigned long prot, |
1189be65 | 358 | int psize, int ssize); |
f6026df1 AB |
359 | int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
360 | int psize, int ssize); | |
41151e77 | 361 | extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); |
fa28237c | 362 | extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); |
8d2169e8 | 363 | |
8d2169e8 DG |
364 | extern void hpte_init_native(void); |
365 | extern void hpte_init_lpar(void); | |
8d2169e8 | 366 | extern void hpte_init_beat(void); |
7f2c8577 | 367 | extern void hpte_init_beat_v3(void); |
8d2169e8 | 368 | |
8d2169e8 DG |
369 | extern void slb_initialize(void); |
370 | extern void slb_flush_and_rebolt(void); | |
8d2169e8 | 371 | |
67439b76 | 372 | extern void slb_vmalloc_update(void); |
46db2f86 | 373 | extern void slb_set_size(u16 size); |
8d2169e8 DG |
374 | #endif /* __ASSEMBLY__ */ |
375 | ||
376 | /* | |
f033d659 | 377 | * VSID allocation (256MB segment) |
8d2169e8 | 378 | * |
c60ac569 AK |
379 | * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated |
380 | * from mmu context id and effective segment id of the address. | |
8d2169e8 | 381 | * |
c60ac569 AK |
382 | * For user processes max context id is limited to ((1ul << 19) - 5) |
383 | * for kernel space, we use the top 4 context ids to map address as below | |
384 | * NOTE: each context only support 64TB now. | |
385 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
386 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
387 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
388 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
8d2169e8 DG |
389 | * |
390 | * The proto-VSIDs are then scrambled into real VSIDs with the | |
391 | * multiplicative hash: | |
392 | * | |
393 | * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS | |
8d2169e8 | 394 | * |
f033d659 | 395 | * VSID_MULTIPLIER is prime, so in particular it is |
8d2169e8 DG |
396 | * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. |
397 | * Because the modulus is 2^n-1 we can compute it efficiently without | |
c60ac569 AK |
398 | * a divide or extra multiply (see below). The scramble function gives |
399 | * robust scattering in the hash table (at least based on some initial | |
400 | * results). | |
8d2169e8 | 401 | * |
c60ac569 AK |
402 | * We also consider VSID 0 special. We use VSID 0 for slb entries mapping |
403 | * bad address. This enables us to consolidate bad address handling in | |
404 | * hash_page. | |
8d2169e8 | 405 | * |
c60ac569 AK |
406 | * We also need to avoid the last segment of the last context, because that |
407 | * would give a protovsid of 0x1fffffffff. That will result in a VSID 0 | |
408 | * because of the modulo operation in vsid scramble. But the vmemmap | |
409 | * (which is what uses region 0xf) will never be close to 64TB in size | |
410 | * (it's 56 bytes per page of system memory). | |
8d2169e8 | 411 | */ |
8d2169e8 | 412 | |
e39d1a47 | 413 | #define CONTEXT_BITS 19 |
af81d787 AK |
414 | #define ESID_BITS 18 |
415 | #define ESID_BITS_1T 6 | |
e39d1a47 | 416 | |
c60ac569 AK |
417 | /* |
418 | * 256MB segment | |
af81d787 | 419 | * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments |
c60ac569 AK |
420 | * available for user + kernel mapping. The top 4 contexts are used for |
421 | * kernel mapping. Each segment contains 2^28 bytes. Each | |
422 | * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts | |
423 | * (19 == 37 + 28 - 46). | |
424 | */ | |
425 | #define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5) | |
426 | ||
048ee099 AK |
427 | /* |
428 | * This should be computed such that protovosid * vsid_mulitplier | |
429 | * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus | |
430 | */ | |
431 | #define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ | |
af81d787 | 432 | #define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS) |
1189be65 | 433 | #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1) |
8d2169e8 | 434 | |
1189be65 | 435 | #define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ |
af81d787 | 436 | #define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T) |
1189be65 PM |
437 | #define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1) |
438 | ||
8d2169e8 | 439 | |
af81d787 | 440 | #define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) |
8d2169e8 DG |
441 | |
442 | /* | |
443 | * This macro generates asm code to compute the VSID scramble | |
444 | * function. Used in slb_allocate() and do_stab_bolted. The function | |
445 | * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS | |
446 | * | |
447 | * rt = register continaing the proto-VSID and into which the | |
448 | * VSID will be stored | |
449 | * rx = scratch register (clobbered) | |
450 | * | |
451 | * - rt and rx must be different registers | |
1189be65 | 452 | * - The answer will end up in the low VSID_BITS bits of rt. The higher |
8d2169e8 DG |
453 | * bits may contain other garbage, so you may need to mask the |
454 | * result. | |
455 | */ | |
1189be65 PM |
456 | #define ASM_VSID_SCRAMBLE(rt, rx, size) \ |
457 | lis rx,VSID_MULTIPLIER_##size@h; \ | |
458 | ori rx,rx,VSID_MULTIPLIER_##size@l; \ | |
8d2169e8 DG |
459 | mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ |
460 | \ | |
1189be65 PM |
461 | srdi rx,rt,VSID_BITS_##size; \ |
462 | clrldi rt,rt,(64-VSID_BITS_##size); \ | |
8d2169e8 | 463 | add rt,rt,rx; /* add high and low bits */ \ |
c60ac569 AK |
464 | /* NOTE: explanation based on VSID_BITS_##size = 36 \ |
465 | * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ | |
8d2169e8 DG |
466 | * 2^36-1+2^28-1. That in particular means that if r3 >= \ |
467 | * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ | |
468 | * the bit clear, r3 already has the answer we want, if it \ | |
469 | * doesn't, the answer is the low 36 bits of r3+1. So in all \ | |
470 | * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ | |
471 | addi rx,rt,1; \ | |
1189be65 | 472 | srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \ |
8d2169e8 DG |
473 | add rt,rt,rx |
474 | ||
78f1dbde AK |
475 | /* 4 bits per slice and we have one slice per 1TB */ |
476 | #define SLICE_ARRAY_SIZE (PGTABLE_RANGE >> 41) | |
8d2169e8 DG |
477 | |
478 | #ifndef __ASSEMBLY__ | |
479 | ||
d28513bc DG |
480 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
481 | /* | |
482 | * For the sub-page protection option, we extend the PGD with one of | |
483 | * these. Basically we have a 3-level tree, with the top level being | |
484 | * the protptrs array. To optimize speed and memory consumption when | |
485 | * only addresses < 4GB are being protected, pointers to the first | |
486 | * four pages of sub-page protection words are stored in the low_prot | |
487 | * array. | |
488 | * Each page of sub-page protection words protects 1GB (4 bytes | |
489 | * protects 64k). For the 3-level tree, each page of pointers then | |
490 | * protects 8TB. | |
491 | */ | |
492 | struct subpage_prot_table { | |
493 | unsigned long maxaddr; /* only addresses < this are protected */ | |
dad6f37c | 494 | unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; |
d28513bc DG |
495 | unsigned int *low_prot[4]; |
496 | }; | |
497 | ||
498 | #define SBP_L1_BITS (PAGE_SHIFT - 2) | |
499 | #define SBP_L2_BITS (PAGE_SHIFT - 3) | |
500 | #define SBP_L1_COUNT (1 << SBP_L1_BITS) | |
501 | #define SBP_L2_COUNT (1 << SBP_L2_BITS) | |
502 | #define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) | |
503 | #define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) | |
504 | ||
505 | extern void subpage_prot_free(struct mm_struct *mm); | |
506 | extern void subpage_prot_init_new_context(struct mm_struct *mm); | |
507 | #else | |
508 | static inline void subpage_prot_free(struct mm_struct *mm) {} | |
509 | static inline void subpage_prot_init_new_context(struct mm_struct *mm) { } | |
510 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
511 | ||
8d2169e8 | 512 | typedef unsigned long mm_context_id_t; |
851d2e2f | 513 | struct spinlock; |
8d2169e8 DG |
514 | |
515 | typedef struct { | |
516 | mm_context_id_t id; | |
d0f13e3c BH |
517 | u16 user_psize; /* page size index */ |
518 | ||
519 | #ifdef CONFIG_PPC_MM_SLICES | |
520 | u64 low_slices_psize; /* SLB page size encodings */ | |
78f1dbde | 521 | unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; |
d0f13e3c BH |
522 | #else |
523 | u16 sllp; /* SLB page size encoding */ | |
8d2169e8 DG |
524 | #endif |
525 | unsigned long vdso_base; | |
d28513bc DG |
526 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
527 | struct subpage_prot_table spt; | |
528 | #endif /* CONFIG_PPC_SUBPAGE_PROT */ | |
851d2e2f THFL |
529 | #ifdef CONFIG_PPC_ICSWX |
530 | struct spinlock *cop_lockp; /* guard acop and cop_pid */ | |
531 | unsigned long acop; /* mask of enabled coprocessor types */ | |
532 | unsigned int cop_pid; /* pid value used with coprocessors */ | |
533 | #endif /* CONFIG_PPC_ICSWX */ | |
5c1f6ee9 AK |
534 | #ifdef CONFIG_PPC_64K_PAGES |
535 | /* for 4K PTE fragment support */ | |
536 | void *pte_frag; | |
537 | #endif | |
8d2169e8 DG |
538 | } mm_context_t; |
539 | ||
540 | ||
8d2169e8 | 541 | #if 0 |
1189be65 PM |
542 | /* |
543 | * The code below is equivalent to this function for arguments | |
544 | * < 2^VSID_BITS, which is all this should ever be called | |
545 | * with. However gcc is not clever enough to compute the | |
546 | * modulus (2^n-1) without a second multiply. | |
547 | */ | |
34692708 | 548 | #define vsid_scramble(protovsid, size) \ |
1189be65 | 549 | ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) |
8d2169e8 | 550 | |
1189be65 PM |
551 | #else /* 1 */ |
552 | #define vsid_scramble(protovsid, size) \ | |
553 | ({ \ | |
554 | unsigned long x; \ | |
555 | x = (protovsid) * VSID_MULTIPLIER_##size; \ | |
556 | x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ | |
557 | (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ | |
558 | }) | |
8d2169e8 | 559 | #endif /* 1 */ |
8d2169e8 | 560 | |
1189be65 PM |
561 | /* Returns the segment size indicator for a user address */ |
562 | static inline int user_segment_size(unsigned long addr) | |
8d2169e8 | 563 | { |
1189be65 PM |
564 | /* Use 1T segments if possible for addresses >= 1T */ |
565 | if (addr >= (1UL << SID_SHIFT_1T)) | |
566 | return mmu_highuser_ssize; | |
567 | return MMU_SEGSIZE_256M; | |
8d2169e8 DG |
568 | } |
569 | ||
1189be65 PM |
570 | static inline unsigned long get_vsid(unsigned long context, unsigned long ea, |
571 | int ssize) | |
572 | { | |
c60ac569 AK |
573 | /* |
574 | * Bad address. We return VSID 0 for that | |
575 | */ | |
576 | if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) | |
577 | return 0; | |
578 | ||
1189be65 | 579 | if (ssize == MMU_SEGSIZE_256M) |
af81d787 | 580 | return vsid_scramble((context << ESID_BITS) |
1189be65 | 581 | | (ea >> SID_SHIFT), 256M); |
af81d787 | 582 | return vsid_scramble((context << ESID_BITS_1T) |
1189be65 PM |
583 | | (ea >> SID_SHIFT_1T), 1T); |
584 | } | |
585 | ||
c60ac569 AK |
586 | /* |
587 | * This is only valid for addresses >= PAGE_OFFSET | |
588 | * | |
589 | * For kernel space, we use the top 4 context ids to map address as below | |
590 | * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ] | |
591 | * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ] | |
592 | * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ] | |
593 | * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ] | |
594 | */ | |
595 | static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) | |
596 | { | |
597 | unsigned long context; | |
598 | ||
599 | /* | |
600 | * kernel take the top 4 context from the available range | |
601 | */ | |
602 | context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1; | |
603 | return get_vsid(context, ea, ssize); | |
604 | } | |
8d2169e8 DG |
605 | #endif /* __ASSEMBLY__ */ |
606 | ||
607 | #endif /* _ASM_POWERPC_MMU_HASH64_H_ */ |