[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / include / asm / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>

/*
 * MMU features bit definitions
 */

/*
 * First half is MMU families
 */
#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_3E			ASM_CONST(0x00000020)
#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000040)

/*
 * This is individual features
 */

/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)

/* Enable >32-bit physical addresses on 32-bit processor, only used
 * by CONFIG_6xx currently as BookE supports that from day 1
 */
#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)

/* Enable use of broadcast TLB invalidations. We don't always set it
 * on processors that support it due to other constraints with the
 * use of such invalidations
 */
#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)

/* Enable use of tlbilx invalidate instructions.
 */
#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)

/* This indicates that the processor cannot handle multiple outstanding
 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
 * around such invalidate forms.
 */
#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)

/* This indicates that the processor doesn't handle way selection
 * properly and needs SW to track and update the LRU state.  This
 * is specific to an errata on e300c2/c3/c4 class parts
 */
#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)

/* This indicates that the processor uses the ISA 2.06 server tlbie
 * mnemonics
 */
#define MMU_FTR_TLBIE_206		ASM_CONST(0x00400000)

/* Enable use of TLB reservation.  Processor should support tlbsrx.
 * instruction and MAS0[WQ].
 */
#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)

/* Use paired MAS registers (MAS7||MAS3, etc.)
 */
#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

#ifndef __ASSEMBLY__
#include <asm/cputable.h>

static inline int mmu_has_feature(unsigned long feature)
{
	return (cur_cpu_spec->mmu_features & feature);
}

extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;

/* MMU initialization (64-bit only fo now) */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);

#endif /* !__ASSEMBLY__ */

/* The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 *
 * Note: This array ended up being a false good idea as it's growing to the
 * point where I wonder if we should replace it with something different,
 * to think about, feedback welcome. --BenH.
 */

/* There are #define as they have to be used in assembly
 *
 * WARNING: If you change this list, make sure to update the array of
 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
 * happen
 */
#define MMU_PAGE_4K	0
#define MMU_PAGE_16K	1
#define MMU_PAGE_64K	2
#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K	4
#define MMU_PAGE_1M	5
#define MMU_PAGE_8M	6
#define MMU_PAGE_16M	7
#define MMU_PAGE_256M	8
#define MMU_PAGE_1G	9
#define MMU_PAGE_16G	10
#define MMU_PAGE_64G	11
#define MMU_PAGE_COUNT	12


#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */
#  include <asm/mmu-hash64.h>
#elif defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#  include <asm/mmu-hash32.h>
#elif defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#  include <asm/mmu-40x.h>
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#  include <asm/mmu-44x.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#  include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
#  include <asm/mmu-8xx.h>
#endif


#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
047ea784 PM	2	#define _ASM_POWERPC_MMU_H_
88ced031	3	#ifdef __KERNEL__
047ea784	4
7c03d653 BH	5	#include <asm/asm-compat.h>
	6	#include <asm/feature-fixups.h>
	7
	8	/*
	9	* MMU features bit definitions
	10	*/
	11
	12	/*
	13	* First half is MMU families
	14	*/
	15	#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
	16	#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
	17	#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
	18	#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
	19	#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
57e2a99f	20	#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
e7f75ad0	21	#define MMU_FTR_TYPE_47x ASM_CONST(0x00000040)
7c03d653 BH	22
	23	/*
	24	* This is individual features
	25	*/
	26
	27	/* Enable use of high BAT registers */
	28	#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
	29
	30	/* Enable >32-bit physical addresses on 32-bit processor, only used
	31	* by CONFIG_6xx currently as BookE supports that from day 1
	32	*/
	33	#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
	34
f048aace BH	35	/* Enable use of broadcast TLB invalidations. We don't always set it
	36	* on processors that support it due to other constraints with the
	37	* use of such invalidations
	38	*/
	39	#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
	40
c3071951	41	/* Enable use of tlbilx invalidate instructions.
f048aace	42	*/
c3071951	43	#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
f048aace BH	44
	45	/* This indicates that the processor cannot handle multiple outstanding
	46	* broadcast tlbivax or tlbsync. This makes the code use a spinlock
	47	* around such invalidate forms.
	48	*/
	49	#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
	50
2319f123 KG	51	/* This indicates that the processor doesn't handle way selection
	52	* properly and needs SW to track and update the LRU state. This
	53	* is specific to an errata on e300c2/c3/c4 class parts
	54	*/
	55	#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
	56
60dbf438 MM	57	/* This indicates that the processor uses the ISA 2.06 server tlbie
	58	* mnemonics
	59	*/
	60	#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
	61
df5d6ecf KG	62	/* Enable use of TLB reservation. Processor should support tlbsrx.
	63	* instruction and MAS0[WQ].
	64	*/
	65	#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
	66
	67	/* Use paired MAS registers (MAS7\|\|MAS3, etc.)
	68	*/
	69	#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
	70
7c03d653 BH	71	#ifndef __ASSEMBLY__
	72	#include <asm/cputable.h>
	73
	74	static inline int mmu_has_feature(unsigned long feature)
	75	{
	76	return (cur_cpu_spec->mmu_features & feature);
	77	}
	78
	79	extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
	80
757c74d2 BH	81	/* MMU initialization (64-bit only fo now) */
	82	extern void early_init_mmu(void);
	83	extern void early_init_mmu_secondary(void);
	84
7c03d653 BH	85	#endif /* !__ASSEMBLY__ */
7c03d653 BH	86
57e2a99f BH	87	/* The kernel use the constants below to index in the page sizes array.
	88	* The use of fixed constants for this purpose is better for performances
	89	* of the low level hash refill handlers.
	90	*
	91	* A non supported page size has a "shift" field set to 0
	92	*
	93	* Any new page size being implemented can get a new entry in here. Whether
	94	* the kernel will use it or not is a different matter though. The actual page
	95	* size used by hugetlbfs is not defined here and may be made variable
	96	*
	97	* Note: This array ended up being a false good idea as it's growing to the
	98	* point where I wonder if we should replace it with something different,
	99	* to think about, feedback welcome. --BenH.
	100	*/
	101
	102	/* There are #define as they have to be used in assembly
	103	*
	104	* WARNING: If you change this list, make sure to update the array of
	105	* names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
	106	* happen
	107	*/
	108	#define MMU_PAGE_4K 0
	109	#define MMU_PAGE_16K 1
	110	#define MMU_PAGE_64K 2
	111	#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
	112	#define MMU_PAGE_256K 4
	113	#define MMU_PAGE_1M 5
	114	#define MMU_PAGE_8M 6
	115	#define MMU_PAGE_16M 7
	116	#define MMU_PAGE_256M 8
	117	#define MMU_PAGE_1G 9
	118	#define MMU_PAGE_16G 10
	119	#define MMU_PAGE_64G 11
	120	#define MMU_PAGE_COUNT 12
	121
7c03d653	122
94491685	123	#if defined(CONFIG_PPC_STD_MMU_64)
8d2169e8 DG	124	/* 64-bit classic hash table MMU */
8d2169e8 DG	125	# include <asm/mmu-hash64.h>
94491685	126	#elif defined(CONFIG_PPC_STD_MMU_32)
4db68bfe DG	127	/* 32-bit classic hash table MMU */
4db68bfe DG	128	# include <asm/mmu-hash32.h>
4d922c8d JB	129	#elif defined(CONFIG_40x)
	130	/* 40x-style software loaded TLB */
	131	# include <asm/mmu-40x.h>
57d7909e DG	132	#elif defined(CONFIG_44x)
	133	/* 44x-style software loaded TLB */
	134	# include <asm/mmu-44x.h>
70fe3af8 KG	135	#elif defined(CONFIG_PPC_BOOK3E_MMU)
	136	/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
	137	# include <asm/mmu-book3e.h>
31202345 DG	138	#elif defined (CONFIG_PPC_8xx)
	139	/* Motorola/Freescale 8xx software loaded TLB */
	140	# include <asm/mmu-8xx.h>
1f8d419e	141	#endif
1f8d419e	142
57e2a99f	143
88ced031	144	#endif /* __KERNEL__ */
047ea784	145	#endif /* _ASM_POWERPC_MMU_H_ */