[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / include / asm / mpic.h

#ifndef _ASM_POWERPC_MPIC_H
#define _ASM_POWERPC_MPIC_H
#ifdef __KERNEL__

#include <linux/irq.h>
#include <asm/dcr.h>
#include <asm/msi_bitmap.h>

/*
 * Global registers
 */

#define MPIC_GREG_BASE			0x01000

#define MPIC_GREG_FEATURE_0		0x00000
#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
#define MPIC_GREG_FEATURE_1		0x00010
#define MPIC_GREG_GLOBAL_CONF_0		0x00020
#define		MPIC_GREG_GCONF_RESET			0x80000000
/* On the FSL mpic implementations the Mode field is expand to be
 * 2 bits wide:
 *	0b00 = pass through (interrupts routed to IRQ0)
 *	0b01 = Mixed mode
 *	0b10 = reserved
 *	0b11 = External proxy / coreint
 */
#define		MPIC_GREG_GCONF_COREINT			0x60000000
#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
#define		MPIC_GREG_GCONF_NO_BIAS			0x10000000
#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
#define		MPIC_GREG_GCONF_MCK			0x08000000
#define MPIC_GREG_GLOBAL_CONF_1		0x00030
#define		MPIC_GREG_GLOBAL_CONF_1_SIE		0x08000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK	0x70000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)	\
			(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
#define MPIC_GREG_VENDOR_0		0x00040
#define MPIC_GREG_VENDOR_1		0x00050
#define MPIC_GREG_VENDOR_2		0x00060
#define MPIC_GREG_VENDOR_3		0x00070
#define MPIC_GREG_VENDOR_ID		0x00080
#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
#define MPIC_GREG_PROCESSOR_INIT	0x00090
#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
#define MPIC_GREG_IPI_STRIDE		0x10
#define MPIC_GREG_SPURIOUS		0x000e0
#define MPIC_GREG_TIMER_FREQ		0x000f0

/*
 *
 * Timer registers
 */
#define MPIC_TIMER_BASE			0x01100
#define MPIC_TIMER_STRIDE		0x40

#define MPIC_TIMER_CURRENT_CNT		0x00000
#define MPIC_TIMER_BASE_CNT		0x00010
#define MPIC_TIMER_VECTOR_PRI		0x00020
#define MPIC_TIMER_DESTINATION		0x00030

/*
 * Per-Processor registers
 */

#define MPIC_CPU_THISBASE		0x00000
#define MPIC_CPU_BASE			0x20000
#define MPIC_CPU_STRIDE			0x01000

#define MPIC_CPU_IPI_DISPATCH_0		0x00040
#define MPIC_CPU_IPI_DISPATCH_1		0x00050
#define MPIC_CPU_IPI_DISPATCH_2		0x00060
#define MPIC_CPU_IPI_DISPATCH_3		0x00070
#define MPIC_CPU_IPI_DISPATCH_STRIDE	0x00010
#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
#define MPIC_CPU_WHOAMI			0x00090
#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
#define MPIC_CPU_INTACK			0x000a0
#define MPIC_CPU_EOI			0x000b0
#define MPIC_CPU_MCACK			0x000c0

/*
 * Per-source registers
 */

#define MPIC_IRQ_BASE			0x10000
#define MPIC_IRQ_STRIDE			0x00020
#define MPIC_IRQ_VECTOR_PRI		0x00000
#define 	MPIC_VECPRI_MASK			0x80000000
#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
#define MPIC_IRQ_DESTINATION		0x00010

#define MPIC_MAX_IRQ_SOURCES	2048
#define MPIC_MAX_CPUS		32
#define MPIC_MAX_ISU		32

/*
 * Tsi108 implementation of MPIC has many differences from the original one
 */

/*
 * Global registers
 */

#define TSI108_GREG_BASE		0x00000
#define TSI108_GREG_FEATURE_0		0x00000
#define TSI108_GREG_GLOBAL_CONF_0	0x00004
#define TSI108_GREG_VENDOR_ID		0x0000c
#define TSI108_GREG_IPI_VECTOR_PRI_0	0x00204		/* Doorbell 0 */
#define TSI108_GREG_IPI_STRIDE		0x0c
#define TSI108_GREG_SPURIOUS		0x00010
#define TSI108_GREG_TIMER_FREQ		0x00014

/*
 * Timer registers
 */
#define TSI108_TIMER_BASE		0x0030
#define TSI108_TIMER_STRIDE		0x10
#define TSI108_TIMER_CURRENT_CNT	0x00000
#define TSI108_TIMER_BASE_CNT		0x00004
#define TSI108_TIMER_VECTOR_PRI		0x00008
#define TSI108_TIMER_DESTINATION	0x0000c

/*
 * Per-Processor registers
 */
#define TSI108_CPU_BASE			0x00300
#define TSI108_CPU_STRIDE		0x00040
#define TSI108_CPU_IPI_DISPATCH_0	0x00200
#define TSI108_CPU_IPI_DISPATCH_STRIDE	0x00000
#define TSI108_CPU_CURRENT_TASK_PRI	0x00000
#define TSI108_CPU_WHOAMI		0xffffffff
#define TSI108_CPU_INTACK		0x00004
#define TSI108_CPU_EOI			0x00008
#define TSI108_CPU_MCACK		0x00004 /* Doesn't really exist here */

/*
 * Per-source registers
 */
#define TSI108_IRQ_BASE			0x00100
#define TSI108_IRQ_STRIDE		0x00008
#define TSI108_IRQ_VECTOR_PRI		0x00000
#define TSI108_VECPRI_VECTOR_MASK	0x000000ff
#define TSI108_VECPRI_POLARITY_POSITIVE	0x01000000
#define TSI108_VECPRI_POLARITY_NEGATIVE	0x00000000
#define TSI108_VECPRI_SENSE_LEVEL	0x02000000
#define TSI108_VECPRI_SENSE_EDGE	0x00000000
#define TSI108_VECPRI_POLARITY_MASK	0x01000000
#define TSI108_VECPRI_SENSE_MASK	0x02000000
#define TSI108_IRQ_DESTINATION		0x00004

/* weird mpic register indices and mask bits in the HW info array */
enum {
	MPIC_IDX_GREG_BASE = 0,
	MPIC_IDX_GREG_FEATURE_0,
	MPIC_IDX_GREG_GLOBAL_CONF_0,
	MPIC_IDX_GREG_VENDOR_ID,
	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	MPIC_IDX_GREG_IPI_STRIDE,
	MPIC_IDX_GREG_SPURIOUS,
	MPIC_IDX_GREG_TIMER_FREQ,

	MPIC_IDX_TIMER_BASE,
	MPIC_IDX_TIMER_STRIDE,
	MPIC_IDX_TIMER_CURRENT_CNT,
	MPIC_IDX_TIMER_BASE_CNT,
	MPIC_IDX_TIMER_VECTOR_PRI,
	MPIC_IDX_TIMER_DESTINATION,

	MPIC_IDX_CPU_BASE,
	MPIC_IDX_CPU_STRIDE,
	MPIC_IDX_CPU_IPI_DISPATCH_0,
	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
	MPIC_IDX_CPU_CURRENT_TASK_PRI,
	MPIC_IDX_CPU_WHOAMI,
	MPIC_IDX_CPU_INTACK,
	MPIC_IDX_CPU_EOI,
	MPIC_IDX_CPU_MCACK,

	MPIC_IDX_IRQ_BASE,
	MPIC_IDX_IRQ_STRIDE,
	MPIC_IDX_IRQ_VECTOR_PRI,

	MPIC_IDX_VECPRI_VECTOR_MASK,
	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
	MPIC_IDX_VECPRI_SENSE_LEVEL,
	MPIC_IDX_VECPRI_SENSE_EDGE,
	MPIC_IDX_VECPRI_POLARITY_MASK,
	MPIC_IDX_VECPRI_SENSE_MASK,
	MPIC_IDX_IRQ_DESTINATION,
	MPIC_IDX_END
};


#ifdef CONFIG_MPIC_U3_HT_IRQS
/* Fixup table entry */
struct mpic_irq_fixup
{
	u8 __iomem	*base;
	u8 __iomem	*applebase;
	u32		data;
	unsigned int	index;
};
#endif /* CONFIG_MPIC_U3_HT_IRQS */


enum mpic_reg_type {
	mpic_access_mmio_le,
	mpic_access_mmio_be,
#ifdef CONFIG_PPC_DCR
	mpic_access_dcr
#endif
};

struct mpic_reg_bank {
	u32 __iomem	*base;
#ifdef CONFIG_PPC_DCR
	dcr_host_t	dhost;
#endif /* CONFIG_PPC_DCR */
};

struct mpic_irq_save {
	u32		vecprio,
			dest;
#ifdef CONFIG_MPIC_U3_HT_IRQS
	u32		fixup_data;
#endif
};

/* The instance data of a given MPIC */
struct mpic
{
	/* The OpenFirmware dt node for this MPIC */
	struct device_node *node;

	/* The remapper for this MPIC */
	struct irq_host		*irqhost;

	/* The "linux" controller struct */
	struct irq_chip		hc_irq;
#ifdef CONFIG_MPIC_U3_HT_IRQS
	struct irq_chip		hc_ht_irq;
#endif
#ifdef CONFIG_SMP
	struct irq_chip		hc_ipi;
#endif
	struct irq_chip		hc_tm;
	const char		*name;
	/* Flags */
	unsigned int		flags;
	/* How many irq sources in a given ISU */
	unsigned int		isu_size;
	unsigned int		isu_shift;
	unsigned int		isu_mask;
	unsigned int		irq_count;
	/* Number of sources */
	unsigned int		num_sources;
	/* default senses array */
	unsigned char		*senses;
	unsigned int		senses_count;

	/* vector numbers used for internal sources (ipi/timers) */
	unsigned int		ipi_vecs[4];
	unsigned int		timer_vecs[8];

	/* Spurious vector to program into unused sources */
	unsigned int		spurious_vec;

#ifdef CONFIG_MPIC_U3_HT_IRQS
	/* The fixup table */
	struct mpic_irq_fixup	*fixups;
	raw_spinlock_t	fixup_lock;
#endif

	/* Register access method */
	enum mpic_reg_type	reg_type;

	/* The physical base address of the MPIC */
	phys_addr_t paddr;

	/* The various ioremap'ed bases */
	struct mpic_reg_bank	gregs;
	struct mpic_reg_bank	tmregs;
	struct mpic_reg_bank	cpuregs[MPIC_MAX_CPUS];
	struct mpic_reg_bank	isus[MPIC_MAX_ISU];

	/* Protected sources */
	unsigned long		*protected;

#ifdef CONFIG_MPIC_WEIRD
	/* Pointer to HW info array */
	u32			*hw_set;
#endif

#ifdef CONFIG_PCI_MSI
	struct msi_bitmap	msi_bitmap;
#endif

#ifdef CONFIG_MPIC_BROKEN_REGREAD
	u32			isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
#endif

	/* link */
	struct mpic		*next;

#ifdef CONFIG_PM
	struct mpic_irq_save	*save_data;
#endif
};

/*
 * MPIC flags (passed to mpic_alloc)
 *
 * The top 4 bits contain an MPIC bhw id that is used to index the
 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 * Note setting any ID (leaving those bits to 0) means standard MPIC
 */

/*
 * This is a secondary ("chained") controller; it only uses the CPU0
 * registers.  Primary controllers have IPIs and affinity control.
 */
#define MPIC_SECONDARY			0x00000001

/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN			0x00000002
/* Broken U3 MPIC */
#define MPIC_U3_HT_IRQS			0x00000004
/* Broken IPI registers (autodetected) */
#define MPIC_BROKEN_IPI			0x00000008
/* MPIC wants a reset */
#define MPIC_WANTS_RESET		0x00000010
/* Spurious vector requires EOI */
#define MPIC_SPV_EOI			0x00000020
/* No passthrough disable */
#define MPIC_NO_PTHROU_DIS		0x00000040
/* DCR based MPIC */
#define MPIC_USES_DCR			0x00000080
/* MPIC has 11-bit vector fields (or larger) */
#define MPIC_LARGE_VECTORS		0x00000100
/* Enable delivery of prio 15 interrupts as MCK instead of EE */
#define MPIC_ENABLE_MCK			0x00000200
/* Disable bias among target selection, spread interrupts evenly */
#define MPIC_NO_BIAS			0x00000400
/* Ignore NIRQS as reported by FRR */
#define MPIC_BROKEN_FRR_NIRQS		0x00000800
/* Destination only supports a single CPU at a time */
#define MPIC_SINGLE_DEST_CPU		0x00001000
/* Enable CoreInt delivery of interrupts */
#define MPIC_ENABLE_COREINT		0x00002000
/* Disable resetting of the MPIC.
 * NOTE: This flag trumps MPIC_WANTS_RESET.
 */
#define MPIC_NO_RESET			0x00004000
/* Freescale MPIC (compatible includes "fsl,mpic") */
#define MPIC_FSL			0x00008000

/* MPIC HW modification ID */
#define MPIC_REGSET_MASK		0xf0000000
#define MPIC_REGSET(val)		(((val) & 0xf ) << 28)
#define MPIC_GET_REGSET(flags)		(((flags) >> 28) & 0xf)

#define	MPIC_REGSET_STANDARD		MPIC_REGSET(0)	/* Original MPIC */
#define	MPIC_REGSET_TSI108		MPIC_REGSET(1)	/* Tsi108/109 PIC */

/* Allocate the controller structure and setup the linux irq descs
 * for the range if interrupts passed in. No HW initialization is
 * actually performed.
 * 
 * @phys_addr:	physial base address of the MPIC
 * @flags:	flags, see constants above
 * @isu_size:	number of interrupts in an ISU. Use 0 to use a
 *              standard ISU-less setup (aka powermac)
 * @irq_offset: first irq number to assign to this mpic
 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 *	        to match the number of sources
 * @ipi_offset: first irq number to assign to this mpic IPI sources,
 *		used only on primary mpic
 * @senses:	array of sense values
 * @senses_num: number of entries in the array
 *
 * Note about the sense array. If none is passed, all interrupts are
 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
 * case they are edge positive (and the array is ignored anyway).
 * The values in the array start at the first source of the MPIC,
 * that is senses[0] correspond to linux irq "irq_offset".
 */
extern struct mpic *mpic_alloc(struct device_node *node,
			       phys_addr_t phys_addr,
			       unsigned int flags,
			       unsigned int isu_size,
			       unsigned int irq_count,
			       const char *name);

/* Assign ISUs, to call before mpic_init()
 *
 * @mpic:	controller structure as returned by mpic_alloc()
 * @isu_num:	ISU number
 * @phys_addr:	physical address of the ISU
 */
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
			    phys_addr_t phys_addr);

/* Set default sense codes
 *
 * @mpic:	controller
 * @senses:	array of sense codes
 * @count:	size of above array
 *
 * Optionally provide an array (indexed on hardware interrupt numbers
 * for this MPIC) of default sense codes for the chip. Those are linux
 * sense codes IRQ_TYPE_*
 *
 * The driver gets ownership of the pointer, don't dispose of it or
 * anything like that. __init only.
 */
extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);


/* Initialize the controller. After this has been called, none of the above
 * should be called again for this mpic
 */
extern void mpic_init(struct mpic *mpic);

/*
 * All of the following functions must only be used after the
 * ISUs have been assigned and the controller fully initialized
 * with mpic_init()
 */


/* Change the priority of an interrupt. Default is 8 for irqs and
 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 */
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);

/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

/* Clean up for kexec (or cpu offline or ...) */
extern void mpic_teardown_this_cpu(int secondary);

/* Get the current cpu priority for this cpu (0..15) */
extern int mpic_cpu_get_priority(void);

/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);

/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);

/* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg);

/* Unmask a specific virq */
extern void mpic_unmask_irq(struct irq_data *d);
/* Mask a specific virq */
extern void mpic_mask_irq(struct irq_data *d);
/* EOI a specific virq */
extern void mpic_end_irq(struct irq_data *d);

/* Fetch interrupt from a given mpic */
extern unsigned int mpic_get_one_irq(struct mpic *mpic);
/* This one gets from the primary mpic */
extern unsigned int mpic_get_irq(void);
/* This one gets from the primary mpic via CoreInt*/
extern unsigned int mpic_get_coreint_irq(void);
/* Fetch Machine Check interrupt from primary mpic */
extern unsigned int mpic_get_mcirq(void);

/* Set the EPIC clock ratio */
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);

/* Enable/Disable EPIC serial interrupt mode */
void mpic_set_serial_int(struct mpic *mpic, int enable);

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_MPIC_H */
Commit	Line	Data
bbeb3f4c SR	1	#ifndef _ASM_POWERPC_MPIC_H
bbeb3f4c SR	2	#define _ASM_POWERPC_MPIC_H
88ced031	3	#ifdef __KERNEL__
bbeb3f4c	4
14cf11af	5	#include <linux/irq.h>
fbf0274e	6	#include <asm/dcr.h>
25235f71	7	#include <asm/msi_bitmap.h>
14cf11af PM	8
	9	/*
	10	* Global registers
	11	*/
	12
	13	#define MPIC_GREG_BASE 0x01000
	14
	15	#define MPIC_GREG_FEATURE_0 0x00000
	16	#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
	17	#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
	18	#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
	19	#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
	20	#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
	21	#define MPIC_GREG_FEATURE_1 0x00010
	22	#define MPIC_GREG_GLOBAL_CONF_0 0x00020
	23	#define MPIC_GREG_GCONF_RESET 0x80000000
d91e4ea7 KG	24	/* On the FSL mpic implementations the Mode field is expand to be
	25	* 2 bits wide:
	26	* 0b00 = pass through (interrupts routed to IRQ0)
	27	* 0b01 = Mixed mode
	28	* 0b10 = reserved
	29	* 0b11 = External proxy / coreint
	30	*/
	31	#define MPIC_GREG_GCONF_COREINT 0x60000000
14cf11af	32	#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
d87bf3be	33	#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
14cf11af	34	#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
f365355e	35	#define MPIC_GREG_GCONF_MCK 0x08000000
14cf11af	36	#define MPIC_GREG_GLOBAL_CONF_1 0x00030
868ea0c9 MG	37	#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
	38	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
	39	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
	40	(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
14cf11af PM	41	#define MPIC_GREG_VENDOR_0 0x00040
	42	#define MPIC_GREG_VENDOR_1 0x00050
	43	#define MPIC_GREG_VENDOR_2 0x00060
	44	#define MPIC_GREG_VENDOR_3 0x00070
	45	#define MPIC_GREG_VENDOR_ID 0x00080
	46	#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
	47	#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
	48	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
	49	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
	50	#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
	51	#define MPIC_GREG_PROCESSOR_INIT 0x00090
	52	#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
	53	#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
	54	#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
	55	#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
7233593b	56	#define MPIC_GREG_IPI_STRIDE 0x10
14cf11af PM	57	#define MPIC_GREG_SPURIOUS 0x000e0
	58	#define MPIC_GREG_TIMER_FREQ 0x000f0
	59
	60	/*
	61	*
	62	* Timer registers
	63	*/
	64	#define MPIC_TIMER_BASE 0x01100
	65	#define MPIC_TIMER_STRIDE 0x40
	66
	67	#define MPIC_TIMER_CURRENT_CNT 0x00000
	68	#define MPIC_TIMER_BASE_CNT 0x00010
	69	#define MPIC_TIMER_VECTOR_PRI 0x00020
	70	#define MPIC_TIMER_DESTINATION 0x00030
	71
	72	/*
	73	* Per-Processor registers
	74	*/
	75
	76	#define MPIC_CPU_THISBASE 0x00000
	77	#define MPIC_CPU_BASE 0x20000
	78	#define MPIC_CPU_STRIDE 0x01000
	79
	80	#define MPIC_CPU_IPI_DISPATCH_0 0x00040
	81	#define MPIC_CPU_IPI_DISPATCH_1 0x00050
	82	#define MPIC_CPU_IPI_DISPATCH_2 0x00060
	83	#define MPIC_CPU_IPI_DISPATCH_3 0x00070
7233593b	84	#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
14cf11af PM	85	#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
	86	#define MPIC_CPU_TASKPRI_MASK 0x0000000f
	87	#define MPIC_CPU_WHOAMI 0x00090
	88	#define MPIC_CPU_WHOAMI_MASK 0x0000001f
	89	#define MPIC_CPU_INTACK 0x000a0
	90	#define MPIC_CPU_EOI 0x000b0
f365355e	91	#define MPIC_CPU_MCACK 0x000c0
14cf11af PM	92
	93	/*
	94	* Per-source registers
	95	*/
	96
	97	#define MPIC_IRQ_BASE 0x10000
	98	#define MPIC_IRQ_STRIDE 0x00020
	99	#define MPIC_IRQ_VECTOR_PRI 0x00000
	100	#define MPIC_VECPRI_MASK 0x80000000
	101	#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
	102	#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
	103	#define MPIC_VECPRI_PRIORITY_SHIFT 16
	104	#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
	105	#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
	106	#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
	107	#define MPIC_VECPRI_POLARITY_MASK 0x00800000
	108	#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
	109	#define MPIC_VECPRI_SENSE_EDGE 0x00000000
	110	#define MPIC_VECPRI_SENSE_MASK 0x00400000
	111	#define MPIC_IRQ_DESTINATION 0x00010
	112
	113	#define MPIC_MAX_IRQ_SOURCES 2048
	114	#define MPIC_MAX_CPUS 32
	115	#define MPIC_MAX_ISU 32
	116
7233593b ZR	117	/*
	118	* Tsi108 implementation of MPIC has many differences from the original one
	119	*/
	120
	121	/*
	122	* Global registers
	123	*/
	124
	125	#define TSI108_GREG_BASE 0x00000
	126	#define TSI108_GREG_FEATURE_0 0x00000
	127	#define TSI108_GREG_GLOBAL_CONF_0 0x00004
	128	#define TSI108_GREG_VENDOR_ID 0x0000c
	129	#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
	130	#define TSI108_GREG_IPI_STRIDE 0x0c
	131	#define TSI108_GREG_SPURIOUS 0x00010
	132	#define TSI108_GREG_TIMER_FREQ 0x00014
	133
	134	/*
	135	* Timer registers
	136	*/
	137	#define TSI108_TIMER_BASE 0x0030
	138	#define TSI108_TIMER_STRIDE 0x10
	139	#define TSI108_TIMER_CURRENT_CNT 0x00000
	140	#define TSI108_TIMER_BASE_CNT 0x00004
	141	#define TSI108_TIMER_VECTOR_PRI 0x00008
	142	#define TSI108_TIMER_DESTINATION 0x0000c
	143
	144	/*
	145	* Per-Processor registers
	146	*/
	147	#define TSI108_CPU_BASE 0x00300
	148	#define TSI108_CPU_STRIDE 0x00040
	149	#define TSI108_CPU_IPI_DISPATCH_0 0x00200
	150	#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
	151	#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
	152	#define TSI108_CPU_WHOAMI 0xffffffff
	153	#define TSI108_CPU_INTACK 0x00004
	154	#define TSI108_CPU_EOI 0x00008
f365355e	155	#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
7233593b ZR	156
	157	/*
	158	* Per-source registers
	159	*/
	160	#define TSI108_IRQ_BASE 0x00100
	161	#define TSI108_IRQ_STRIDE 0x00008
	162	#define TSI108_IRQ_VECTOR_PRI 0x00000
	163	#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
	164	#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
	165	#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
	166	#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
	167	#define TSI108_VECPRI_SENSE_EDGE 0x00000000
	168	#define TSI108_VECPRI_POLARITY_MASK 0x01000000
	169	#define TSI108_VECPRI_SENSE_MASK 0x02000000
	170	#define TSI108_IRQ_DESTINATION 0x00004
	171
	172	/* weird mpic register indices and mask bits in the HW info array */
	173	enum {
	174	MPIC_IDX_GREG_BASE = 0,
	175	MPIC_IDX_GREG_FEATURE_0,
	176	MPIC_IDX_GREG_GLOBAL_CONF_0,
	177	MPIC_IDX_GREG_VENDOR_ID,
	178	MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
	179	MPIC_IDX_GREG_IPI_STRIDE,
	180	MPIC_IDX_GREG_SPURIOUS,
	181	MPIC_IDX_GREG_TIMER_FREQ,
	182
	183	MPIC_IDX_TIMER_BASE,
	184	MPIC_IDX_TIMER_STRIDE,
	185	MPIC_IDX_TIMER_CURRENT_CNT,
	186	MPIC_IDX_TIMER_BASE_CNT,
	187	MPIC_IDX_TIMER_VECTOR_PRI,
	188	MPIC_IDX_TIMER_DESTINATION,
	189
	190	MPIC_IDX_CPU_BASE,
	191	MPIC_IDX_CPU_STRIDE,
	192	MPIC_IDX_CPU_IPI_DISPATCH_0,
	193	MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
	194	MPIC_IDX_CPU_CURRENT_TASK_PRI,
	195	MPIC_IDX_CPU_WHOAMI,
	196	MPIC_IDX_CPU_INTACK,
	197	MPIC_IDX_CPU_EOI,
f365355e	198	MPIC_IDX_CPU_MCACK,
7233593b ZR	199
	200	MPIC_IDX_IRQ_BASE,
	201	MPIC_IDX_IRQ_STRIDE,
	202	MPIC_IDX_IRQ_VECTOR_PRI,
	203
	204	MPIC_IDX_VECPRI_VECTOR_MASK,
	205	MPIC_IDX_VECPRI_POLARITY_POSITIVE,
	206	MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
	207	MPIC_IDX_VECPRI_SENSE_LEVEL,
	208	MPIC_IDX_VECPRI_SENSE_EDGE,
	209	MPIC_IDX_VECPRI_POLARITY_MASK,
	210	MPIC_IDX_VECPRI_SENSE_MASK,
	211	MPIC_IDX_IRQ_DESTINATION,
	212	MPIC_IDX_END
	213	};
	214
	215
6cfef5b2	216	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	217	/* Fixup table entry */
	218	struct mpic_irq_fixup
	219	{
	220	u8 __iomem *base;
1beb6a7d	221	u8 __iomem *applebase;
c4b22f26	222	u32 data;
1beb6a7d	223	unsigned int index;
14cf11af	224	};
6cfef5b2	225	#endif /* CONFIG_MPIC_U3_HT_IRQS */
14cf11af PM	226
14cf11af PM	227
fbf0274e BH	228	enum mpic_reg_type {
	229	mpic_access_mmio_le,
	230	mpic_access_mmio_be,
	231	#ifdef CONFIG_PPC_DCR
	232	mpic_access_dcr
	233	#endif
	234	};
	235
	236	struct mpic_reg_bank {
	237	u32 __iomem *base;
	238	#ifdef CONFIG_PPC_DCR
	239	dcr_host_t dhost;
fbf0274e BH	240	#endif /* CONFIG_PPC_DCR */
	241	};
	242
3669e930 JB	243	struct mpic_irq_save {
	244	u32 vecprio,
	245	dest;
	246	#ifdef CONFIG_MPIC_U3_HT_IRQS
	247	u32 fixup_data;
	248	#endif
	249	};
	250
14cf11af PM	251	/* The instance data of a given MPIC */
	252	struct mpic
	253	{
c51242e7 KM	254	/* The OpenFirmware dt node for this MPIC */
	255	struct device_node *node;
	256
0ebfff14 BH	257	/* The remapper for this MPIC */
	258	struct irq_host *irqhost;
	259
14cf11af	260	/* The "linux" controller struct */
b9e5b4e6	261	struct irq_chip hc_irq;
6cfef5b2	262	#ifdef CONFIG_MPIC_U3_HT_IRQS
b9e5b4e6 BH	263	struct irq_chip hc_ht_irq;
b9e5b4e6 BH	264	#endif
14cf11af	265	#ifdef CONFIG_SMP
b9e5b4e6	266	struct irq_chip hc_ipi;
14cf11af	267	#endif
ea94187f	268	struct irq_chip hc_tm;
14cf11af PM	269	const char *name;
	270	/* Flags */
	271	unsigned int flags;
	272	/* How many irq sources in a given ISU */
	273	unsigned int isu_size;
	274	unsigned int isu_shift;
	275	unsigned int isu_mask;
14cf11af	276	unsigned int irq_count;
14cf11af PM	277	/* Number of sources */
14cf11af PM	278	unsigned int num_sources;
0ebfff14	279	/* default senses array */
14cf11af PM	280	unsigned char *senses;
	281	unsigned int senses_count;
	282
7df2457d OJ	283	/* vector numbers used for internal sources (ipi/timers) */
7df2457d OJ	284	unsigned int ipi_vecs[4];
ea94187f	285	unsigned int timer_vecs[8];
7df2457d OJ	286
	287	/* Spurious vector to program into unused sources */
	288	unsigned int spurious_vec;
	289
6cfef5b2	290	#ifdef CONFIG_MPIC_U3_HT_IRQS
14cf11af PM	291	/* The fixup table */
14cf11af PM	292	struct mpic_irq_fixup *fixups;
203041ad	293	raw_spinlock_t fixup_lock;
14cf11af PM	294	#endif
14cf11af PM	295
fbf0274e BH	296	/* Register access method */
	297	enum mpic_reg_type reg_type;
	298
e7a98675 KM	299	/* The physical base address of the MPIC */
	300	phys_addr_t paddr;
	301
14cf11af	302	/* The various ioremap'ed bases */
fbf0274e BH	303	struct mpic_reg_bank gregs;
	304	struct mpic_reg_bank tmregs;
	305	struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
	306	struct mpic_reg_bank isus[MPIC_MAX_ISU];
	307
7fd72186 BH	308	/* Protected sources */
	309	unsigned long *protected;
	310
7233593b ZR	311	#ifdef CONFIG_MPIC_WEIRD
	312	/* Pointer to HW info array */
	313	u32 *hw_set;
	314	#endif
	315
a7de7c74	316	#ifdef CONFIG_PCI_MSI
25235f71	317	struct msi_bitmap msi_bitmap;
a7de7c74 ME	318	#endif
a7de7c74 ME	319
0d72ba93 OJ	320	#ifdef CONFIG_MPIC_BROKEN_REGREAD
	321	u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
	322	#endif
	323
14cf11af PM	324	/* link */
14cf11af PM	325	struct mpic *next;
3669e930	326
3669e930 JB	327	#ifdef CONFIG_PM
	328	struct mpic_irq_save *save_data;
	329	#endif
14cf11af PM	330	};
14cf11af PM	331
7233593b ZR	332	/*
	333	* MPIC flags (passed to mpic_alloc)
	334	*
	335	* The top 4 bits contain an MPIC bhw id that is used to index the
	336	* register offsets and some masks when CONFIG_MPIC_WEIRD is set.
	337	* Note setting any ID (leaving those bits to 0) means standard MPIC
	338	*/
	339
be8bec56 KM	340	/*
	341	* This is a secondary ("chained") controller; it only uses the CPU0
	342	* registers. Primary controllers have IPIs and affinity control.
14cf11af	343	*/
be8bec56	344	#define MPIC_SECONDARY 0x00000001
7233593b	345
14cf11af PM	346	/* Set this for a big-endian MPIC */
	347	#define MPIC_BIG_ENDIAN 0x00000002
	348	/* Broken U3 MPIC */
6cfef5b2	349	#define MPIC_U3_HT_IRQS 0x00000004
14cf11af PM	350	/* Broken IPI registers (autodetected) */
	351	#define MPIC_BROKEN_IPI 0x00000008
	352	/* MPIC wants a reset */
	353	#define MPIC_WANTS_RESET 0x00000010
7233593b ZR	354	/* Spurious vector requires EOI */
	355	#define MPIC_SPV_EOI 0x00000020
	356	/* No passthrough disable */
	357	#define MPIC_NO_PTHROU_DIS 0x00000040
fbf0274e BH	358	/* DCR based MPIC */
fbf0274e BH	359	#define MPIC_USES_DCR 0x00000080
7df2457d OJ	360	/* MPIC has 11-bit vector fields (or larger) */
7df2457d OJ	361	#define MPIC_LARGE_VECTORS 0x00000100
f365355e OJ	362	/* Enable delivery of prio 15 interrupts as MCK instead of EE */
f365355e OJ	363	#define MPIC_ENABLE_MCK 0x00000200
d87bf3be OJ	364	/* Disable bias among target selection, spread interrupts evenly */
d87bf3be OJ	365	#define MPIC_NO_BIAS 0x00000400
475ca391 KG	366	/* Ignore NIRQS as reported by FRR */
475ca391 KG	367	#define MPIC_BROKEN_FRR_NIRQS 0x00000800
3c10c9c4 KG	368	/* Destination only supports a single CPU at a time */
3c10c9c4 KG	369	#define MPIC_SINGLE_DEST_CPU 0x00001000
d91e4ea7 KG	370	/* Enable CoreInt delivery of interrupts */
d91e4ea7 KG	371	#define MPIC_ENABLE_COREINT 0x00002000
dfec2202 MI	372	/* Disable resetting of the MPIC.
	373	* NOTE: This flag trumps MPIC_WANTS_RESET.
	374	*/
	375	#define MPIC_NO_RESET 0x00004000
22d168ce SW	376	/* Freescale MPIC (compatible includes "fsl,mpic") */
22d168ce SW	377	#define MPIC_FSL 0x00008000
7233593b ZR	378
	379	/* MPIC HW modification ID */
	380	#define MPIC_REGSET_MASK 0xf0000000
	381	#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
	382	#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
	383
	384	#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
	385	#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
14cf11af PM	386
	387	/* Allocate the controller structure and setup the linux irq descs
	388	* for the range if interrupts passed in. No HW initialization is
	389	* actually performed.
	390	*
	391	* @phys_addr: physial base address of the MPIC
	392	* @flags: flags, see constants above
	393	* @isu_size: number of interrupts in an ISU. Use 0 to use a
	394	* standard ISU-less setup (aka powermac)
	395	* @irq_offset: first irq number to assign to this mpic
	396	* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
	397	* to match the number of sources
	398	* @ipi_offset: first irq number to assign to this mpic IPI sources,
	399	* used only on primary mpic
	400	* @senses: array of sense values
	401	* @senses_num: number of entries in the array
	402	*
	403	* Note about the sense array. If none is passed, all interrupts are
6cfef5b2	404	* setup to be level negative unless MPIC_U3_HT_IRQS is set in which
14cf11af PM	405	* case they are edge positive (and the array is ignored anyway).
	406	* The values in the array start at the first source of the MPIC,
	407	* that is senses[0] correspond to linux irq "irq_offset".
	408	*/
0ebfff14	409	extern struct mpic mpic_alloc(struct device_node node,
a959ff56	410	phys_addr_t phys_addr,
14cf11af PM	411	unsigned int flags,
14cf11af PM	412	unsigned int isu_size,
14cf11af	413	unsigned int irq_count,
14cf11af PM	414	const char *name);
	415
	416	/* Assign ISUs, to call before mpic_init()
	417	*
	418	* @mpic: controller structure as returned by mpic_alloc()
	419	* @isu_num: ISU number
	420	* @phys_addr: physical address of the ISU
	421	*/
	422	extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
a959ff56	423	phys_addr_t phys_addr);
14cf11af	424
0ebfff14 BH	425	/* Set default sense codes
	426	*
	427	* @mpic: controller
	428	* @senses: array of sense codes
	429	* @count: size of above array
	430	*
	431	* Optionally provide an array (indexed on hardware interrupt numbers
	432	* for this MPIC) of default sense codes for the chip. Those are linux
	433	* sense codes IRQ_TYPE_*
	434	*
	435	* The driver gets ownership of the pointer, don't dispose of it or
	436	* anything like that. __init only.
	437	*/
	438	extern void mpic_set_default_senses(struct mpic mpic, u8 senses, int count);
	439
	440
14cf11af PM	441	/* Initialize the controller. After this has been called, none of the above
	442	* should be called again for this mpic
	443	*/
	444	extern void mpic_init(struct mpic *mpic);
	445
14cf11af PM	446	/*
	447	* All of the following functions must only be used after the
	448	* ISUs have been assigned and the controller fully initialized
	449	* with mpic_init()
	450	*/
	451
	452
06a901c5	453	/* Change the priority of an interrupt. Default is 8 for irqs and
14cf11af PM	454	* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
	455	* IPI number is then the offset'ed (linux irq number mapped to the IPI)
	456	*/
	457	extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
14cf11af PM	458
	459	/* Setup a non-boot CPU */
	460	extern void mpic_setup_this_cpu(void);
	461
	462	/* Clean up for kexec (or cpu offline or ...) */
	463	extern void mpic_teardown_this_cpu(int secondary);
	464
	465	/* Get the current cpu priority for this cpu (0..15) */
	466	extern int mpic_cpu_get_priority(void);
	467
	468	/* Set the current cpu priority for this cpu */
	469	extern void mpic_cpu_set_priority(int prio);
	470
	471	/* Request IPIs on primary mpic */
	472	extern void mpic_request_ipis(void);
	473
a9c59264 PM	474	/* Send a message (IPI) to a given target (cpu number or MSG_) /
	475	void smp_mpic_message_pass(int target, int msg);
	476
f365355e	477	/* Unmask a specific virq */
835c0553	478	extern void mpic_unmask_irq(struct irq_data *d);
f365355e	479	/* Mask a specific virq */
835c0553	480	extern void mpic_mask_irq(struct irq_data *d);
f365355e	481	/* EOI a specific virq */
835c0553	482	extern void mpic_end_irq(struct irq_data *d);
f365355e	483
14cf11af	484	/* Fetch interrupt from a given mpic */
35a84c2f	485	extern unsigned int mpic_get_one_irq(struct mpic *mpic);
f365355e	486	/* This one gets from the primary mpic */
35a84c2f	487	extern unsigned int mpic_get_irq(void);
d91e4ea7 KG	488	/* This one gets from the primary mpic via CoreInt*/
d91e4ea7 KG	489	extern unsigned int mpic_get_coreint_irq(void);
f365355e OJ	490	/* Fetch Machine Check interrupt from primary mpic */
f365355e OJ	491	extern unsigned int mpic_get_mcirq(void);
14cf11af	492
868ea0c9 MG	493	/* Set the EPIC clock ratio */
	494	void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
	495
	496	/* Enable/Disable EPIC serial interrupt mode */
	497	void mpic_set_serial_int(struct mpic *mpic, int enable);
	498
88ced031	499	#endif /* __KERNEL__ */
bbeb3f4c	500	#endif /* _ASM_POWERPC_MPIC_H */