[mirror_ubuntu-focal-kernel.git] / arch / powerpc / include / asm / nohash / 64 / pgtable-4k.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
#define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H

#include <asm-generic/5level-fixup.h>

/*
 * Entries per page directory level.  The PTE level must use a 64b record
 * for each page table entry.  The PMD and PGD level use a 32b record for
 * each entry by assuming that each entry is page aligned.
 */
#define PTE_INDEX_SIZE  9
#define PMD_INDEX_SIZE  7
#define PUD_INDEX_SIZE  9
#define PGD_INDEX_SIZE  9

#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_INDEX_SIZE)
#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
#define PUD_TABLE_SIZE	(sizeof(pud_t) << PUD_INDEX_SIZE)
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
#define PTRS_PER_PUD	(1 << PUD_INDEX_SIZE)
#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)

/* PMD_SHIFT determines what a second-level page table entry can map */
#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PUD_SHIFT determines what a third-level page table entry can map */
#define PUD_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
#define PUD_SIZE	(1UL << PUD_SHIFT)
#define PUD_MASK	(~(PUD_SIZE-1))

/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
#define PGDIR_SHIFT	(PUD_SHIFT + PUD_INDEX_SIZE)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/* Bits to mask out from a PMD to get to the PTE page */
#define PMD_MASKED_BITS		0
/* Bits to mask out from a PUD to get to the PMD page */
#define PUD_MASKED_BITS		0
/* Bits to mask out from a PGD to get to the PUD page */
#define PGD_MASKED_BITS		0


/*
 * 4-level page tables related bits
 */

#define pgd_none(pgd)		(!pgd_val(pgd))
#define pgd_bad(pgd)		(pgd_val(pgd) == 0)
#define pgd_present(pgd)	(pgd_val(pgd) != 0)
#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)

#ifndef __ASSEMBLY__

static inline void pgd_clear(pgd_t *pgdp)
{
	*pgdp = __pgd(0);
}

static inline pte_t pgd_pte(pgd_t pgd)
{
	return __pte(pgd_val(pgd));
}

static inline pgd_t pte_pgd(pte_t pte)
{
	return __pgd(pte_val(pte));
}
extern struct page *pgd_page(pgd_t pgd);

#endif /* !__ASSEMBLY__ */

#define pud_offset(pgdp, addr)	\
  (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
    (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))

#define pud_ERROR(e) \
	pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))

/*
 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
#define remap_4k_pfn(vma, addr, pfn, prot)	\
	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))

#endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
17ed9e31 AK	2	#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
17ed9e31 AK	3	#define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
9849a569 KS	4
	5	#include <asm-generic/5level-fixup.h>
	6
3c726f8d BH	7	/*
	8	* Entries per page directory level. The PTE level must use a 64b record
	9	* for each page table entry. The PMD and PGD level use a 32b record for
	10	* each entry by assuming that each entry is page aligned.
	11	*/
	12	#define PTE_INDEX_SIZE 9
	13	#define PMD_INDEX_SIZE 7
048ee099	14	#define PUD_INDEX_SIZE 9
3c726f8d BH	15	#define PGD_INDEX_SIZE 9
3c726f8d BH	16
ee7a76da	17	#ifndef __ASSEMBLY__
3c726f8d BH	18	#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
	19	#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
	20	#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
	21	#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
ee7a76da	22	#endif /* __ASSEMBLY__ */
3c726f8d BH	23
	24	#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
	25	#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
f3d34445	26	#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
3c726f8d BH	27	#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
	28
	29	/* PMD_SHIFT determines what a second-level page table entry can map */
	30	#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
	31	#define PMD_SIZE (1UL << PMD_SHIFT)
	32	#define PMD_MASK (~(PMD_SIZE-1))
	33
	34	/* PUD_SHIFT determines what a third-level page table entry can map */
	35	#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
	36	#define PUD_SIZE (1UL << PUD_SHIFT)
	37	#define PUD_MASK (~(PUD_SIZE-1))
	38
	39	/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
	40	#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
	41	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	42	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	43
3c726f8d BH	44	/* Bits to mask out from a PMD to get to the PTE page */
	45	#define PMD_MASKED_BITS 0
	46	/* Bits to mask out from a PUD to get to the PMD page */
	47	#define PUD_MASKED_BITS 0
	48	/* Bits to mask out from a PGD to get to the PUD page */
	49	#define PGD_MASKED_BITS 0
	50
bf72aeba	51
3c726f8d BH	52	/*
	53	* 4-level page tables related bits
	54	*/
	55
	56	#define pgd_none(pgd) (!pgd_val(pgd))
	57	#define pgd_bad(pgd) (pgd_val(pgd) == 0)
	58	#define pgd_present(pgd) (pgd_val(pgd) != 0)
46a82b2d	59	#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
06743521 AK	60
	61	#ifndef __ASSEMBLY__
	62
f281b5d5 AK	63	static inline void pgd_clear(pgd_t *pgdp)
	64	{
	65	*pgdp = __pgd(0);
	66	}
	67
06743521 AK	68	static inline pte_t pgd_pte(pgd_t pgd)
	69	{
	70	return __pte(pgd_val(pgd));
	71	}
	72
	73	static inline pgd_t pte_pgd(pte_t pte)
	74	{
	75	return __pgd(pte_val(pte));
	76	}
	77	extern struct page *pgd_page(pgd_t pgd);
	78
	79	#endif /* !__ASSEMBLY__ */
3c726f8d BH	80
3c726f8d BH	81	#define pud_offset(pgdp, addr) \
46a82b2d	82	(((pud_t ) pgd_page_vaddr((pgdp))) + \
3c726f8d BH	83	(((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
	84
	85	#define pud_ERROR(e) \
a7696b36	86	pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
721151d0	87
c605782b BH	88	/*
c605782b BH	89	* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
721151d0 PM	90	#define remap_4k_pfn(vma, addr, pfn, prot) \
721151d0 PM	91	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
c605782b	92
17ed9e31	93	#endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */