projects / mirror_ubuntu-hirsute-kernel.git / blame
| Commit | Line | Data |
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| 17ed9e31 AK |
1 | #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H |
| 2 | #define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H | |
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3 | |
| 4 | #include <asm-generic/5level-fixup.h> | |
| 5 | ||
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6 | /* |
| 7 | * Entries per page directory level. The PTE level must use a 64b record | |
| 8 | * for each page table entry. The PMD and PGD level use a 32b record for | |
| 9 | * each entry by assuming that each entry is page aligned. | |
| 10 | */ | |
| 11 | #define PTE_INDEX_SIZE 9 | |
| 12 | #define PMD_INDEX_SIZE 7 | |
| 048ee099 | 13 | #define PUD_INDEX_SIZE 9 |
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14 | #define PGD_INDEX_SIZE 9 |
| 15 | ||
| ee7a76da | 16 | #ifndef __ASSEMBLY__ |
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17 | #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) |
| 18 | #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) | |
| 19 | #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) | |
| 20 | #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) | |
| ee7a76da | 21 | #endif /* __ASSEMBLY__ */ |
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22 | |
| 23 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
| 24 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
| f3d34445 | 25 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) |
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26 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) |
| 27 | ||
| 28 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
| 29 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
| 30 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
| 31 | #define PMD_MASK (~(PMD_SIZE-1)) | |
| 32 | ||
| 33 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
| 34 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
| 35 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
| 36 | #define PUD_MASK (~(PUD_SIZE-1)) | |
| 37 | ||
| 38 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
| 39 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
| 40 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
| 41 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
| 42 | ||
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43 | /* Bits to mask out from a PMD to get to the PTE page */ |
| 44 | #define PMD_MASKED_BITS 0 | |
| 45 | /* Bits to mask out from a PUD to get to the PMD page */ | |
| 46 | #define PUD_MASKED_BITS 0 | |
| 47 | /* Bits to mask out from a PGD to get to the PUD page */ | |
| 48 | #define PGD_MASKED_BITS 0 | |
| 49 | ||
| bf72aeba | 50 | |
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51 | /* |
| 52 | * 4-level page tables related bits | |
| 53 | */ | |
| 54 | ||
| 55 | #define pgd_none(pgd) (!pgd_val(pgd)) | |
| 56 | #define pgd_bad(pgd) (pgd_val(pgd) == 0) | |
| 57 | #define pgd_present(pgd) (pgd_val(pgd) != 0) | |
| 46a82b2d | 58 | #define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS) |
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59 | |
| 60 | #ifndef __ASSEMBLY__ | |
| 61 | ||
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62 | static inline void pgd_clear(pgd_t *pgdp) |
| 63 | { | |
| 64 | *pgdp = __pgd(0); | |
| 65 | } | |
| 66 | ||
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67 | static inline pte_t pgd_pte(pgd_t pgd) |
| 68 | { | |
| 69 | return __pte(pgd_val(pgd)); | |
| 70 | } | |
| 71 | ||
| 72 | static inline pgd_t pte_pgd(pte_t pte) | |
| 73 | { | |
| 74 | return __pgd(pte_val(pte)); | |
| 75 | } | |
| 76 | extern struct page *pgd_page(pgd_t pgd); | |
| 77 | ||
| 78 | #endif /* !__ASSEMBLY__ */ | |
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79 | |
| 80 | #define pud_offset(pgdp, addr) \ | |
| 46a82b2d | 81 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + \ |
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82 | (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) |
| 83 | ||
| 84 | #define pud_ERROR(e) \ | |
| a7696b36 | 85 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) |
| 721151d0 | 86 | |
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87 | /* |
| 88 | * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */ | |
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89 | #define remap_4k_pfn(vma, addr, pfn, prot) \ |
| 90 | remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) | |
| c605782b | 91 | |
| 17ed9e31 | 92 | #endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */ |