[mirror_ubuntu-eoan-kernel.git] / arch / powerpc / include / asm / nohash / 64 / pgtable-64k.h

#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
#define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H

#define __ARCH_USE_5LEVEL_HACK
#include <asm-generic/pgtable-nopud.h>


#define PTE_INDEX_SIZE  8
#define PMD_INDEX_SIZE  10
#define PUD_INDEX_SIZE	0
#define PGD_INDEX_SIZE  12

/*
 * we support 32 fragments per PTE page of 64K size
 */
#define PTE_FRAG_NR	32
/*
 * We use a 2K PTE page fragment and another 2K for storing
 * real_pte_t hash index
 */
#define PTE_FRAG_SIZE_SHIFT  11
#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)

#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE	PTE_FRAG_SIZE
#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
#define PUD_TABLE_SIZE	(0)
#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
#endif	/* __ASSEMBLY__ */

#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)

/* PMD_SHIFT determines what a second-level page table entry can map */
#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * Bits to mask out from a PMD to get to the PTE page
 * PMDs point to PTE table fragments which are PTE_FRAG_SIZE aligned.
 */
#define PMD_MASKED_BITS		(PTE_FRAG_SIZE - 1)
/* Bits to mask out from a PGD/PUD to get to the PMD page */
#define PUD_MASKED_BITS		0x1ff

#define pgd_pte(pgd)	(pud_pte(((pud_t){ pgd })))
#define pte_pgd(pte)	((pgd_t)pte_pud(pte))

#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */
Commit	Line	Data
17ed9e31 AK	1	#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
17ed9e31 AK	2	#define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
c605782b	3
9849a569	4	#define __ARCH_USE_5LEVEL_HACK
c605782b BH	5	#include <asm-generic/pgtable-nopud.h>
	6
	7
419df06e AK	8	#define PTE_INDEX_SIZE 8
419df06e AK	9	#define PMD_INDEX_SIZE 10
c605782b	10	#define PUD_INDEX_SIZE 0
419df06e	11	#define PGD_INDEX_SIZE 12
c605782b	12
62607bc6	13	/*
cc50380d	14	* we support 32 fragments per PTE page of 64K size
62607bc6	15	*/
cc50380d	16	#define PTE_FRAG_NR 32
62607bc6 AK	17	/*
	18	* We use a 2K PTE page fragment and another 2K for storing
	19	* real_pte_t hash index
	20	*/
cc50380d	21	#define PTE_FRAG_SIZE_SHIFT 11
62607bc6 AK	22	#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
62607bc6 AK	23
c605782b	24	#ifndef __ASSEMBLY__
62607bc6	25	#define PTE_TABLE_SIZE PTE_FRAG_SIZE
c605782b	26	#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
e93d8e67	27	#define PUD_TABLE_SIZE (0)
c605782b	28	#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
7d60b02c	29	#endif /* __ASSEMBLY__ */
c605782b BH	30
	31	#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
	32	#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
	33	#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
	34
c605782b BH	35	/* PMD_SHIFT determines what a second-level page table entry can map */
	36	#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
	37	#define PMD_SIZE (1UL << PMD_SHIFT)
	38	#define PMD_MASK (~(PMD_SIZE-1))
	39
	40	/* PGDIR_SHIFT determines what a third-level page table entry can map */
	41	#define PGDIR_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
	42	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	43	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	44
62607bc6 AK	45	/*
	46	* Bits to mask out from a PMD to get to the PTE page
	47	* PMDs point to PTE table fragments which are PTE_FRAG_SIZE aligned.
	48	*/
	49	#define PMD_MASKED_BITS (PTE_FRAG_SIZE - 1)
c605782b BH	50	/* Bits to mask out from a PGD/PUD to get to the PMD page */
	51	#define PUD_MASKED_BITS 0x1ff
	52
06743521 AK	53	#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
	54	#define pte_pgd(pte) ((pgd_t)pte_pud(pte))
	55
17ed9e31	56	#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */