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Commit | Line | Data |
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d800ba12 | 1 | /* |
d7cf83fc | 2 | * OPAL API definitions. |
d800ba12 | 3 | * |
d7cf83fc | 4 | * Copyright 2011-2015 IBM Corp. |
d800ba12 ME |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #ifndef __OPAL_API_H | |
13 | #define __OPAL_API_H | |
14 | ||
15 | /****** OPAL APIs ******/ | |
16 | ||
17 | /* Return codes */ | |
d7cf83fc | 18 | #define OPAL_SUCCESS 0 |
d800ba12 ME |
19 | #define OPAL_PARAMETER -1 |
20 | #define OPAL_BUSY -2 | |
21 | #define OPAL_PARTIAL -3 | |
22 | #define OPAL_CONSTRAINED -4 | |
23 | #define OPAL_CLOSED -5 | |
24 | #define OPAL_HARDWARE -6 | |
25 | #define OPAL_UNSUPPORTED -7 | |
26 | #define OPAL_PERMISSION -8 | |
27 | #define OPAL_NO_MEM -9 | |
28 | #define OPAL_RESOURCE -10 | |
29 | #define OPAL_INTERNAL_ERROR -11 | |
30 | #define OPAL_BUSY_EVENT -12 | |
31 | #define OPAL_HARDWARE_FROZEN -13 | |
32 | #define OPAL_WRONG_STATE -14 | |
33 | #define OPAL_ASYNC_COMPLETION -15 | |
d7cf83fc | 34 | #define OPAL_EMPTY -16 |
d800ba12 ME |
35 | #define OPAL_I2C_TIMEOUT -17 |
36 | #define OPAL_I2C_INVALID_CMD -18 | |
37 | #define OPAL_I2C_LBUS_PARITY -19 | |
38 | #define OPAL_I2C_BKEND_OVERRUN -20 | |
39 | #define OPAL_I2C_BKEND_ACCESS -21 | |
40 | #define OPAL_I2C_ARBT_LOST -22 | |
41 | #define OPAL_I2C_NACK_RCVD -23 | |
42 | #define OPAL_I2C_STOP_ERR -24 | |
eeea1a43 BH |
43 | #define OPAL_XIVE_PROVISIONING -31 |
44 | #define OPAL_XIVE_FREE_ACTIVE -32 | |
d800ba12 ME |
45 | |
46 | /* API Tokens (in r0) */ | |
d7cf83fc ME |
47 | #define OPAL_INVALID_CALL -1 |
48 | #define OPAL_TEST 0 | |
d800ba12 ME |
49 | #define OPAL_CONSOLE_WRITE 1 |
50 | #define OPAL_CONSOLE_READ 2 | |
51 | #define OPAL_RTC_READ 3 | |
52 | #define OPAL_RTC_WRITE 4 | |
53 | #define OPAL_CEC_POWER_DOWN 5 | |
54 | #define OPAL_CEC_REBOOT 6 | |
55 | #define OPAL_READ_NVRAM 7 | |
56 | #define OPAL_WRITE_NVRAM 8 | |
57 | #define OPAL_HANDLE_INTERRUPT 9 | |
58 | #define OPAL_POLL_EVENTS 10 | |
59 | #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 | |
60 | #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 | |
61 | #define OPAL_PCI_CONFIG_READ_BYTE 13 | |
62 | #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 | |
63 | #define OPAL_PCI_CONFIG_READ_WORD 15 | |
64 | #define OPAL_PCI_CONFIG_WRITE_BYTE 16 | |
65 | #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 | |
66 | #define OPAL_PCI_CONFIG_WRITE_WORD 18 | |
67 | #define OPAL_SET_XIVE 19 | |
68 | #define OPAL_GET_XIVE 20 | |
69 | #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ | |
70 | #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 | |
71 | #define OPAL_PCI_EEH_FREEZE_STATUS 23 | |
72 | #define OPAL_PCI_SHPC 24 | |
73 | #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 | |
74 | #define OPAL_PCI_EEH_FREEZE_CLEAR 26 | |
75 | #define OPAL_PCI_PHB_MMIO_ENABLE 27 | |
76 | #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 | |
77 | #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 | |
78 | #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 | |
79 | #define OPAL_PCI_SET_PE 31 | |
80 | #define OPAL_PCI_SET_PELTV 32 | |
81 | #define OPAL_PCI_SET_MVE 33 | |
82 | #define OPAL_PCI_SET_MVE_ENABLE 34 | |
83 | #define OPAL_PCI_GET_XIVE_REISSUE 35 | |
84 | #define OPAL_PCI_SET_XIVE_REISSUE 36 | |
85 | #define OPAL_PCI_SET_XIVE_PE 37 | |
86 | #define OPAL_GET_XIVE_SOURCE 38 | |
87 | #define OPAL_GET_MSI_32 39 | |
88 | #define OPAL_GET_MSI_64 40 | |
89 | #define OPAL_START_CPU 41 | |
90 | #define OPAL_QUERY_CPU_STATUS 42 | |
d7cf83fc | 91 | #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ |
d800ba12 ME |
92 | #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 |
93 | #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 | |
94 | #define OPAL_PCI_RESET 49 | |
95 | #define OPAL_PCI_GET_HUB_DIAG_DATA 50 | |
96 | #define OPAL_PCI_GET_PHB_DIAG_DATA 51 | |
97 | #define OPAL_PCI_FENCE_PHB 52 | |
98 | #define OPAL_PCI_REINIT 53 | |
99 | #define OPAL_PCI_MASK_PE_ERROR 54 | |
100 | #define OPAL_SET_SLOT_LED_STATUS 55 | |
101 | #define OPAL_GET_EPOW_STATUS 56 | |
102 | #define OPAL_SET_SYSTEM_ATTENTION_LED 57 | |
103 | #define OPAL_RESERVED1 58 | |
104 | #define OPAL_RESERVED2 59 | |
105 | #define OPAL_PCI_NEXT_ERROR 60 | |
106 | #define OPAL_PCI_EEH_FREEZE_STATUS2 61 | |
107 | #define OPAL_PCI_POLL 62 | |
108 | #define OPAL_PCI_MSI_EOI 63 | |
109 | #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 | |
110 | #define OPAL_XSCOM_READ 65 | |
111 | #define OPAL_XSCOM_WRITE 66 | |
112 | #define OPAL_LPC_READ 67 | |
113 | #define OPAL_LPC_WRITE 68 | |
114 | #define OPAL_RETURN_CPU 69 | |
115 | #define OPAL_REINIT_CPUS 70 | |
116 | #define OPAL_ELOG_READ 71 | |
117 | #define OPAL_ELOG_WRITE 72 | |
118 | #define OPAL_ELOG_ACK 73 | |
119 | #define OPAL_ELOG_RESEND 74 | |
120 | #define OPAL_ELOG_SIZE 75 | |
121 | #define OPAL_FLASH_VALIDATE 76 | |
122 | #define OPAL_FLASH_MANAGE 77 | |
123 | #define OPAL_FLASH_UPDATE 78 | |
124 | #define OPAL_RESYNC_TIMEBASE 79 | |
125 | #define OPAL_CHECK_TOKEN 80 | |
126 | #define OPAL_DUMP_INIT 81 | |
127 | #define OPAL_DUMP_INFO 82 | |
128 | #define OPAL_DUMP_READ 83 | |
129 | #define OPAL_DUMP_ACK 84 | |
130 | #define OPAL_GET_MSG 85 | |
131 | #define OPAL_CHECK_ASYNC_COMPLETION 86 | |
132 | #define OPAL_SYNC_HOST_REBOOT 87 | |
133 | #define OPAL_SENSOR_READ 88 | |
134 | #define OPAL_GET_PARAM 89 | |
135 | #define OPAL_SET_PARAM 90 | |
136 | #define OPAL_DUMP_RESEND 91 | |
d7cf83fc ME |
137 | #define OPAL_ELOG_SEND 92 /* Deprecated */ |
138 | #define OPAL_PCI_SET_PHB_CAPI_MODE 93 | |
d800ba12 | 139 | #define OPAL_DUMP_INFO2 94 |
d7cf83fc | 140 | #define OPAL_WRITE_OPPANEL_ASYNC 95 |
d800ba12 ME |
141 | #define OPAL_PCI_ERR_INJECT 96 |
142 | #define OPAL_PCI_EEH_FREEZE_SET 97 | |
143 | #define OPAL_HANDLE_HMI 98 | |
144 | #define OPAL_CONFIG_CPU_IDLE_STATE 99 | |
145 | #define OPAL_SLW_SET_REG 100 | |
146 | #define OPAL_REGISTER_DUMP_REGION 101 | |
147 | #define OPAL_UNREGISTER_DUMP_REGION 102 | |
148 | #define OPAL_WRITE_TPO 103 | |
149 | #define OPAL_READ_TPO 104 | |
d7cf83fc ME |
150 | #define OPAL_GET_DPO_STATUS 105 |
151 | #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ | |
d800ba12 ME |
152 | #define OPAL_IPMI_SEND 107 |
153 | #define OPAL_IPMI_RECV 108 | |
154 | #define OPAL_I2C_REQUEST 109 | |
ed59190e CB |
155 | #define OPAL_FLASH_READ 110 |
156 | #define OPAL_FLASH_WRITE 111 | |
157 | #define OPAL_FLASH_ERASE 112 | |
0d7cd855 | 158 | #define OPAL_PRD_MSG 113 |
8a8d9181 AK |
159 | #define OPAL_LEDS_GET_INDICATOR 114 |
160 | #define OPAL_LEDS_SET_INDICATOR 115 | |
e784b649 | 161 | #define OPAL_CEC_REBOOT2 116 |
affddff6 | 162 | #define OPAL_CONSOLE_FLUSH 117 |
ea0d856c GS |
163 | #define OPAL_GET_DEVICE_TREE 118 |
164 | #define OPAL_PCI_GET_PRESENCE_STATE 119 | |
165 | #define OPAL_PCI_GET_POWER_STATE 120 | |
166 | #define OPAL_PCI_SET_POWER_STATE 121 | |
9fedd3f8 BH |
167 | #define OPAL_INT_GET_XIRR 122 |
168 | #define OPAL_INT_SET_CPPR 123 | |
169 | #define OPAL_INT_EOI 124 | |
170 | #define OPAL_INT_SET_MFRR 125 | |
69c592ed | 171 | #define OPAL_PCI_TCE_KILL 126 |
1d0761d2 | 172 | #define OPAL_NMMU_SET_PTCR 127 |
eeea1a43 BH |
173 | #define OPAL_XIVE_RESET 128 |
174 | #define OPAL_XIVE_GET_IRQ_INFO 129 | |
175 | #define OPAL_XIVE_GET_IRQ_CONFIG 130 | |
176 | #define OPAL_XIVE_SET_IRQ_CONFIG 131 | |
177 | #define OPAL_XIVE_GET_QUEUE_INFO 132 | |
178 | #define OPAL_XIVE_SET_QUEUE_INFO 133 | |
179 | #define OPAL_XIVE_DONATE_PAGE 134 | |
180 | #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135 | |
181 | #define OPAL_XIVE_FREE_VP_BLOCK 136 | |
182 | #define OPAL_XIVE_GET_VP_INFO 137 | |
183 | #define OPAL_XIVE_SET_VP_INFO 138 | |
184 | #define OPAL_XIVE_ALLOCATE_IRQ 139 | |
185 | #define OPAL_XIVE_FREE_IRQ 140 | |
186 | #define OPAL_XIVE_SYNC 141 | |
187 | #define OPAL_XIVE_DUMP 142 | |
188 | #define OPAL_XIVE_RESERVED3 143 | |
189 | #define OPAL_XIVE_RESERVED4 144 | |
1ab66d1f AP |
190 | #define OPAL_NPU_INIT_CONTEXT 146 |
191 | #define OPAL_NPU_DESTROY_CONTEXT 147 | |
192 | #define OPAL_NPU_MAP_LPAR 148 | |
c7ea8292 MS |
193 | #define OPAL_IMC_COUNTERS_INIT 149 |
194 | #define OPAL_IMC_COUNTERS_START 150 | |
195 | #define OPAL_IMC_COUNTERS_STOP 151 | |
1b9f175e | 196 | #define OPAL_LAST 151 |
d800ba12 ME |
197 | |
198 | /* Device tree flags */ | |
199 | ||
bcef83a0 SP |
200 | /* |
201 | * Flags set in power-mgmt nodes in device tree describing | |
202 | * idle states that are supported in the platform. | |
d800ba12 | 203 | */ |
bcef83a0 SP |
204 | |
205 | #define OPAL_PM_TIMEBASE_STOP 0x00000002 | |
206 | #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000 | |
207 | #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000 | |
d7cf83fc ME |
208 | #define OPAL_PM_NAP_ENABLED 0x00010000 |
209 | #define OPAL_PM_SLEEP_ENABLED 0x00020000 | |
210 | #define OPAL_PM_WINKLE_ENABLED 0x00040000 | |
211 | #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ | |
bcef83a0 SP |
212 | #define OPAL_PM_STOP_INST_FAST 0x00100000 |
213 | #define OPAL_PM_STOP_INST_DEEP 0x00200000 | |
d800ba12 | 214 | |
5703d2f4 SP |
215 | /* |
216 | * OPAL_CONFIG_CPU_IDLE_STATE parameters | |
217 | */ | |
218 | #define OPAL_CONFIG_IDLE_FASTSLEEP 1 | |
219 | #define OPAL_CONFIG_IDLE_UNDO 0 | |
220 | #define OPAL_CONFIG_IDLE_APPLY 1 | |
221 | ||
d800ba12 ME |
222 | #ifndef __ASSEMBLY__ |
223 | ||
224 | /* Other enums */ | |
d800ba12 ME |
225 | enum OpalFreezeState { |
226 | OPAL_EEH_STOPPED_NOT_FROZEN = 0, | |
227 | OPAL_EEH_STOPPED_MMIO_FREEZE = 1, | |
228 | OPAL_EEH_STOPPED_DMA_FREEZE = 2, | |
229 | OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, | |
230 | OPAL_EEH_STOPPED_RESET = 4, | |
231 | OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, | |
232 | OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 | |
233 | }; | |
234 | ||
235 | enum OpalEehFreezeActionToken { | |
236 | OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, | |
237 | OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, | |
238 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, | |
239 | ||
240 | OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, | |
241 | OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, | |
242 | OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 | |
243 | }; | |
244 | ||
245 | enum OpalPciStatusToken { | |
246 | OPAL_EEH_NO_ERROR = 0, | |
247 | OPAL_EEH_IOC_ERROR = 1, | |
248 | OPAL_EEH_PHB_ERROR = 2, | |
249 | OPAL_EEH_PE_ERROR = 3, | |
250 | OPAL_EEH_PE_MMIO_ERROR = 4, | |
251 | OPAL_EEH_PE_DMA_ERROR = 5 | |
252 | }; | |
253 | ||
254 | enum OpalPciErrorSeverity { | |
255 | OPAL_EEH_SEV_NO_ERROR = 0, | |
256 | OPAL_EEH_SEV_IOC_DEAD = 1, | |
257 | OPAL_EEH_SEV_PHB_DEAD = 2, | |
258 | OPAL_EEH_SEV_PHB_FENCED = 3, | |
259 | OPAL_EEH_SEV_PE_ER = 4, | |
260 | OPAL_EEH_SEV_INF = 5 | |
261 | }; | |
262 | ||
263 | enum OpalErrinjectType { | |
264 | OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, | |
265 | OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, | |
266 | }; | |
267 | ||
268 | enum OpalErrinjectFunc { | |
269 | /* IOA bus specific errors */ | |
270 | OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, | |
271 | OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, | |
272 | OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, | |
273 | OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, | |
274 | OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, | |
275 | OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, | |
276 | OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, | |
277 | OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, | |
278 | OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, | |
279 | OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, | |
280 | OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, | |
281 | OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, | |
282 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, | |
283 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, | |
284 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, | |
285 | OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, | |
286 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, | |
287 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, | |
288 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, | |
289 | OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, | |
290 | }; | |
291 | ||
d800ba12 ME |
292 | enum OpalMmioWindowType { |
293 | OPAL_M32_WINDOW_TYPE = 1, | |
294 | OPAL_M64_WINDOW_TYPE = 2, | |
d7cf83fc | 295 | OPAL_IO_WINDOW_TYPE = 3 |
d800ba12 ME |
296 | }; |
297 | ||
d800ba12 | 298 | enum OpalExceptionHandler { |
d7cf83fc | 299 | OPAL_MACHINE_CHECK_HANDLER = 1, |
d800ba12 | 300 | OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, |
d7cf83fc | 301 | OPAL_SOFTPATCH_HANDLER = 3 |
d800ba12 ME |
302 | }; |
303 | ||
304 | enum OpalPendingState { | |
d7cf83fc ME |
305 | OPAL_EVENT_OPAL_INTERNAL = 0x1, |
306 | OPAL_EVENT_NVRAM = 0x2, | |
307 | OPAL_EVENT_RTC = 0x4, | |
308 | OPAL_EVENT_CONSOLE_OUTPUT = 0x8, | |
309 | OPAL_EVENT_CONSOLE_INPUT = 0x10, | |
310 | OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, | |
311 | OPAL_EVENT_ERROR_LOG = 0x40, | |
312 | OPAL_EVENT_EPOW = 0x80, | |
313 | OPAL_EVENT_LED_STATUS = 0x100, | |
314 | OPAL_EVENT_PCI_ERROR = 0x200, | |
315 | OPAL_EVENT_DUMP_AVAIL = 0x400, | |
316 | OPAL_EVENT_MSG_PENDING = 0x800, | |
d800ba12 ME |
317 | }; |
318 | ||
319 | enum OpalThreadStatus { | |
320 | OPAL_THREAD_INACTIVE = 0x0, | |
321 | OPAL_THREAD_STARTED = 0x1, | |
322 | OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ | |
323 | }; | |
324 | ||
325 | enum OpalPciBusCompare { | |
326 | OpalPciBusAny = 0, /* Any bus number match */ | |
327 | OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ | |
328 | OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ | |
329 | OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ | |
330 | OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ | |
331 | OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ | |
332 | OpalPciBusAll = 7, /* Match bus number exactly */ | |
333 | }; | |
334 | ||
335 | enum OpalDeviceCompare { | |
336 | OPAL_IGNORE_RID_DEVICE_NUMBER = 0, | |
337 | OPAL_COMPARE_RID_DEVICE_NUMBER = 1 | |
338 | }; | |
339 | ||
340 | enum OpalFuncCompare { | |
341 | OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, | |
342 | OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 | |
343 | }; | |
344 | ||
345 | enum OpalPeAction { | |
346 | OPAL_UNMAP_PE = 0, | |
347 | OPAL_MAP_PE = 1 | |
348 | }; | |
349 | ||
350 | enum OpalPeltvAction { | |
351 | OPAL_REMOVE_PE_FROM_DOMAIN = 0, | |
352 | OPAL_ADD_PE_TO_DOMAIN = 1 | |
353 | }; | |
354 | ||
355 | enum OpalMveEnableAction { | |
356 | OPAL_DISABLE_MVE = 0, | |
357 | OPAL_ENABLE_MVE = 1 | |
358 | }; | |
359 | ||
d7cf83fc | 360 | enum OpalM64Action { |
d800ba12 ME |
361 | OPAL_DISABLE_M64 = 0, |
362 | OPAL_ENABLE_M64_SPLIT = 1, | |
363 | OPAL_ENABLE_M64_NON_SPLIT = 2 | |
364 | }; | |
365 | ||
366 | enum OpalPciResetScope { | |
367 | OPAL_RESET_PHB_COMPLETE = 1, | |
368 | OPAL_RESET_PCI_LINK = 2, | |
369 | OPAL_RESET_PHB_ERROR = 3, | |
370 | OPAL_RESET_PCI_HOT = 4, | |
371 | OPAL_RESET_PCI_FUNDAMENTAL = 5, | |
372 | OPAL_RESET_PCI_IODA_TABLE = 6 | |
373 | }; | |
374 | ||
375 | enum OpalPciReinitScope { | |
d7cf83fc ME |
376 | /* |
377 | * Note: we chose values that do not overlap | |
378 | * OpalPciResetScope as OPAL v2 used the same | |
379 | * enum for both | |
380 | */ | |
d800ba12 ME |
381 | OPAL_REINIT_PCI_DEV = 1000 |
382 | }; | |
383 | ||
384 | enum OpalPciResetState { | |
385 | OPAL_DEASSERT_RESET = 0, | |
d7cf83fc | 386 | OPAL_ASSERT_RESET = 1 |
d800ba12 ME |
387 | }; |
388 | ||
ea0d856c GS |
389 | enum OpalPciSlotPresence { |
390 | OPAL_PCI_SLOT_EMPTY = 0, | |
391 | OPAL_PCI_SLOT_PRESENT = 1 | |
392 | }; | |
393 | ||
394 | enum OpalPciSlotPower { | |
395 | OPAL_PCI_SLOT_POWER_OFF = 0, | |
396 | OPAL_PCI_SLOT_POWER_ON = 1, | |
397 | OPAL_PCI_SLOT_OFFLINE = 2, | |
398 | OPAL_PCI_SLOT_ONLINE = 3 | |
399 | }; | |
400 | ||
5d53be7d ME |
401 | enum OpalSlotLedType { |
402 | OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */ | |
403 | OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */ | |
404 | OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */ | |
405 | OPAL_SLOT_LED_TYPE_MAX = 3 | |
406 | }; | |
407 | ||
408 | enum OpalSlotLedState { | |
409 | OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */ | |
410 | OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */ | |
411 | }; | |
412 | ||
d800ba12 ME |
413 | /* |
414 | * Address cycle types for LPC accesses. These also correspond | |
415 | * to the content of the first cell of the "reg" property for | |
416 | * device nodes on the LPC bus | |
417 | */ | |
418 | enum OpalLPCAddressType { | |
419 | OPAL_LPC_MEM = 0, | |
420 | OPAL_LPC_IO = 1, | |
421 | OPAL_LPC_FW = 2, | |
422 | }; | |
423 | ||
d7cf83fc | 424 | enum opal_msg_type { |
b3d79eaa | 425 | OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, |
d7cf83fc ME |
426 | * additional params function-specific |
427 | */ | |
b3d79eaa VP |
428 | OPAL_MSG_MEM_ERR = 1, |
429 | OPAL_MSG_EPOW = 2, | |
430 | OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */ | |
431 | OPAL_MSG_HMI_EVT = 4, | |
432 | OPAL_MSG_DPO = 5, | |
433 | OPAL_MSG_PRD = 6, | |
434 | OPAL_MSG_OCC = 7, | |
d7cf83fc | 435 | OPAL_MSG_TYPE_MAX, |
d800ba12 ME |
436 | }; |
437 | ||
438 | struct opal_msg { | |
439 | __be32 msg_type; | |
440 | __be32 reserved; | |
441 | __be64 params[8]; | |
442 | }; | |
443 | ||
d7cf83fc ME |
444 | /* System parameter permission */ |
445 | enum OpalSysparamPerm { | |
446 | OPAL_SYSPARAM_READ = 0x1, | |
447 | OPAL_SYSPARAM_WRITE = 0x2, | |
448 | OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), | |
449 | }; | |
450 | ||
d800ba12 ME |
451 | enum { |
452 | OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, | |
453 | }; | |
454 | ||
455 | struct opal_ipmi_msg { | |
d7cf83fc ME |
456 | uint8_t version; |
457 | uint8_t netfn; | |
458 | uint8_t cmd; | |
459 | uint8_t data[]; | |
d800ba12 ME |
460 | }; |
461 | ||
462 | /* FSP memory errors handling */ | |
463 | enum OpalMemErr_Version { | |
464 | OpalMemErr_V1 = 1, | |
465 | }; | |
466 | ||
467 | enum OpalMemErrType { | |
468 | OPAL_MEM_ERR_TYPE_RESILIENCE = 0, | |
469 | OPAL_MEM_ERR_TYPE_DYN_DALLOC, | |
d800ba12 ME |
470 | }; |
471 | ||
472 | /* Memory Reilience error type */ | |
473 | enum OpalMemErr_ResilErrType { | |
474 | OPAL_MEM_RESILIENCE_CE = 0, | |
475 | OPAL_MEM_RESILIENCE_UE, | |
476 | OPAL_MEM_RESILIENCE_UE_SCRUB, | |
477 | }; | |
478 | ||
479 | /* Dynamic Memory Deallocation type */ | |
480 | enum OpalMemErr_DynErrType { | |
481 | OPAL_MEM_DYNAMIC_DEALLOC = 0, | |
482 | }; | |
483 | ||
d800ba12 ME |
484 | struct OpalMemoryErrorData { |
485 | enum OpalMemErr_Version version:8; /* 0x00 */ | |
486 | enum OpalMemErrType type:8; /* 0x01 */ | |
487 | __be16 flags; /* 0x02 */ | |
488 | uint8_t reserved_1[4]; /* 0x04 */ | |
489 | ||
490 | union { | |
491 | /* Memory Resilience corrected/uncorrected error info */ | |
492 | struct { | |
d7cf83fc ME |
493 | enum OpalMemErr_ResilErrType resil_err_type:8; |
494 | uint8_t reserved_1[7]; | |
495 | __be64 physical_address_start; | |
496 | __be64 physical_address_end; | |
d800ba12 ME |
497 | } resilience; |
498 | /* Dynamic memory deallocation error info */ | |
499 | struct { | |
d7cf83fc ME |
500 | enum OpalMemErr_DynErrType dyn_err_type:8; |
501 | uint8_t reserved_1[7]; | |
502 | __be64 physical_address_start; | |
503 | __be64 physical_address_end; | |
d800ba12 ME |
504 | } dyn_dealloc; |
505 | } u; | |
506 | }; | |
507 | ||
508 | /* HMI interrupt event */ | |
509 | enum OpalHMI_Version { | |
510 | OpalHMIEvt_V1 = 1, | |
c33e11d0 | 511 | OpalHMIEvt_V2 = 2, |
d800ba12 ME |
512 | }; |
513 | ||
514 | enum OpalHMI_Severity { | |
515 | OpalHMI_SEV_NO_ERROR = 0, | |
516 | OpalHMI_SEV_WARNING = 1, | |
517 | OpalHMI_SEV_ERROR_SYNC = 2, | |
518 | OpalHMI_SEV_FATAL = 3, | |
519 | }; | |
520 | ||
521 | enum OpalHMI_Disposition { | |
522 | OpalHMI_DISPOSITION_RECOVERED = 0, | |
523 | OpalHMI_DISPOSITION_NOT_RECOVERED = 1, | |
524 | }; | |
525 | ||
526 | enum OpalHMI_ErrType { | |
527 | OpalHMI_ERROR_MALFUNC_ALERT = 0, | |
528 | OpalHMI_ERROR_PROC_RECOV_DONE, | |
529 | OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, | |
530 | OpalHMI_ERROR_PROC_RECOV_MASKED, | |
531 | OpalHMI_ERROR_TFAC, | |
532 | OpalHMI_ERROR_TFMR_PARITY, | |
533 | OpalHMI_ERROR_HA_OVERFLOW_WARN, | |
534 | OpalHMI_ERROR_XSCOM_FAIL, | |
535 | OpalHMI_ERROR_XSCOM_DONE, | |
536 | OpalHMI_ERROR_SCOM_FIR, | |
537 | OpalHMI_ERROR_DEBUG_TRIG_FIR, | |
538 | OpalHMI_ERROR_HYP_RESOURCE, | |
d7cf83fc | 539 | OpalHMI_ERROR_CAPP_RECOVERY, |
d800ba12 ME |
540 | }; |
541 | ||
c33e11d0 MS |
542 | enum OpalHMI_XstopType { |
543 | CHECKSTOP_TYPE_UNKNOWN = 0, | |
544 | CHECKSTOP_TYPE_CORE = 1, | |
545 | CHECKSTOP_TYPE_NX = 2, | |
546 | }; | |
547 | ||
548 | enum OpalHMI_CoreXstopReason { | |
549 | CORE_CHECKSTOP_IFU_REGFILE = 0x00000001, | |
550 | CORE_CHECKSTOP_IFU_LOGIC = 0x00000002, | |
551 | CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004, | |
552 | CORE_CHECKSTOP_ISU_REGFILE = 0x00000008, | |
553 | CORE_CHECKSTOP_ISU_LOGIC = 0x00000010, | |
554 | CORE_CHECKSTOP_FXU_LOGIC = 0x00000020, | |
555 | CORE_CHECKSTOP_VSU_LOGIC = 0x00000040, | |
556 | CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080, | |
557 | CORE_CHECKSTOP_LSU_REGFILE = 0x00000100, | |
558 | CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200, | |
559 | CORE_CHECKSTOP_LSU_LOGIC = 0x00000400, | |
560 | CORE_CHECKSTOP_PC_LOGIC = 0x00000800, | |
561 | CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000, | |
562 | CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000, | |
563 | CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000, | |
564 | CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000, | |
565 | CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000, | |
566 | }; | |
567 | ||
568 | enum OpalHMI_NestAccelXstopReason { | |
569 | NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001, | |
570 | NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002, | |
571 | NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004, | |
572 | NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008, | |
573 | NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010, | |
574 | NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020, | |
575 | NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040, | |
576 | NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080, | |
577 | NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100, | |
578 | NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200, | |
579 | NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400, | |
580 | NX_CHECKSTOP_DMA_CRB_UE = 0x00000800, | |
581 | NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000, | |
582 | NX_CHECKSTOP_PBI_ISN_UE = 0x00002000, | |
583 | }; | |
584 | ||
d800ba12 ME |
585 | struct OpalHMIEvent { |
586 | uint8_t version; /* 0x00 */ | |
587 | uint8_t severity; /* 0x01 */ | |
588 | uint8_t type; /* 0x02 */ | |
589 | uint8_t disposition; /* 0x03 */ | |
590 | uint8_t reserved_1[4]; /* 0x04 */ | |
591 | ||
592 | __be64 hmer; | |
593 | /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ | |
594 | __be64 tfmr; | |
c33e11d0 MS |
595 | |
596 | /* version 2 and later */ | |
597 | union { | |
598 | /* | |
599 | * checkstop info (Core/NX). | |
600 | * Valid for OpalHMI_ERROR_MALFUNC_ALERT. | |
601 | */ | |
602 | struct { | |
603 | uint8_t xstop_type; /* enum OpalHMI_XstopType */ | |
604 | uint8_t reserved_1[3]; | |
605 | __be32 xstop_reason; | |
606 | union { | |
607 | __be32 pir; /* for CHECKSTOP_TYPE_CORE */ | |
608 | __be32 chip_id; /* for CHECKSTOP_TYPE_NX */ | |
609 | } u; | |
610 | } xstop_error; | |
611 | } u; | |
d800ba12 ME |
612 | }; |
613 | ||
614 | enum { | |
615 | OPAL_P7IOC_DIAG_TYPE_NONE = 0, | |
616 | OPAL_P7IOC_DIAG_TYPE_RGC = 1, | |
617 | OPAL_P7IOC_DIAG_TYPE_BI = 2, | |
618 | OPAL_P7IOC_DIAG_TYPE_CI = 3, | |
619 | OPAL_P7IOC_DIAG_TYPE_MISC = 4, | |
620 | OPAL_P7IOC_DIAG_TYPE_I2C = 5, | |
621 | OPAL_P7IOC_DIAG_TYPE_LAST = 6 | |
622 | }; | |
623 | ||
624 | struct OpalIoP7IOCErrorData { | |
625 | __be16 type; | |
626 | ||
627 | /* GEM */ | |
628 | __be64 gemXfir; | |
629 | __be64 gemRfir; | |
630 | __be64 gemRirqfir; | |
631 | __be64 gemMask; | |
632 | __be64 gemRwof; | |
633 | ||
634 | /* LEM */ | |
635 | __be64 lemFir; | |
636 | __be64 lemErrMask; | |
637 | __be64 lemAction0; | |
638 | __be64 lemAction1; | |
639 | __be64 lemWof; | |
640 | ||
641 | union { | |
642 | struct OpalIoP7IOCRgcErrorData { | |
643 | __be64 rgcStatus; /* 3E1C10 */ | |
644 | __be64 rgcLdcp; /* 3E1C18 */ | |
645 | }rgc; | |
646 | struct OpalIoP7IOCBiErrorData { | |
647 | __be64 biLdcp0; /* 3C0100, 3C0118 */ | |
648 | __be64 biLdcp1; /* 3C0108, 3C0120 */ | |
649 | __be64 biLdcp2; /* 3C0110, 3C0128 */ | |
650 | __be64 biFenceStatus; /* 3C0130, 3C0130 */ | |
651 | ||
d7cf83fc | 652 | uint8_t biDownbound; /* BI Downbound or Upbound */ |
d800ba12 ME |
653 | }bi; |
654 | struct OpalIoP7IOCCiErrorData { | |
655 | __be64 ciPortStatus; /* 3Dn008 */ | |
656 | __be64 ciPortLdcp; /* 3Dn010 */ | |
657 | ||
d7cf83fc | 658 | uint8_t ciPort; /* Index of CI port: 0/1 */ |
d800ba12 ME |
659 | }ci; |
660 | }; | |
661 | }; | |
662 | ||
663 | /** | |
664 | * This structure defines the overlay which will be used to store PHB error | |
665 | * data upon request. | |
666 | */ | |
667 | enum { | |
668 | OPAL_PHB_ERROR_DATA_VERSION_1 = 1, | |
669 | }; | |
670 | ||
671 | enum { | |
672 | OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, | |
a4b48ba9 RC |
673 | OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2, |
674 | OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3 | |
d800ba12 ME |
675 | }; |
676 | ||
677 | enum { | |
678 | OPAL_P7IOC_NUM_PEST_REGS = 128, | |
a4b48ba9 RC |
679 | OPAL_PHB3_NUM_PEST_REGS = 256, |
680 | OPAL_PHB4_NUM_PEST_REGS = 512 | |
d800ba12 ME |
681 | }; |
682 | ||
d800ba12 ME |
683 | struct OpalIoPhbErrorCommon { |
684 | __be32 version; | |
685 | __be32 ioType; | |
686 | __be32 len; | |
687 | }; | |
688 | ||
689 | struct OpalIoP7IOCPhbErrorData { | |
690 | struct OpalIoPhbErrorCommon common; | |
691 | ||
692 | __be32 brdgCtl; | |
693 | ||
694 | // P7IOC utl regs | |
695 | __be32 portStatusReg; | |
696 | __be32 rootCmplxStatus; | |
697 | __be32 busAgentStatus; | |
698 | ||
699 | // P7IOC cfg regs | |
700 | __be32 deviceStatus; | |
701 | __be32 slotStatus; | |
702 | __be32 linkStatus; | |
703 | __be32 devCmdStatus; | |
704 | __be32 devSecStatus; | |
705 | ||
706 | // cfg AER regs | |
707 | __be32 rootErrorStatus; | |
708 | __be32 uncorrErrorStatus; | |
709 | __be32 corrErrorStatus; | |
710 | __be32 tlpHdr1; | |
711 | __be32 tlpHdr2; | |
712 | __be32 tlpHdr3; | |
713 | __be32 tlpHdr4; | |
714 | __be32 sourceId; | |
715 | ||
716 | __be32 rsv3; | |
717 | ||
718 | // Record data about the call to allocate a buffer. | |
719 | __be64 errorClass; | |
720 | __be64 correlator; | |
721 | ||
722 | //P7IOC MMIO Error Regs | |
723 | __be64 p7iocPlssr; // n120 | |
724 | __be64 p7iocCsr; // n110 | |
725 | __be64 lemFir; // nC00 | |
726 | __be64 lemErrorMask; // nC18 | |
727 | __be64 lemWOF; // nC40 | |
728 | __be64 phbErrorStatus; // nC80 | |
729 | __be64 phbFirstErrorStatus; // nC88 | |
730 | __be64 phbErrorLog0; // nCC0 | |
731 | __be64 phbErrorLog1; // nCC8 | |
732 | __be64 mmioErrorStatus; // nD00 | |
733 | __be64 mmioFirstErrorStatus; // nD08 | |
734 | __be64 mmioErrorLog0; // nD40 | |
735 | __be64 mmioErrorLog1; // nD48 | |
736 | __be64 dma0ErrorStatus; // nD80 | |
737 | __be64 dma0FirstErrorStatus; // nD88 | |
738 | __be64 dma0ErrorLog0; // nDC0 | |
739 | __be64 dma0ErrorLog1; // nDC8 | |
740 | __be64 dma1ErrorStatus; // nE00 | |
741 | __be64 dma1FirstErrorStatus; // nE08 | |
742 | __be64 dma1ErrorLog0; // nE40 | |
743 | __be64 dma1ErrorLog1; // nE48 | |
744 | __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; | |
745 | __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; | |
746 | }; | |
747 | ||
748 | struct OpalIoPhb3ErrorData { | |
749 | struct OpalIoPhbErrorCommon common; | |
750 | ||
751 | __be32 brdgCtl; | |
752 | ||
753 | /* PHB3 UTL regs */ | |
754 | __be32 portStatusReg; | |
755 | __be32 rootCmplxStatus; | |
756 | __be32 busAgentStatus; | |
757 | ||
758 | /* PHB3 cfg regs */ | |
759 | __be32 deviceStatus; | |
760 | __be32 slotStatus; | |
761 | __be32 linkStatus; | |
762 | __be32 devCmdStatus; | |
763 | __be32 devSecStatus; | |
764 | ||
765 | /* cfg AER regs */ | |
766 | __be32 rootErrorStatus; | |
767 | __be32 uncorrErrorStatus; | |
768 | __be32 corrErrorStatus; | |
769 | __be32 tlpHdr1; | |
770 | __be32 tlpHdr2; | |
771 | __be32 tlpHdr3; | |
772 | __be32 tlpHdr4; | |
773 | __be32 sourceId; | |
774 | ||
775 | __be32 rsv3; | |
776 | ||
777 | /* Record data about the call to allocate a buffer */ | |
778 | __be64 errorClass; | |
779 | __be64 correlator; | |
780 | ||
d7cf83fc | 781 | /* PHB3 MMIO Error Regs */ |
d800ba12 ME |
782 | __be64 nFir; /* 000 */ |
783 | __be64 nFirMask; /* 003 */ | |
784 | __be64 nFirWOF; /* 008 */ | |
d800ba12 ME |
785 | __be64 phbPlssr; /* 120 */ |
786 | __be64 phbCsr; /* 110 */ | |
787 | __be64 lemFir; /* C00 */ | |
788 | __be64 lemErrorMask; /* C18 */ | |
789 | __be64 lemWOF; /* C40 */ | |
790 | __be64 phbErrorStatus; /* C80 */ | |
791 | __be64 phbFirstErrorStatus; /* C88 */ | |
792 | __be64 phbErrorLog0; /* CC0 */ | |
793 | __be64 phbErrorLog1; /* CC8 */ | |
794 | __be64 mmioErrorStatus; /* D00 */ | |
795 | __be64 mmioFirstErrorStatus; /* D08 */ | |
796 | __be64 mmioErrorLog0; /* D40 */ | |
797 | __be64 mmioErrorLog1; /* D48 */ | |
798 | __be64 dma0ErrorStatus; /* D80 */ | |
799 | __be64 dma0FirstErrorStatus; /* D88 */ | |
800 | __be64 dma0ErrorLog0; /* DC0 */ | |
801 | __be64 dma0ErrorLog1; /* DC8 */ | |
802 | __be64 dma1ErrorStatus; /* E00 */ | |
803 | __be64 dma1FirstErrorStatus; /* E08 */ | |
804 | __be64 dma1ErrorLog0; /* E40 */ | |
805 | __be64 dma1ErrorLog1; /* E48 */ | |
806 | __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; | |
807 | __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; | |
808 | }; | |
809 | ||
a4b48ba9 RC |
810 | struct OpalIoPhb4ErrorData { |
811 | struct OpalIoPhbErrorCommon common; | |
812 | ||
813 | __be32 brdgCtl; | |
814 | ||
815 | /* PHB4 cfg regs */ | |
816 | __be32 deviceStatus; | |
817 | __be32 slotStatus; | |
818 | __be32 linkStatus; | |
819 | __be32 devCmdStatus; | |
820 | __be32 devSecStatus; | |
821 | ||
822 | /* cfg AER regs */ | |
823 | __be32 rootErrorStatus; | |
824 | __be32 uncorrErrorStatus; | |
825 | __be32 corrErrorStatus; | |
826 | __be32 tlpHdr1; | |
827 | __be32 tlpHdr2; | |
828 | __be32 tlpHdr3; | |
829 | __be32 tlpHdr4; | |
830 | __be32 sourceId; | |
831 | ||
832 | /* PHB4 ETU Error Regs */ | |
833 | __be64 nFir; /* 000 */ | |
834 | __be64 nFirMask; /* 003 */ | |
835 | __be64 nFirWOF; /* 008 */ | |
836 | __be64 phbPlssr; /* 120 */ | |
837 | __be64 phbCsr; /* 110 */ | |
838 | __be64 lemFir; /* C00 */ | |
839 | __be64 lemErrorMask; /* C18 */ | |
840 | __be64 lemWOF; /* C40 */ | |
841 | __be64 phbErrorStatus; /* C80 */ | |
842 | __be64 phbFirstErrorStatus; /* C88 */ | |
843 | __be64 phbErrorLog0; /* CC0 */ | |
844 | __be64 phbErrorLog1; /* CC8 */ | |
845 | __be64 phbTxeErrorStatus; /* D00 */ | |
846 | __be64 phbTxeFirstErrorStatus; /* D08 */ | |
847 | __be64 phbTxeErrorLog0; /* D40 */ | |
848 | __be64 phbTxeErrorLog1; /* D48 */ | |
849 | __be64 phbRxeArbErrorStatus; /* D80 */ | |
850 | __be64 phbRxeArbFirstErrorStatus; /* D88 */ | |
851 | __be64 phbRxeArbErrorLog0; /* DC0 */ | |
852 | __be64 phbRxeArbErrorLog1; /* DC8 */ | |
853 | __be64 phbRxeMrgErrorStatus; /* E00 */ | |
854 | __be64 phbRxeMrgFirstErrorStatus; /* E08 */ | |
855 | __be64 phbRxeMrgErrorLog0; /* E40 */ | |
856 | __be64 phbRxeMrgErrorLog1; /* E48 */ | |
857 | __be64 phbRxeTceErrorStatus; /* E80 */ | |
858 | __be64 phbRxeTceFirstErrorStatus; /* E88 */ | |
859 | __be64 phbRxeTceErrorLog0; /* EC0 */ | |
860 | __be64 phbRxeTceErrorLog1; /* EC8 */ | |
861 | ||
862 | /* PHB4 REGB Error Regs */ | |
863 | __be64 phbPblErrorStatus; /* 1900 */ | |
864 | __be64 phbPblFirstErrorStatus; /* 1908 */ | |
865 | __be64 phbPblErrorLog0; /* 1940 */ | |
866 | __be64 phbPblErrorLog1; /* 1948 */ | |
867 | __be64 phbPcieDlpErrorLog1; /* 1AA0 */ | |
868 | __be64 phbPcieDlpErrorLog2; /* 1AA8 */ | |
869 | __be64 phbPcieDlpErrorStatus; /* 1AB0 */ | |
870 | __be64 phbRegbErrorStatus; /* 1C00 */ | |
871 | __be64 phbRegbFirstErrorStatus; /* 1C08 */ | |
872 | __be64 phbRegbErrorLog0; /* 1C40 */ | |
873 | __be64 phbRegbErrorLog1; /* 1C48 */ | |
874 | ||
875 | __be64 pestA[OPAL_PHB4_NUM_PEST_REGS]; | |
876 | __be64 pestB[OPAL_PHB4_NUM_PEST_REGS]; | |
877 | }; | |
878 | ||
d800ba12 ME |
879 | enum { |
880 | OPAL_REINIT_CPUS_HILE_BE = (1 << 0), | |
881 | OPAL_REINIT_CPUS_HILE_LE = (1 << 1), | |
1c0eaf0f BH |
882 | |
883 | /* These two define the base MMU mode of the host on P9 | |
884 | * | |
885 | * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still | |
886 | * create hash guests in "radix" mode with care (full core | |
887 | * switch only). | |
888 | */ | |
889 | OPAL_REINIT_CPUS_MMU_HASH = (1 << 2), | |
890 | OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3), | |
d800ba12 ME |
891 | }; |
892 | ||
893 | typedef struct oppanel_line { | |
d7cf83fc ME |
894 | __be64 line; |
895 | __be64 line_len; | |
d800ba12 ME |
896 | } oppanel_line_t; |
897 | ||
0d7cd855 JK |
898 | enum opal_prd_msg_type { |
899 | OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */ | |
900 | OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */ | |
901 | OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */ | |
902 | OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */ | |
903 | OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */ | |
904 | OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */ | |
905 | }; | |
906 | ||
907 | struct opal_prd_msg_header { | |
908 | uint8_t type; | |
909 | uint8_t pad[1]; | |
910 | __be16 size; | |
911 | }; | |
912 | ||
913 | struct opal_prd_msg; | |
914 | ||
196ba2d5 SB |
915 | #define OCC_RESET 0 |
916 | #define OCC_LOAD 1 | |
917 | #define OCC_THROTTLE 2 | |
918 | #define OCC_MAX_THROTTLE_STATUS 5 | |
919 | ||
920 | struct opal_occ_msg { | |
921 | __be64 type; | |
922 | __be64 chip; | |
923 | __be64 throttle_status; | |
924 | }; | |
925 | ||
d800ba12 ME |
926 | /* |
927 | * SG entries | |
928 | * | |
929 | * WARNING: The current implementation requires each entry | |
930 | * to represent a block that is 4k aligned *and* each block | |
931 | * size except the last one in the list to be as well. | |
932 | */ | |
933 | struct opal_sg_entry { | |
934 | __be64 data; | |
935 | __be64 length; | |
936 | }; | |
937 | ||
d7cf83fc | 938 | /* |
027dfac6 | 939 | * Candidate image SG list. |
d7cf83fc ME |
940 | * |
941 | * length = VER | length | |
942 | */ | |
d800ba12 ME |
943 | struct opal_sg_list { |
944 | __be64 length; | |
945 | __be64 next; | |
946 | struct opal_sg_entry entry[]; | |
947 | }; | |
948 | ||
949 | /* | |
950 | * Dump region ID range usable by the OS | |
951 | */ | |
952 | #define OPAL_DUMP_REGION_HOST_START 0x80 | |
953 | #define OPAL_DUMP_REGION_LOG_BUF 0x80 | |
954 | #define OPAL_DUMP_REGION_HOST_END 0xFF | |
955 | ||
d7cf83fc ME |
956 | /* CAPI modes for PHB */ |
957 | enum { | |
958 | OPAL_PHB_CAPI_MODE_PCIE = 0, | |
959 | OPAL_PHB_CAPI_MODE_CAPI = 1, | |
960 | OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, | |
961 | OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, | |
b385c9e9 | 962 | OPAL_PHB_CAPI_MODE_DMA = 4, |
3ced8d73 | 963 | OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5, |
d7cf83fc ME |
964 | }; |
965 | ||
d800ba12 ME |
966 | /* OPAL I2C request */ |
967 | struct opal_i2c_request { | |
968 | uint8_t type; | |
969 | #define OPAL_I2C_RAW_READ 0 | |
970 | #define OPAL_I2C_RAW_WRITE 1 | |
971 | #define OPAL_I2C_SM_READ 2 | |
972 | #define OPAL_I2C_SM_WRITE 3 | |
973 | uint8_t flags; | |
974 | #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ | |
975 | uint8_t subaddr_sz; /* Max 4 */ | |
976 | uint8_t reserved; | |
977 | __be16 addr; /* 7 or 10 bit address */ | |
978 | __be16 reserved2; | |
979 | __be32 subaddr; /* Sub-address if any */ | |
980 | __be32 size; /* Data size */ | |
981 | __be64 buffer_ra; /* Buffer real address */ | |
982 | }; | |
983 | ||
3b476aad VP |
984 | /* |
985 | * EPOW status sharing (OPAL and the host) | |
986 | * | |
987 | * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX | |
988 | * with individual elements being 16 bits wide to fetch the system | |
989 | * wide EPOW status. Each element in the buffer will contain the | |
990 | * EPOW status in it's bit representation for a particular EPOW sub | |
027dfac6 | 991 | * class as defined here. So multiple detailed EPOW status bits |
3b476aad VP |
992 | * specific for any sub class can be represented in a single buffer |
993 | * element as it's bit representation. | |
994 | */ | |
995 | ||
996 | /* System EPOW type */ | |
997 | enum OpalSysEpow { | |
998 | OPAL_SYSEPOW_POWER = 0, /* Power EPOW */ | |
999 | OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */ | |
1000 | OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */ | |
1001 | OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */ | |
1002 | }; | |
1003 | ||
1004 | /* Power EPOW */ | |
1005 | enum OpalSysPower { | |
1006 | OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */ | |
1007 | OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */ | |
1008 | OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */ | |
1009 | OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */ | |
1010 | }; | |
1011 | ||
1012 | /* Temperature EPOW */ | |
1013 | enum OpalSysTemp { | |
1014 | OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */ | |
1015 | OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */ | |
1016 | OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */ | |
1017 | }; | |
1018 | ||
1019 | /* Cooling EPOW */ | |
1020 | enum OpalSysCooling { | |
1021 | OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */ | |
1022 | }; | |
1023 | ||
e784b649 MS |
1024 | /* Argument to OPAL_CEC_REBOOT2() */ |
1025 | enum { | |
1026 | OPAL_REBOOT_NORMAL = 0, | |
1027 | OPAL_REBOOT_PLATFORM_ERROR = 1, | |
1028 | }; | |
1029 | ||
69c592ed BH |
1030 | /* Argument to OPAL_PCI_TCE_KILL */ |
1031 | enum { | |
1032 | OPAL_PCI_TCE_KILL_PAGES, | |
1033 | OPAL_PCI_TCE_KILL_PE, | |
1034 | OPAL_PCI_TCE_KILL_ALL, | |
1035 | }; | |
1036 | ||
eeea1a43 BH |
1037 | /* The xive operation mode indicates the active "API" and |
1038 | * corresponds to the "mode" parameter of the opal_xive_reset() | |
1039 | * call | |
1040 | */ | |
1041 | enum { | |
1042 | OPAL_XIVE_MODE_EMU = 0, | |
1043 | OPAL_XIVE_MODE_EXPL = 1, | |
1044 | }; | |
1045 | ||
1046 | /* Flags for OPAL_XIVE_GET_IRQ_INFO */ | |
1047 | enum { | |
1048 | OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001, | |
1049 | OPAL_XIVE_IRQ_STORE_EOI = 0x00000002, | |
1050 | OPAL_XIVE_IRQ_LSI = 0x00000004, | |
1051 | OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, | |
1052 | OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, | |
1053 | OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, | |
1054 | }; | |
1055 | ||
1056 | /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */ | |
1057 | enum { | |
1058 | OPAL_XIVE_EQ_ENABLED = 0x00000001, | |
1059 | OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002, | |
1060 | OPAL_XIVE_EQ_ESCALATE = 0x00000004, | |
1061 | }; | |
1062 | ||
1063 | /* Flags for OPAL_XIVE_GET/SET_VP_INFO */ | |
1064 | enum { | |
1065 | OPAL_XIVE_VP_ENABLED = 0x00000001, | |
1066 | }; | |
1067 | ||
1068 | /* "Any chip" replacement for chip ID for allocation functions */ | |
1069 | enum { | |
1070 | OPAL_XIVE_ANY_CHIP = 0xffffffff, | |
1071 | }; | |
1072 | ||
1073 | /* Xive sync options */ | |
1074 | enum { | |
1075 | /* This bits are cumulative, arg is a girq */ | |
1076 | XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */ | |
1077 | XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */ | |
1078 | }; | |
1079 | ||
1080 | /* Dump options */ | |
1081 | enum { | |
1082 | XIVE_DUMP_TM_HYP = 0, | |
1083 | XIVE_DUMP_TM_POOL = 1, | |
1084 | XIVE_DUMP_TM_OS = 2, | |
1085 | XIVE_DUMP_TM_USER = 3, | |
1086 | XIVE_DUMP_VP = 4, | |
1087 | XIVE_DUMP_EMU_STATE = 5, | |
1088 | }; | |
1089 | ||
c7ea8292 MS |
1090 | /* "type" argument options for OPAL_IMC_COUNTERS_* calls */ |
1091 | enum { | |
1092 | OPAL_IMC_COUNTERS_NEST = 1, | |
1093 | OPAL_IMC_COUNTERS_CORE = 2, | |
1094 | }; | |
1095 | ||
1096 | ||
d800ba12 ME |
1097 | #endif /* __ASSEMBLY__ */ |
1098 | ||
1099 | #endif /* __OPAL_API_H */ |