[mirror_ubuntu-kernels.git] / arch / powerpc / include / asm / opal.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * PowerNV OPAL definitions.
 *
 * Copyright 2011 IBM Corp.
 */

#ifndef _ASM_POWERPC_OPAL_H
#define _ASM_POWERPC_OPAL_H

#include <asm/opal-api.h>

#ifndef __ASSEMBLY__

#include <linux/notifier.h>

/* We calculate number of sg entries based on PAGE_SIZE */
#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))

/* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
#define OPAL_BUSY_DELAY_MS	10

/* /sys/firmware/opal */
extern struct kobject *opal_kobj;

/* /ibm,opal */
extern struct device_node *opal_node;

/* API functions */
int64_t opal_invalid_call(void);
int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
			uint64_t bdf);
int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
			uint64_t lpcr);
int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
			uint64_t addr, uint64_t PE_mask);
int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
				uint64_t PE_handle);
int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
			uint64_t rate_phys, uint32_t size);
int64_t opal_console_write(int64_t term_number, __be64 *length,
			   const uint8_t *buffer);
int64_t opal_console_read(int64_t term_number, __be64 *length,
			  uint8_t *buffer);
int64_t opal_console_write_buffer_space(int64_t term_number,
					__be64 *length);
int64_t opal_console_flush(int64_t term_number);
int64_t opal_rtc_read(__be32 *year_month_day,
		      __be64 *hour_minute_second_millisecond);
int64_t opal_rtc_write(uint32_t year_month_day,
		       uint64_t hour_minute_second_millisecond);
int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
		       uint32_t hour_min);
int64_t opal_cec_power_down(uint64_t request);
int64_t opal_cec_reboot(void);
int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
int64_t opal_poll_events(__be64 *outstanding_event_mask);
int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
				    uint64_t tce_mem_size);
int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
				    uint64_t tce_mem_size);
int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
				  uint64_t offset, uint8_t *data);
int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
				       uint64_t offset, __be16 *data);
int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
				  uint64_t offset, __be32 *data);
int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
				   uint64_t offset, uint8_t data);
int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
					uint64_t offset, uint16_t data);
int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
				   uint64_t offset, uint32_t data);
int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
int64_t opal_register_exception_handler(uint64_t opal_exception,
					uint64_t handler_address,
					uint64_t glue_cache_line);
int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
				   uint8_t *freeze_state,
				   __be16 *pci_error_type,
				   __be64 *phb_status);
int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
				  uint64_t eeh_action_token);
int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
				uint64_t eeh_action_token);
int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
			    uint32_t func, uint64_t addr, uint64_t mask);
int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);


int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
				 uint16_t window_num, uint16_t enable);
int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
				    uint16_t window_num,
				    uint64_t starting_real_address,
				    uint64_t starting_pci_address,
				    uint64_t size);
int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
				    uint16_t window_type, uint16_t window_num,
				    uint16_t segment_num);
int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
				      uint64_t ivt_addr, uint64_t ivt_len,
				      uint64_t reject_array_addr,
				      uint64_t peltv_addr);
int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
			uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
			uint8_t pe_action);
int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
			   uint8_t state);
int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
				uint32_t state);
int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
				  uint8_t *p_bit, uint8_t *q_bit);
int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
				  uint8_t p_bit, uint8_t q_bit);
int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
			     uint32_t xive_num);
int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
			     __be32 *interrupt_source_number);
int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
			uint8_t msi_range, __be32 *msi_address,
			__be32 *message_data);
int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
			uint32_t xive_num, uint8_t msi_range,
			__be64 *msi_address, __be32 *message_data);
int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
				   uint16_t tce_levels, uint64_t tce_table_addr,
				   uint64_t tce_table_size, uint64_t tce_page_size);
int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
					uint16_t dma_window_number, uint64_t pci_start_addr,
					uint64_t pci_mem_size);
int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);

int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
				   uint64_t diag_buffer_len);
int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
				   uint64_t diag_buffer_len);
int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
				    uint64_t diag_buffer_len);
int64_t opal_pci_fence_phb(uint64_t phb_id);
int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
int64_t opal_get_dpo_status(__be64 *dpo_timeout);
int64_t opal_set_system_attention_led(uint8_t led_action);
int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
			    __be16 *pci_error_type, __be16 *severity);
int64_t opal_pci_poll(uint64_t id);
int64_t opal_return_cpu(void);
int64_t opal_check_token(uint64_t token);
int64_t opal_reinit_cpus(uint64_t flags);

int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);

int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
		       uint32_t addr, uint32_t data, uint32_t sz);
int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
		      uint32_t addr, __be32 *data, uint32_t sz);

int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
int64_t opal_send_ack_elog(uint64_t log_id);
void opal_resend_pending_logs(void);

int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
int64_t opal_manage_flash(uint8_t op);
int64_t opal_update_flash(uint64_t blk_list);
int64_t opal_dump_init(uint8_t dump_type);
int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
int64_t opal_dump_ack(uint32_t dump_id);
int64_t opal_dump_resend_notification(void);

int64_t opal_get_msg(uint64_t buffer, uint64_t size);
int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
					uint64_t num_lines);
int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
int64_t opal_sync_host_reboot(void);
int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
		uint64_t length);
int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
		uint64_t length);
int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
int64_t opal_handle_hmi(void);
int64_t opal_handle_hmi2(__be64 *out_flags);
int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
int64_t opal_unregister_dump_region(uint32_t id);
int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
		uint64_t msg_len);
int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
		uint64_t *msg_len);
int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
			 struct opal_i2c_request *oreq);
int64_t opal_prd_msg(struct opal_prd_msg *msg);
int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
			  __be64 *led_value, __be64 *max_led_type);
int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
			  const u64 led_value, __be64 *max_led_type);

int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
		uint64_t size, uint64_t token);
int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
		uint64_t size, uint64_t token);
int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
		uint64_t token);
int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
				 uint64_t data);
int64_t opal_pci_poll2(uint64_t id, uint64_t data);

int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
int64_t opal_int_set_cppr(uint8_t cppr);
int64_t opal_int_eoi(uint32_t xirr);
int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
			  uint32_t pe_num, uint32_t tce_size,
			  uint64_t dma_addr, uint32_t npages);
int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
int64_t opal_xive_reset(uint64_t version);
int64_t opal_xive_get_irq_info(uint32_t girq,
			       __be64 *out_flags,
			       __be64 *out_eoi_page,
			       __be64 *out_trig_page,
			       __be32 *out_esb_shift,
			       __be32 *out_src_chip);
int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
				 uint8_t *out_prio, __be32 *out_lirq);
int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
				 uint32_t lirq);
int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
				 __be64 *out_qpage,
				 __be64 *out_qsize,
				 __be64 *out_qeoi_page,
				 __be32 *out_escalate_irq,
				 __be64 *out_qflags);
int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
				 uint64_t qpage,
				 uint64_t qsize,
				 uint64_t qflags);
int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
int64_t opal_xive_free_vp_block(uint64_t vp);
int64_t opal_xive_get_vp_info(uint64_t vp,
			      __be64 *out_flags,
			      __be64 *out_cam_value,
			      __be64 *out_report_cl_pair,
			      __be32 *out_chip_id);
int64_t opal_xive_set_vp_info(uint64_t vp,
			      uint64_t flags,
			      uint64_t report_cl_pair);
int64_t opal_xive_allocate_irq(uint32_t chip_id);
int64_t opal_xive_free_irq(uint32_t girq);
int64_t opal_xive_sync(uint32_t type, uint32_t id);
int64_t opal_xive_dump(uint32_t type, uint32_t id);
int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
				  __be32 *out_qtoggle,
				  __be32 *out_qindex);
int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
				  uint32_t qtoggle,
				  uint32_t qindex);
int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
			uint64_t desc, uint16_t pe_number);

int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
							uint64_t cpu_pir);
int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);

int opal_get_powercap(u32 handle, int token, u32 *pcap);
int opal_set_powercap(u32 handle, int token, u32 pcap);
int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
int opal_sensor_group_clear(u32 group_hndl, int token);
int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);

s64 opal_signal_system_reset(s32 cpu);
s64 opal_quiesce(u64 shutdown_type, s32 cpu);

/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
				   int depth, void *data);
extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
				 const char *uname, int depth, void *data);
extern void opal_configure_cores(void);

extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
extern int opal_flush_chars(uint32_t vtermno, bool wait);
extern int opal_flush_console(uint32_t vtermno);

extern void hvc_opal_init_early(void);

extern int opal_notifier_register(struct notifier_block *nb);
extern int opal_notifier_unregister(struct notifier_block *nb);

extern int opal_message_notifier_register(enum opal_msg_type msg_type,
						struct notifier_block *nb);
extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
					    struct notifier_block *nb);
extern void opal_notifier_enable(void);
extern void opal_notifier_disable(void);
extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);

extern int opal_async_get_token_interruptible(void);
extern int opal_async_release_token(int token);
extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
extern int opal_async_wait_response_interruptible(uint64_t token,
		struct opal_msg *msg);
extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
extern int sensor_group_enable(u32 grp_hndl, bool enable);

struct rtc_time;
extern time64_t opal_get_boot_time(void);
extern void opal_nvram_init(void);
extern void opal_flash_update_init(void);
extern void opal_flash_update_print_message(void);
extern int opal_elog_init(void);
extern void opal_platform_dump_init(void);
extern void opal_sys_param_init(void);
extern void opal_msglog_init(void);
extern void opal_msglog_sysfs_init(void);
extern int opal_async_comp_init(void);
extern int opal_sensor_init(void);
extern int opal_hmi_handler_init(void);
extern int opal_event_init(void);
int opal_power_control_init(void);

extern int opal_machine_check(struct pt_regs *regs);
extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
extern int opal_hmi_exception_early(struct pt_regs *regs);
extern int opal_hmi_exception_early2(struct pt_regs *regs);
extern int opal_handle_hmi_exception(struct pt_regs *regs);

extern void opal_shutdown(void);
extern int opal_resync_timebase(void);

extern void opal_lpc_init(void);

extern void opal_kmsg_init(void);

extern int opal_event_request(unsigned int opal_event_nr);

struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
					     unsigned long vmalloc_size);
void opal_free_sg_list(struct opal_sg_list *sg);

extern int opal_error_code(int rc);

ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);

static inline int opal_get_async_rc(struct opal_msg msg)
{
	if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
		return OPAL_PARAMETER;
	else
		return be64_to_cpu(msg.params[1]);
}

void opal_wake_poller(void);

void opal_powercap_init(void);
void opal_psr_init(void);
void opal_sensor_groups_init(void);

#endif /* __ASSEMBLY__ */

#endif /* _ASM_POWERPC_OPAL_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
27f44888 BH	2	/*
	3	* PowerNV OPAL definitions.
	4	*
	5	* Copyright 2011 IBM Corp.
27f44888 BH	6	*/
27f44888 BH	7
d800ba12 ME	8	#ifndef _ASM_POWERPC_OPAL_H
d800ba12 ME	9	#define _ASM_POWERPC_OPAL_H
27f44888	10
d800ba12	11	#include <asm/opal-api.h>
8eb8ac89	12
14a43e69 BH	13	#ifndef __ASSEMBLY__
14a43e69 BH	14
bfd25d72 MN	15	#include <linux/notifier.h>
bfd25d72 MN	16
d800ba12 ME	17	/* We calculate number of sg entries based on PAGE_SIZE */
d800ba12 ME	18	#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
47083450	19
34dd25de NP	20	/* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
	21	#define OPAL_BUSY_DELAY_MS 10
	22
6f68b5e2 VH	23	/* /sys/firmware/opal */
	24	extern struct kobject *opal_kobj;
	25
bfc36894 JS	26	/* /ibm,opal */
	27	extern struct device_node *opal_node;
	28
14a43e69	29	/* API functions */
e28b05e7	30	int64_t opal_invalid_call(void);
1ab66d1f AP	31	int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
	32	int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
	33	uint64_t bdf);
	34	int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
	35	uint64_t lpcr);
74d656d2 FB	36	int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
	37	uint64_t addr, uint64_t PE_mask);
	38	int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
	39	uint64_t PE_handle);
	40	int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
	41	uint64_t rate_phys, uint32_t size);
4f89363b	42	int64_t opal_console_write(int64_t term_number, __be64 *length,
14a43e69	43	const uint8_t *buffer);
4f89363b	44	int64_t opal_console_read(int64_t term_number, __be64 *length,
14a43e69 BH	45	uint8_t *buffer);
14a43e69 BH	46	int64_t opal_console_write_buffer_space(int64_t term_number,
4f89363b	47	__be64 *length);
c88c5d43	48	int64_t opal_console_flush(int64_t term_number);
6feff6d4 AB	49	int64_t opal_rtc_read(__be32 *year_month_day,
6feff6d4 AB	50	__be64 *hour_minute_second_millisecond);
14a43e69 BH	51	int64_t opal_rtc_write(uint32_t year_month_day,
14a43e69 BH	52	uint64_t hour_minute_second_millisecond);
16b1d26e NG	53	int64_t opal_tpo_read(uint64_t token, __be32 year_mon_day, __be32 hour_min);
	54	int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
	55	uint32_t hour_min);
14a43e69 BH	56	int64_t opal_cec_power_down(uint64_t request);
14a43e69 BH	57	int64_t opal_cec_reboot(void);
b746e3e0	58	int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
14a43e69 BH	59	int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
14a43e69 BH	60	int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
5e4da530	61	int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
4f89363b	62	int64_t opal_poll_events(__be64 *outstanding_event_mask);
14a43e69 BH	63	int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
	64	uint64_t tce_mem_size);
	65	int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
	66	uint64_t tce_mem_size);
	67	int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
	68	uint64_t offset, uint8_t *data);
	69	int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
5e4da530	70	uint64_t offset, __be16 *data);
14a43e69	71	int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
5e4da530	72	uint64_t offset, __be32 *data);
14a43e69 BH	73	int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
	74	uint64_t offset, uint8_t data);
	75	int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
	76	uint64_t offset, uint16_t data);
	77	int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
	78	uint64_t offset, uint32_t data);
	79	int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
5e4da530	80	int64_t opal_get_xive(uint32_t isn, __be16 server, uint8_t priority);
14a43e69 BH	81	int64_t opal_register_exception_handler(uint64_t opal_exception,
	82	uint64_t handler_address,
	83	uint64_t glue_cache_line);
	84	int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
	85	uint8_t *freeze_state,
5e4da530 AB	86	__be16 *pci_error_type,
5e4da530 AB	87	__be64 *phb_status);
14a43e69 BH	88	int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
14a43e69 BH	89	uint64_t eeh_action_token);
5ca27efb GS	90	int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
5ca27efb GS	91	uint64_t eeh_action_token);
5b642340 GS	92	int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
5b642340 GS	93	uint32_t func, uint64_t addr, uint64_t mask);
14a43e69 BH	94	int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
	95
	96
	97
	98	int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
	99	uint16_t window_num, uint16_t enable);
	100	int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
	101	uint16_t window_num,
	102	uint64_t starting_real_address,
	103	uint64_t starting_pci_address,
262af557	104	uint64_t size);
14a43e69 BH	105	int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
	106	uint16_t window_type, uint16_t window_num,
	107	uint16_t segment_num);
	108	int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
	109	uint64_t ivt_addr, uint64_t ivt_len,
	110	uint64_t reject_array_addr,
	111	uint64_t peltv_addr);
	112	int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
	113	uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
	114	uint8_t pe_action);
	115	int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
	116	uint8_t state);
	117	int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
	118	int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
	119	uint32_t state);
	120	int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
	121	uint8_t p_bit, uint8_t q_bit);
	122	int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
	123	uint8_t p_bit, uint8_t q_bit);
137436c9	124	int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
14a43e69 BH	125	int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
	126	uint32_t xive_num);
	127	int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
5e4da530	128	__be32 *interrupt_source_number);
14a43e69	129	int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
5e4da530 AB	130	uint8_t msi_range, __be32 *msi_address,
5e4da530 AB	131	__be32 *message_data);
14a43e69 BH	132	int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
14a43e69 BH	133	uint32_t xive_num, uint8_t msi_range,
5e4da530	134	__be64 msi_address, __be32 message_data);
14a43e69 BH	135	int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
	136	int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
	137	int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
	138	int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
	139	uint16_t tce_levels, uint64_t tce_table_addr,
	140	uint64_t tce_table_size, uint64_t tce_page_size);
	141	int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
	142	uint16_t dma_window_number, uint64_t pci_start_addr,
	143	uint64_t pci_mem_size);
ebe22531	144	int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
14a43e69	145
23773230 GS	146	int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
	147	uint64_t diag_buffer_len);
	148	int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
	149	uint64_t diag_buffer_len);
	150	int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
	151	uint64_t diag_buffer_len);
f11fe552	152	int64_t opal_pci_fence_phb(uint64_t phb_id);
9be3becc	153	int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
f11fe552 BH	154	int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
f11fe552 BH	155	int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
3b476aad VP	156	int64_t opal_get_epow_status(__be16 epow_status, __be16 num_epow_classes);
3b476aad VP	157	int64_t opal_get_dpo_status(__be64 *dpo_timeout);
f11fe552	158	int64_t opal_set_system_attention_led(uint8_t led_action);
ddf0322a GC	159	int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
ddf0322a GC	160	__be16 pci_error_type, __be16 severity);
ebe22531	161	int64_t opal_pci_poll(uint64_t id);
13906db6	162	int64_t opal_return_cpu(void);
bffe6bda	163	int64_t opal_check_token(uint64_t token);
4926616c	164	int64_t opal_reinit_cpus(uint64_t flags);
f11fe552	165
2f3f38e4 BH	166	int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
2f3f38e4 BH	167	int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
cc0efb57 BH	168
	169	int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
	170	uint32_t addr, uint32_t data, uint32_t sz);
	171	int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
803c2d2f	172	uint32_t addr, __be32 *data, uint32_t sz);
774fea1a	173
2bad7423	174	int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
14ad0c58	175	int64_t opal_get_elog_size(__be64 log_id, __be64 size, __be64 *elog_type);
774fea1a SS	176	int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
	177	int64_t opal_send_ack_elog(uint64_t log_id);
	178	void opal_resend_pending_logs(void);
	179
50bd6153 VH	180	int64_t opal_validate_flash(uint64_t buffer, uint32_t size, uint32_t result);
	181	int64_t opal_manage_flash(uint8_t op);
	182	int64_t opal_update_flash(uint64_t blk_list);
c7e64b9c	183	int64_t opal_dump_init(uint8_t dump_type);
2d6b63bb AB	184	int64_t opal_dump_info(__be32 dump_id, __be32 dump_size);
2d6b63bb AB	185	int64_t opal_dump_info2(__be32 dump_id, __be32 dump_size, __be32 *dump_type);
c7e64b9c SS	186	int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
	187	int64_t opal_dump_ack(uint32_t dump_id);
	188	int64_t opal_dump_resend_notification(void);
cc0efb57	189
2bad7423	190	int64_t opal_get_msg(uint64_t buffer, uint64_t size);
43a1dd9b SJS	191	int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
43a1dd9b SJS	192	uint64_t num_lines);
2bad7423	193	int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
f7d98d18	194	int64_t opal_sync_host_reboot(void);
4029cd66	195	int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
2bad7423	196	uint64_t length);
4029cd66	197	int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
2bad7423	198	uint64_t length);
9000c17d	199	int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
5cdcb01e	200	int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
0ef95b41	201	int64_t opal_handle_hmi(void);
de269129	202	int64_t opal_handle_hmi2(__be64 *out_flags);
b09c2ec4 VH	203	int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
b09c2ec4 VH	204	int64_t opal_unregister_dump_region(uint32_t id);
77b54e9f	205	int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
5703d2f4	206	int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
09521736	207	int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
d6a90bb8 PB	208	int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
d6a90bb8 PB	209	int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
608b286d JK	210	int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
	211	uint64_t msg_len);
	212	int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
	213	uint64_t *msg_len);
47083450 NG	214	int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
47083450 NG	215	struct opal_i2c_request *oreq);
0d7cd855	216	int64_t opal_prd_msg(struct opal_prd_msg *msg);
8a8d9181 AK	217	int64_t opal_leds_get_ind(char loc_code, __be64 led_mask,
	218	__be64 led_value, __be64 max_led_type);
	219	int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
	220	const u64 led_value, __be64 *max_led_type);
24366360	221
ed59190e CB	222	int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
	223	uint64_t size, uint64_t token);
	224	int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
	225	uint64_t size, uint64_t token);
	226	int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
	227	uint64_t token);
ea0d856c GS	228	int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
	229	int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
	230	int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
	231	int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
	232	uint64_t data);
	233	int64_t opal_pci_poll2(uint64_t id, uint64_t data);
ed59190e	234
9fedd3f8 BH	235	int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
	236	int64_t opal_int_set_cppr(uint8_t cppr);
	237	int64_t opal_int_eoi(uint32_t xirr);
	238	int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
69c592ed BH	239	int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
	240	uint32_t pe_num, uint32_t tce_size,
	241	uint64_t dma_addr, uint32_t npages);
1d0761d2	242	int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
eeea1a43 BH	243	int64_t opal_xive_reset(uint64_t version);
	244	int64_t opal_xive_get_irq_info(uint32_t girq,
	245	__be64 *out_flags,
	246	__be64 *out_eoi_page,
	247	__be64 *out_trig_page,
	248	__be32 *out_esb_shift,
	249	__be32 *out_src_chip);
	250	int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
	251	uint8_t out_prio, __be32 out_lirq);
	252	int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
	253	uint32_t lirq);
	254	int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
	255	__be64 *out_qpage,
	256	__be64 *out_qsize,
	257	__be64 *out_qeoi_page,
	258	__be32 *out_escalate_irq,
	259	__be64 *out_qflags);
	260	int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
	261	uint64_t qpage,
	262	uint64_t qsize,
	263	uint64_t qflags);
	264	int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
	265	int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
	266	int64_t opal_xive_free_vp_block(uint64_t vp);
	267	int64_t opal_xive_get_vp_info(uint64_t vp,
	268	__be64 *out_flags,
	269	__be64 *out_cam_value,
	270	__be64 *out_report_cl_pair,
	271	__be32 *out_chip_id);
	272	int64_t opal_xive_set_vp_info(uint64_t vp,
	273	uint64_t flags,
	274	uint64_t report_cl_pair);
	275	int64_t opal_xive_allocate_irq(uint32_t chip_id);
	276	int64_t opal_xive_free_irq(uint32_t girq);
	277	int64_t opal_xive_sync(uint32_t type, uint32_t id);
	278	int64_t opal_xive_dump(uint32_t type, uint32_t id);
88ec6b93 CLG	279	int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
	280	__be32 *out_qtoggle,
	281	__be32 *out_qindex);
	282	int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
	283	uint32_t qtoggle,
	284	uint32_t qindex);
	285	int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
25529100 FB	286	int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
25529100 FB	287	uint64_t desc, uint16_t pe_number);
9fedd3f8	288
28a5db00 MS	289	int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
	290	uint64_t cpu_pir);
	291	int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
	292	int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
	293
cb8b340d SB	294	int opal_get_powercap(u32 handle, int token, u32 *pcap);
cb8b340d SB	295	int opal_set_powercap(u32 handle, int token, u32 pcap);
8e84b2d1 SB	296	int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
8e84b2d1 SB	297	int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
bf957155	298	int opal_sensor_group_clear(u32 group_hndl, int token);
04baaf28	299	int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
656ecc16	300	int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
cb8b340d	301
e36d0a2e	302	s64 opal_signal_system_reset(s32 cpu);
ee03b9b4	303	s64 opal_quiesce(u64 shutdown_type, s32 cpu);
e36d0a2e	304
14a43e69	305	/* Internal functions */
e2c8b93e AB	306	extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
e2c8b93e AB	307	int depth, void *data);
55672ecf MS	308	extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
55672ecf MS	309	const char uname, int depth, void data);
d3cbff1b	310	extern void opal_configure_cores(void);
14a43e69 BH	311
	312	extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
	313	extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
17cc1dd4	314	extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
95b861a7	315	extern int opal_flush_chars(uint32_t vtermno, bool wait);
d2a2262e	316	extern int opal_flush_console(uint32_t vtermno);
14a43e69 BH	317
	318	extern void hvc_opal_init_early(void);
	319
1bc98de2	320	extern int opal_notifier_register(struct notifier_block *nb);
798af00c BH	321	extern int opal_notifier_unregister(struct notifier_block *nb);
798af00c BH	322
d7cf83fc	323	extern int opal_message_notifier_register(enum opal_msg_type msg_type,
24366360	324	struct notifier_block *nb);
df60f576	325	extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
b921e902	326	struct notifier_block *nb);
1bc98de2 GS	327	extern void opal_notifier_enable(void);
	328	extern void opal_notifier_disable(void);
	329	extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
	330
8d724823	331	extern int opal_async_get_token_interruptible(void);
8d724823 NG	332	extern int opal_async_release_token(int token);
8d724823 NG	333	extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
9aab2449 CB	334	extern int opal_async_wait_response_interruptible(uint64_t token,
9aab2449 CB	335	struct opal_msg *msg);
7224adbb	336	extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
5cdcb01e	337	extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
04baaf28	338	extern int sensor_group_enable(u32 grp_hndl, bool enable);
8d724823	339
628daa8d	340	struct rtc_time;
5bfd6435	341	extern time64_t opal_get_boot_time(void);
628daa8d	342	extern void opal_nvram_init(void);
ed59190e	343	extern void opal_flash_update_init(void);
f2748bdf	344	extern void opal_flash_update_print_message(void);
774fea1a	345	extern int opal_elog_init(void);
c7e64b9c	346	extern void opal_platform_dump_init(void);
4029cd66	347	extern void opal_sys_param_init(void);
bfc36894	348	extern void opal_msglog_init(void);
9b4fffa1	349	extern void opal_msglog_sysfs_init(void);
96e023e7 AP	350	extern int opal_async_comp_init(void);
	351	extern int opal_sensor_init(void);
	352	extern int opal_hmi_handler_init(void);
9f0fd049	353	extern int opal_event_init(void);
08fb726d	354	int opal_power_control_init(void);
628daa8d	355
ed79ba9e	356	extern int opal_machine_check(struct pt_regs *regs);
55672ecf	357	extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
0869b6fd	358	extern int opal_hmi_exception_early(struct pt_regs *regs);
de269129	359	extern int opal_hmi_exception_early2(struct pt_regs *regs);
0869b6fd	360	extern int opal_handle_hmi_exception(struct pt_regs *regs);
ed79ba9e	361
73ed148a	362	extern void opal_shutdown(void);
97eb001f	363	extern int opal_resync_timebase(void);
73ed148a	364
3fafe9c2 BH	365	extern void opal_lpc_init(void);
3fafe9c2 BH	366
affddff6 RC	367	extern void opal_kmsg_init(void);
affddff6 RC	368
9f0fd049 AP	369	extern int opal_event_request(unsigned int opal_event_nr);
9f0fd049 AP	370
3441f04b AB	371	struct opal_sg_list opal_vmalloc_to_sg_list(void vmalloc_addr,
	372	unsigned long vmalloc_size);
	373	void opal_free_sg_list(struct opal_sg_list *sg);
	374
e3c5c2e0 CLG	375	extern int opal_error_code(int rc);
e3c5c2e0 CLG	376
9b4fffa1 AD	377	ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
9b4fffa1 AD	378
d0226d31 SJS	379	static inline int opal_get_async_rc(struct opal_msg msg)
	380	{
	381	if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
	382	return OPAL_PARAMETER;
	383	else
	384	return be64_to_cpu(msg.params[1]);
	385	}
	386
a203658b BH	387	void opal_wake_poller(void);
a203658b BH	388
cb8b340d	389	void opal_powercap_init(void);
8e84b2d1	390	void opal_psr_init(void);
bf957155	391	void opal_sensor_groups_init(void);
cb8b340d	392
14a43e69	393	#endif /* __ASSEMBLY__ */
27f44888	394
d800ba12	395	#endif /* _ASM_POWERPC_OPAL_H */