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Commit | Line | Data |
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1da177e4 | 1 | /* |
8882a4da DG |
2 | * This control block defines the PACA which defines the processor |
3 | * specific data for each logical processor on the system. | |
1da177e4 LT |
4 | * There are some pointers defined that are utilized by PLIC. |
5 | * | |
6 | * C 2001 PPC 64 Team, IBM Corp | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
8882a4da DG |
12 | */ |
13 | #ifndef _ASM_POWERPC_PACA_H | |
14 | #define _ASM_POWERPC_PACA_H | |
88ced031 | 15 | #ifdef __KERNEL__ |
1da177e4 | 16 | |
1426d5a3 ME |
17 | #ifdef CONFIG_PPC64 |
18 | ||
2fc251a8 | 19 | #include <linux/string.h> |
dce6670a BH |
20 | #include <asm/types.h> |
21 | #include <asm/lppaca.h> | |
22 | #include <asm/mmu.h> | |
23 | #include <asm/page.h> | |
8c388514 | 24 | #ifdef CONFIG_PPC_BOOK3E |
dce6670a | 25 | #include <asm/exception-64e.h> |
8c388514 NP |
26 | #else |
27 | #include <asm/exception-64s.h> | |
28 | #endif | |
7e57cba0 | 29 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
2191d657 | 30 | #include <asm/kvm_book3s_asm.h> |
7e57cba0 | 31 | #endif |
c223c903 | 32 | #include <asm/accounting.h> |
fd7bacbc | 33 | #include <asm/hmi.h> |
e1c1cfed | 34 | #include <asm/cpuidle.h> |
1da177e4 LT |
35 | |
36 | register struct paca_struct *local_paca asm("r13"); | |
048c8bc9 HD |
37 | |
38 | #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP) | |
39 | extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */ | |
40 | /* | |
41 | * Add standard checks that preemption cannot occur when using get_paca(): | |
42 | * otherwise the paca_struct it points to may be the wrong one just after. | |
43 | */ | |
44 | #define get_paca() ((void) debug_smp_processor_id(), local_paca) | |
45 | #else | |
1da177e4 | 46 | #define get_paca() local_paca |
048c8bc9 HD |
47 | #endif |
48 | ||
3356bb9f | 49 | #define get_lppaca() (get_paca()->lppaca_ptr) |
2f6093c8 | 50 | #define get_slb_shadow() (get_paca()->slb_shadow_ptr) |
1da177e4 LT |
51 | |
52 | struct task_struct; | |
1da177e4 LT |
53 | |
54 | /* | |
55 | * Defines the layout of the paca. | |
56 | * | |
57 | * This structure is not directly accessed by firmware or the service | |
30ff2e87 | 58 | * processor. |
1da177e4 LT |
59 | */ |
60 | struct paca_struct { | |
91c60b5b | 61 | #ifdef CONFIG_PPC_BOOK3S |
1da177e4 LT |
62 | /* |
63 | * Because hw_cpu_id, unlike other paca fields, is accessed | |
64 | * routinely from other CPUs (from the IRQ code), we stick to | |
65 | * read-only (after boot) fields in the first cacheline to | |
66 | * avoid cacheline bouncing. | |
67 | */ | |
68 | ||
1da177e4 | 69 | struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ |
91c60b5b | 70 | #endif /* CONFIG_PPC_BOOK3S */ |
1da177e4 | 71 | /* |
2ef9481e | 72 | * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c |
1da177e4 LT |
73 | * load lock_token and paca_index with a single lwz |
74 | * instruction. They must travel together and be properly | |
75 | * aligned. | |
76 | */ | |
54bb7f4b | 77 | #ifdef __BIG_ENDIAN__ |
1da177e4 LT |
78 | u16 lock_token; /* Constant 0x8000, used in locks */ |
79 | u16 paca_index; /* Logical processor number */ | |
54bb7f4b AB |
80 | #else |
81 | u16 paca_index; /* Logical processor number */ | |
82 | u16 lock_token; /* Constant 0x8000, used in locks */ | |
83 | #endif | |
1da177e4 | 84 | |
1da177e4 | 85 | u64 kernel_toc; /* Kernel TOC address */ |
1f6a93e4 PM |
86 | u64 kernelbase; /* Base address of kernel */ |
87 | u64 kernel_msr; /* MSR while running in kernel */ | |
1da177e4 | 88 | void *emergency_sp; /* pointer to emergency stack */ |
7a0268fa | 89 | u64 data_offset; /* per cpu data offset */ |
1da177e4 LT |
90 | s16 hw_cpu_id; /* Physical processor number */ |
91 | u8 cpu_start; /* At startup, processor spins until */ | |
92 | /* this becomes non-zero. */ | |
1fc711f7 | 93 | u8 kexec_state; /* set when kexec down has irqs off */ |
4e003747 | 94 | #ifdef CONFIG_PPC_BOOK3S_64 |
e91948fd | 95 | struct slb_shadow *slb_shadow_ptr; |
cf9efce0 PM |
96 | struct dtl_entry *dispatch_log; |
97 | struct dtl_entry *dispatch_log_end; | |
4e003747 | 98 | #endif |
1739ea9e | 99 | u64 dscr_default; /* per-CPU default DSCR */ |
1da177e4 | 100 | |
4e003747 | 101 | #ifdef CONFIG_PPC_BOOK3S_64 |
1da177e4 LT |
102 | /* |
103 | * Now, starting in cacheline 2, the exception save areas | |
104 | */ | |
3c726f8d | 105 | /* used for most interrupts/exceptions */ |
8c388514 NP |
106 | u64 exgen[EX_SIZE] __attribute__((aligned(0x80))); |
107 | u64 exslb[EX_SIZE]; /* used for SLB/segment table misses | |
3c726f8d | 108 | * on the linear mapping */ |
91c60b5b | 109 | /* SLB related definitions */ |
bf72aeba | 110 | u16 vmalloc_sllp; |
1da177e4 | 111 | u16 slb_cache_ptr; |
735cafc3 | 112 | u32 slb_cache[SLB_CACHE_ENTRIES]; |
4e003747 | 113 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
91c60b5b | 114 | |
dce6670a | 115 | #ifdef CONFIG_PPC_BOOK3E |
016f8cf0 | 116 | u64 exgen[8] __aligned(0x40); |
f67f4ef5 | 117 | /* Keep pgd in the same cacheline as the start of extlb */ |
016f8cf0 | 118 | pgd_t *pgd __aligned(0x40); /* Current PGD */ |
f67f4ef5 | 119 | pgd_t *kernel_pgd; /* Kernel PGD */ |
28efc35f SW |
120 | |
121 | /* Shared by all threads of a core -- points to tcd of first thread */ | |
122 | struct tlb_core_data *tcd_ptr; | |
123 | ||
609af38f SW |
124 | /* |
125 | * We can have up to 3 levels of reentrancy in the TLB miss handler, | |
126 | * in each of four exception levels (normal, crit, mcheck, debug). | |
127 | */ | |
128 | u64 extlb[12][EX_TLB_SIZE / sizeof(u64)]; | |
dce6670a BH |
129 | u64 exmc[8]; /* used for machine checks */ |
130 | u64 excrit[8]; /* used for crit interrupts */ | |
131 | u64 exdbg[8]; /* used for debug interrupts */ | |
132 | ||
133 | /* Kernel stack pointers for use by special exceptions */ | |
134 | void *mc_kstack; | |
135 | void *crit_kstack; | |
136 | void *dbg_kstack; | |
28efc35f SW |
137 | |
138 | struct tlb_core_data tcd; | |
dce6670a BH |
139 | #endif /* CONFIG_PPC_BOOK3E */ |
140 | ||
c395465d | 141 | #ifdef CONFIG_PPC_BOOK3S |
2fc251a8 MN |
142 | mm_context_id_t mm_ctx_id; |
143 | #ifdef CONFIG_PPC_MM_SLICES | |
144 | u64 mm_ctx_low_slices_psize; | |
145 | unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE]; | |
4722476b | 146 | unsigned long mm_ctx_slb_addr_limit; |
2fc251a8 | 147 | #else |
c33e54fa | 148 | u16 mm_ctx_user_psize; |
2fc251a8 MN |
149 | u16 mm_ctx_sllp; |
150 | #endif | |
c395465d | 151 | #endif |
1da177e4 LT |
152 | |
153 | /* | |
154 | * then miscellaneous read-write fields | |
155 | */ | |
156 | struct task_struct *__current; /* Pointer to current */ | |
157 | u64 kstack; /* Saved Kernel stack addr */ | |
158 | u64 stab_rr; /* stab/slb round-robin counter */ | |
948cf67c | 159 | u64 saved_r1; /* r1 save for RTAS calls or PM */ |
1da177e4 | 160 | u64 saved_msr; /* MSR saved here by enter_rtas */ |
68730401 | 161 | u16 trap_save; /* Used when bad stack is encountered */ |
d04c56f7 | 162 | u8 soft_enabled; /* irq soft-enable flag */ |
7230c564 | 163 | u8 irq_happened; /* irq happened while soft-disabled */ |
f007cacf | 164 | u8 io_sync; /* writel() needs spin_unlock sync */ |
e360adbe | 165 | u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ |
2fde6d20 | 166 | u8 nap_state_lost; /* NV GPR values lost in power7_idle */ |
9d378dfa | 167 | u64 sprg_vdso; /* Saved user-visible sprg */ |
afc07701 MN |
168 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
169 | u64 tm_scratch; /* TM scratch area for reclaim */ | |
170 | #endif | |
c6622f63 | 171 | |
7cba160a SP |
172 | #ifdef CONFIG_PPC_POWERNV |
173 | /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */ | |
174 | u32 *core_idle_state_ptr; | |
175 | u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */ | |
176 | /* Mask to indicate thread id in core */ | |
177 | u8 thread_mask; | |
77b54e9f SP |
178 | /* Mask to denote subcore sibling threads */ |
179 | u8 subcore_sibling_mask; | |
17ed4c8f GS |
180 | /* |
181 | * Pointer to an array which contains pointer | |
182 | * to the sibling threads' paca. | |
183 | */ | |
184 | struct paca_struct **thread_sibling_pacas; | |
22c6663d GS |
185 | /* The PSSCR value that the kernel requested before going to stop */ |
186 | u64 requested_psscr; | |
e1c1cfed GS |
187 | |
188 | /* | |
189 | * Save area for additional SPRs that need to be | |
190 | * saved/restored during cpuidle stop. | |
191 | */ | |
192 | struct stop_sprs stop_sprs; | |
7cba160a SP |
193 | #endif |
194 | ||
4e003747 | 195 | #ifdef CONFIG_PPC_BOOK3S_64 |
a3d96f70 | 196 | /* Non-maskable exceptions that are not performance critical */ |
8c388514 NP |
197 | u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */ |
198 | u64 exmc[EX_SIZE]; /* used for machine checks */ | |
a3d96f70 | 199 | #endif |
729b0f71 | 200 | #ifdef CONFIG_PPC_BOOK3S_64 |
b1ee8a3d NP |
201 | /* Exclusive stacks for system reset and machine check exception. */ |
202 | void *nmi_emergency_sp; | |
729b0f71 | 203 | void *mc_emergency_sp; |
c4f3b52c NP |
204 | |
205 | u16 in_nmi; /* In nmi handler */ | |
206 | ||
729b0f71 MS |
207 | /* |
208 | * Flag to check whether we are in machine check early handler | |
209 | * and already using emergency stack. | |
210 | */ | |
211 | u16 in_mce; | |
c4f3b52c | 212 | u8 hmi_event_available; /* HMI event is available */ |
5080332c | 213 | u8 hmi_p9_special_emu; /* HMI P9 special emulation */ |
729b0f71 | 214 | #endif |
ed79ba9e | 215 | |
c6622f63 | 216 | /* Stuff for accurate time accounting */ |
c223c903 | 217 | struct cpu_accounting_data accounting; |
cf9efce0 PM |
218 | u64 dtl_ridx; /* read index in dispatch log */ |
219 | struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */ | |
4b7ae55d | 220 | |
c14dea04 | 221 | #ifdef CONFIG_KVM_BOOK3S_HANDLER |
7aa79938 | 222 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
7e57cba0 AG |
223 | /* We use this to store guest state in */ |
224 | struct kvmppc_book3s_shadow_vcpu shadow_vcpu; | |
de56a948 | 225 | #endif |
3c42bf8a | 226 | struct kvmppc_host_state kvm_hstate; |
7c379526 PB |
227 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
228 | /* | |
229 | * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for | |
230 | * more details | |
231 | */ | |
232 | struct sibling_subcore_state *sibling_subcore_state; | |
233 | #endif | |
4b7ae55d | 234 | #endif |
aa8a5e00 ME |
235 | #ifdef CONFIG_PPC_BOOK3S_64 |
236 | /* | |
237 | * rfi fallback flush must be in its own cacheline to prevent | |
238 | * other paca data leaking into the L1d | |
239 | */ | |
240 | u64 exrfi[EX_SIZE] __aligned(0x80); | |
241 | void *rfi_flush_fallback_area; | |
242 | u64 l1d_flush_congruence; | |
243 | u64 l1d_flush_sets; | |
244 | #endif | |
1da177e4 LT |
245 | }; |
246 | ||
52b1e665 | 247 | extern void copy_mm_to_paca(struct mm_struct *mm); |
1426d5a3 | 248 | extern struct paca_struct *paca; |
1426d5a3 | 249 | extern void initialise_paca(struct paca_struct *new_paca, int cpu); |
fc53b420 | 250 | extern void setup_paca(struct paca_struct *new_paca); |
1426d5a3 ME |
251 | extern void allocate_pacas(void); |
252 | extern void free_unused_pacas(void); | |
253 | ||
254 | #else /* CONFIG_PPC64 */ | |
255 | ||
256 | static inline void allocate_pacas(void) { }; | |
257 | static inline void free_unused_pacas(void) { }; | |
258 | ||
259 | #endif /* CONFIG_PPC64 */ | |
1da177e4 | 260 | |
88ced031 | 261 | #endif /* __KERNEL__ */ |
8882a4da | 262 | #endif /* _ASM_POWERPC_PACA_H */ |