[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / include / asm / page_64.h

#ifndef _ASM_POWERPC_PAGE_64_H
#define _ASM_POWERPC_PAGE_64_H

/*
 * Copyright (C) 2001 PPC64 Team, IBM Corp
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

/*
 * We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
 * specific, every notion of page number shared with the firmware, TCEs,
 * iommu, etc... still uses a page size of 4K.
 */
#define HW_PAGE_SHIFT		12
#define HW_PAGE_SIZE		(ASM_CONST(1) << HW_PAGE_SHIFT)
#define HW_PAGE_MASK		(~(HW_PAGE_SIZE-1))

/*
 * PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
 * HW_PAGE_SHIFT, that is 4K pages.
 */
#define PAGE_FACTOR		(PAGE_SHIFT - HW_PAGE_SHIFT)

/* Segment size; normal 256M segments */
#define SID_SHIFT		28
#define SID_MASK		ASM_CONST(0xfffffffff)
#define ESID_MASK		0xfffffffff0000000UL
#define GET_ESID(x)		(((x) >> SID_SHIFT) & SID_MASK)

/* 1T segments */
#define SID_SHIFT_1T		40
#define SID_MASK_1T		0xffffffUL
#define ESID_MASK_1T		0xffffff0000000000UL
#define GET_ESID_1T(x)		(((x) >> SID_SHIFT_1T) & SID_MASK_1T)

#ifndef __ASSEMBLY__
#include <asm/cache.h>

typedef unsigned long pte_basic_t;

static inline void clear_page(void *addr)
{
	unsigned long iterations;
	unsigned long onex, twox, fourx, eightx;

	iterations = ppc64_caches.dlines_per_page / 8;

	/*
	 * Some verisions of gcc use multiply instructions to
	 * calculate the offsets so lets give it a hand to
	 * do better.
	 */
	onex = ppc64_caches.dline_size;
	twox = onex << 1;
	fourx = onex << 2;
	eightx = onex << 3;

	asm volatile(
	"mtctr	%1	# clear_page\n\
	.balign	16\n\
1:	dcbz	0,%0\n\
	dcbz	%3,%0\n\
	dcbz	%4,%0\n\
	dcbz	%5,%0\n\
	dcbz	%6,%0\n\
	dcbz	%7,%0\n\
	dcbz	%8,%0\n\
	dcbz	%9,%0\n\
	add	%0,%0,%10\n\
	bdnz+	1b"
	: "=&r" (addr)
	: "r" (iterations), "0" (addr), "b" (onex), "b" (twox),
		"b" (twox+onex), "b" (fourx), "b" (fourx+onex),
		"b" (twox+fourx), "b" (eightx-onex), "r" (eightx)
	: "ctr", "memory");
}

extern void copy_page(void *to, void *from);

/* Log 2 of page table size */
extern u64 ppc64_pft_size;

#endif /* __ASSEMBLY__ */

#ifdef CONFIG_PPC_MM_SLICES

#define SLICE_LOW_SHIFT		28
#define SLICE_HIGH_SHIFT	40

#define SLICE_LOW_TOP		(0x100000000ul)
#define SLICE_NUM_LOW		(SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
#define SLICE_NUM_HIGH		(H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)

#define GET_LOW_SLICE_INDEX(addr)	((addr) >> SLICE_LOW_SHIFT)
#define GET_HIGH_SLICE_INDEX(addr)	((addr) >> SLICE_HIGH_SHIFT)

/*
 * 1 bit per slice and we have one slice per 1TB
 * Right now we support only 64TB.
 * IF we change this we will have to change the type
 * of high_slices
 */
#define SLICE_MASK_SIZE 8

#ifndef __ASSEMBLY__

struct slice_mask {
	u16 low_slices;
	u64 high_slices;
};

struct mm_struct;

extern unsigned long slice_get_unmapped_area(unsigned long addr,
					     unsigned long len,
					     unsigned long flags,
					     unsigned int psize,
					     int topdown);

extern unsigned int get_slice_psize(struct mm_struct *mm,
				    unsigned long addr);

extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
				  unsigned long len, unsigned int psize);

#endif /* __ASSEMBLY__ */
#else
#define slice_init()
#ifdef CONFIG_PPC_STD_MMU_64
#define get_slice_psize(mm, addr)	((mm)->context.user_psize)
#define slice_set_user_psize(mm, psize)		\
do {						\
	(mm)->context.user_psize = (psize);	\
	(mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
} while (0)
#else /* CONFIG_PPC_STD_MMU_64 */
#ifdef CONFIG_PPC_64K_PAGES
#define get_slice_psize(mm, addr)	MMU_PAGE_64K
#else /* CONFIG_PPC_64K_PAGES */
#define get_slice_psize(mm, addr)	MMU_PAGE_4K
#endif /* !CONFIG_PPC_64K_PAGES */
#define slice_set_user_psize(mm, psize)	do { BUG(); } while(0)
#endif /* !CONFIG_PPC_STD_MMU_64 */

#define slice_set_range_psize(mm, start, len, psize)	\
	slice_set_user_psize((mm), (psize))
#endif /* CONFIG_PPC_MM_SLICES */

#ifdef CONFIG_HUGETLB_PAGE

#ifdef CONFIG_PPC_MM_SLICES
#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
#endif

#endif /* !CONFIG_HUGETLB_PAGE */

#define VM_DATA_DEFAULT_FLAGS \
	(is_32bit_task() ? \
	 VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)

/*
 * This is the default if a program doesn't have a PT_GNU_STACK
 * program header entry. The PPC64 ELF ABI has a non executable stack
 * stack by default, so in the absence of a PT_GNU_STACK program header
 * we turn execute permission off.
 */
#define VM_STACK_DEFAULT_FLAGS32	(VM_READ | VM_WRITE | VM_EXEC | \
					 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)

#define VM_STACK_DEFAULT_FLAGS64	(VM_READ | VM_WRITE | \
					 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)

#define VM_STACK_DEFAULT_FLAGS \
	(is_32bit_task() ? \
	 VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)

#include <asm-generic/getorder.h>

#endif /* _ASM_POWERPC_PAGE_64_H */
Commit	Line	Data
5cd16ee9 ME	1	#ifndef _ASM_POWERPC_PAGE_64_H
	2	#define _ASM_POWERPC_PAGE_64_H
	3
	4	/*
	5	* Copyright (C) 2001 PPC64 Team, IBM Corp
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; either version
	10	* 2 of the License, or (at your option) any later version.
	11	*/
	12
	13	/*
	14	* We always define HW_PAGE_SHIFT to 12 as use of 64K pages remains Linux
	15	* specific, every notion of page number shared with the firmware, TCEs,
	16	* iommu, etc... still uses a page size of 4K.
	17	*/
	18	#define HW_PAGE_SHIFT 12
	19	#define HW_PAGE_SIZE (ASM_CONST(1) << HW_PAGE_SHIFT)
	20	#define HW_PAGE_MASK (~(HW_PAGE_SIZE-1))
	21
	22	/*
	23	* PAGE_FACTOR is the number of bits factor between PAGE_SHIFT and
	24	* HW_PAGE_SHIFT, that is 4K pages.
	25	*/
	26	#define PAGE_FACTOR (PAGE_SHIFT - HW_PAGE_SHIFT)
	27
1189be65	28	/* Segment size; normal 256M segments */
5cd16ee9	29	#define SID_SHIFT 28
16a15a30	30	#define SID_MASK ASM_CONST(0xfffffffff)
5cd16ee9 ME	31	#define ESID_MASK 0xfffffffff0000000UL
	32	#define GET_ESID(x) (((x) >> SID_SHIFT) & SID_MASK)
	33
1189be65 PM	34	/* 1T segments */
	35	#define SID_SHIFT_1T 40
	36	#define SID_MASK_1T 0xffffffUL
	37	#define ESID_MASK_1T 0xffffff0000000000UL
	38	#define GET_ESID_1T(x) (((x) >> SID_SHIFT_1T) & SID_MASK_1T)
	39
5cd16ee9 ME	40	#ifndef __ASSEMBLY__
	41	#include <asm/cache.h>
	42
	43	typedef unsigned long pte_basic_t;
	44
e35735b9	45	static inline void clear_page(void *addr)
5cd16ee9	46	{
e35735b9 AB	47	unsigned long iterations;
	48	unsigned long onex, twox, fourx, eightx;
	49
	50	iterations = ppc64_caches.dlines_per_page / 8;
	51
	52	/*
	53	* Some verisions of gcc use multiply instructions to
	54	* calculate the offsets so lets give it a hand to
	55	* do better.
	56	*/
	57	onex = ppc64_caches.dline_size;
	58	twox = onex << 1;
	59	fourx = onex << 2;
	60	eightx = onex << 3;
	61
	62	asm volatile(
5cd16ee9	63	"mtctr %1 # clear_page\n\
e35735b9 AB	64	.balign 16\n\
	65	1: dcbz 0,%0\n\
	66	dcbz %3,%0\n\
	67	dcbz %4,%0\n\
	68	dcbz %5,%0\n\
	69	dcbz %6,%0\n\
	70	dcbz %7,%0\n\
	71	dcbz %8,%0\n\
	72	dcbz %9,%0\n\
	73	add %0,%0,%10\n\
5cd16ee9	74	bdnz+ 1b"
e35735b9 AB	75	: "=&r" (addr)
	76	: "r" (iterations), "0" (addr), "b" (onex), "b" (twox),
	77	"b" (twox+onex), "b" (fourx), "b" (fourx+onex),
	78	"b" (twox+fourx), "b" (eightx-onex), "r" (eightx)
5cd16ee9 ME	79	: "ctr", "memory");
	80	}
	81
d988f0e3	82	extern void copy_page(void to, void from);
5cd16ee9 ME	83
	84	/* Log 2 of page table size */
	85	extern u64 ppc64_pft_size;
	86
5cd16ee9 ME	87	#endif /* __ASSEMBLY__ */
5cd16ee9 ME	88
d0f13e3c	89	#ifdef CONFIG_PPC_MM_SLICES
5cd16ee9	90
d0f13e3c BH	91	#define SLICE_LOW_SHIFT 28
d0f13e3c BH	92	#define SLICE_HIGH_SHIFT 40
5cd16ee9	93
d0f13e3c BH	94	#define SLICE_LOW_TOP (0x100000000ul)
d0f13e3c BH	95	#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
dd1842a2	96	#define SLICE_NUM_HIGH (H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
5cd16ee9	97
d0f13e3c BH	98	#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
d0f13e3c BH	99	#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
5cd16ee9	100
78f1dbde AK	101	/*
	102	* 1 bit per slice and we have one slice per 1TB
	103	* Right now we support only 64TB.
	104	* IF we change this we will have to change the type
	105	* of high_slices
	106	*/
	107	#define SLICE_MASK_SIZE 8
	108
d0f13e3c BH	109	#ifndef __ASSEMBLY__
	110
	111	struct slice_mask {
	112	u16 low_slices;
7aa0727f	113	u64 high_slices;
d0f13e3c BH	114	};
	115
	116	struct mm_struct;
5cd16ee9	117
d0f13e3c BH	118	extern unsigned long slice_get_unmapped_area(unsigned long addr,
	119	unsigned long len,
	120	unsigned long flags,
	121	unsigned int psize,
34d07177	122	int topdown);
5cd16ee9	123
d0f13e3c BH	124	extern unsigned int get_slice_psize(struct mm_struct *mm,
d0f13e3c BH	125	unsigned long addr);
5cd16ee9	126
d0f13e3c	127	extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
3a8247cc PM	128	extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
	129	unsigned long len, unsigned int psize);
	130
d0f13e3c BH	131	#endif /* __ASSEMBLY__ */
	132	#else
	133	#define slice_init()
57e2a99f	134	#ifdef CONFIG_PPC_STD_MMU_64
3a8247cc	135	#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
e8ff0646 SR	136	#define slice_set_user_psize(mm, psize) \
	137	do { \
	138	(mm)->context.user_psize = (psize); \
	139	(mm)->context.sllp = SLB_VSID_USER \| mmu_psize_defs[(psize)].sllp; \
	140	} while (0)
57e2a99f BH	141	#else /* CONFIG_PPC_STD_MMU_64 */
	142	#ifdef CONFIG_PPC_64K_PAGES
	143	#define get_slice_psize(mm, addr) MMU_PAGE_64K
	144	#else /* CONFIG_PPC_64K_PAGES */
	145	#define get_slice_psize(mm, addr) MMU_PAGE_4K
	146	#endif /* !CONFIG_PPC_64K_PAGES */
	147	#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
	148	#endif /* !CONFIG_PPC_STD_MMU_64 */
	149
3a8247cc PM	150	#define slice_set_range_psize(mm, start, len, psize) \
3a8247cc PM	151	slice_set_user_psize((mm), (psize))
d0f13e3c BH	152	#endif /* CONFIG_PPC_MM_SLICES */
	153
	154	#ifdef CONFIG_HUGETLB_PAGE
	155
76512959	156	#ifdef CONFIG_PPC_MM_SLICES
d0f13e3c	157	#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
76512959	158	#endif
5cd16ee9 ME	159
	160	#endif /* !CONFIG_HUGETLB_PAGE */
	161
5cd16ee9	162	#define VM_DATA_DEFAULT_FLAGS \
cab175f9	163	(is_32bit_task() ? \
5cd16ee9 ME	164	VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
	165
	166	/*
	167	* This is the default if a program doesn't have a PT_GNU_STACK
	168	* program header entry. The PPC64 ELF ABI has a non executable stack
25985edc	169	* stack by default, so in the absence of a PT_GNU_STACK program header
5cd16ee9 ME	170	* we turn execute permission off.
	171	*/
	172	#define VM_STACK_DEFAULT_FLAGS32 (VM_READ \| VM_WRITE \| VM_EXEC \| \
	173	VM_MAYREAD \| VM_MAYWRITE \| VM_MAYEXEC)
	174
	175	#define VM_STACK_DEFAULT_FLAGS64 (VM_READ \| VM_WRITE \| \
	176	VM_MAYREAD \| VM_MAYWRITE \| VM_MAYEXEC)
	177
	178	#define VM_STACK_DEFAULT_FLAGS \
cab175f9	179	(is_32bit_task() ? \
5cd16ee9 ME	180	VM_STACK_DEFAULT_FLAGS32 : VM_STACK_DEFAULT_FLAGS64)
5cd16ee9 ME	181
5b17e1cd	182	#include <asm-generic/getorder.h>
5cd16ee9 ME	183
5cd16ee9 ME	184	#endif /* _ASM_POWERPC_PAGE_64_H */