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047ea784 PM |
1 | #ifndef _ASM_POWERPC_PCI_BRIDGE_H |
2 | #define _ASM_POWERPC_PCI_BRIDGE_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
7cd1de6b SR |
4 | /* |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
5531e41b | 10 | #include <linux/pci.h> |
a4c9e328 KG |
11 | #include <linux/list.h> |
12 | #include <linux/ioport.h> | |
13 | ||
44ef3390 SR |
14 | struct device_node; |
15 | ||
fc3fb71c BH |
16 | extern unsigned int ppc_pci_flags; |
17 | enum { | |
18 | /* Force re-assigning all resources (ignore firmware | |
19 | * setup completely) | |
20 | */ | |
21 | PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, | |
22 | ||
23 | /* Re-assign all bus numbers */ | |
24 | PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, | |
25 | ||
26 | /* Do not try to assign, just use existing setup */ | |
27 | PPC_PCI_PROBE_ONLY = 0x00000004, | |
28 | ||
29 | /* Don't bother with ISA alignment unless the bridge has | |
30 | * ISA forwarding enabled | |
31 | */ | |
32 | PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, | |
fa462f2d BH |
33 | |
34 | /* Enable domain numbers in /proc */ | |
35 | PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, | |
36 | /* ... except for domain 0 */ | |
37 | PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, | |
fc3fb71c BH |
38 | }; |
39 | ||
40 | ||
5531e41b KG |
41 | /* |
42 | * Structure of a PCI controller (host bridge) | |
43 | */ | |
44 | struct pci_controller { | |
45 | struct pci_bus *bus; | |
a4c9e328 | 46 | char is_dynamic; |
7211991f SR |
47 | #ifdef CONFIG_PPC64 |
48 | int node; | |
49 | #endif | |
44ef3390 | 50 | struct device_node *dn; |
a4c9e328 | 51 | struct list_head list_node; |
5531e41b KG |
52 | struct device *parent; |
53 | ||
54 | int first_busno; | |
55 | int last_busno; | |
7211991f | 56 | #ifndef CONFIG_PPC64 |
5531e41b | 57 | int self_busno; |
7211991f | 58 | #endif |
5531e41b KG |
59 | |
60 | void __iomem *io_base_virt; | |
7211991f SR |
61 | #ifdef CONFIG_PPC64 |
62 | void *io_base_alloc; | |
63 | #endif | |
5531e41b | 64 | resource_size_t io_base_phys; |
13dccb9e BH |
65 | #ifndef CONFIG_PPC64 |
66 | resource_size_t pci_io_size; | |
67 | #endif | |
5531e41b KG |
68 | |
69 | /* Some machines (PReP) have a non 1:1 mapping of | |
70 | * the PCI memory space in the CPU bus space | |
71 | */ | |
72 | resource_size_t pci_mem_offset; | |
7211991f SR |
73 | #ifdef CONFIG_PPC64 |
74 | unsigned long pci_io_size; | |
75 | #endif | |
5531e41b | 76 | |
e9f82cb7 BH |
77 | /* Some machines have a special region to forward the ISA |
78 | * "memory" cycles such as VGA memory regions. Left to 0 | |
79 | * if unsupported | |
80 | */ | |
81 | resource_size_t isa_mem_phys; | |
82 | resource_size_t isa_mem_size; | |
83 | ||
5531e41b | 84 | struct pci_ops *ops; |
70fbb938 SR |
85 | unsigned int __iomem *cfg_addr; |
86 | void __iomem *cfg_data; | |
5531e41b | 87 | |
7211991f | 88 | #ifndef CONFIG_PPC64 |
5531e41b KG |
89 | /* |
90 | * Used for variants of PCI indirect handling and possible quirks: | |
91 | * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 | |
92 | * EXT_REG - provides access to PCI-e extended registers | |
93 | * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS | |
94 | * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS | |
95 | * to determine which bus number to match on when generating type0 | |
96 | * config cycles | |
62c66c8e KG |
97 | * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with |
98 | * hanging if we don't have link and try to do config cycles to | |
99 | * anything but the PHB. Only allow talking to the PHB if this is | |
100 | * set. | |
2e56ff20 | 101 | * BIG_ENDIAN - cfg_addr is a big endian register |
5ce4b596 JB |
102 | * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on |
103 | * the PLB4. Effectively disable MRM commands by setting this. | |
5531e41b | 104 | */ |
7cd1de6b SR |
105 | #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 |
106 | #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 | |
107 | #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 | |
108 | #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 | |
109 | #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 | |
5ce4b596 | 110 | #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 |
5531e41b | 111 | u32 indirect_type; |
7211991f | 112 | #endif /* !CONFIG_PPC64 */ |
5531e41b KG |
113 | /* Currently, we limit ourselves to 1 IO range and 3 mem |
114 | * ranges since the common pci_bus structure can't handle more | |
115 | */ | |
116 | struct resource io_resource; | |
117 | struct resource mem_resources[3]; | |
5516b540 | 118 | int global_number; /* PCI domain number */ |
7211991f SR |
119 | #ifdef CONFIG_PPC64 |
120 | unsigned long buid; | |
121 | unsigned long dma_window_base_cur; | |
122 | unsigned long dma_window_size; | |
123 | ||
124 | void *private_data; | |
125 | #endif /* CONFIG_PPC64 */ | |
5531e41b KG |
126 | }; |
127 | ||
7211991f SR |
128 | #ifndef CONFIG_PPC64 |
129 | ||
f13f4ca8 | 130 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) |
5531e41b KG |
131 | { |
132 | return bus->sysdata; | |
133 | } | |
134 | ||
6dfbde20 BH |
135 | static inline int isa_vaddr_is_ioport(void __iomem *address) |
136 | { | |
137 | /* No specific ISA handling on ppc32 at this stage, it | |
138 | * all goes through PCI | |
139 | */ | |
140 | return 0; | |
141 | } | |
142 | ||
5531e41b KG |
143 | /* These are used for config access before all the PCI probing |
144 | has been done. */ | |
7cd1de6b SR |
145 | extern int early_read_config_byte(struct pci_controller *hose, int bus, |
146 | int dev_fn, int where, u8 *val); | |
147 | extern int early_read_config_word(struct pci_controller *hose, int bus, | |
148 | int dev_fn, int where, u16 *val); | |
149 | extern int early_read_config_dword(struct pci_controller *hose, int bus, | |
150 | int dev_fn, int where, u32 *val); | |
151 | extern int early_write_config_byte(struct pci_controller *hose, int bus, | |
152 | int dev_fn, int where, u8 val); | |
153 | extern int early_write_config_word(struct pci_controller *hose, int bus, | |
154 | int dev_fn, int where, u16 val); | |
155 | extern int early_write_config_dword(struct pci_controller *hose, int bus, | |
156 | int dev_fn, int where, u32 val); | |
5531e41b | 157 | |
38805e5f KG |
158 | extern int early_find_capability(struct pci_controller *hose, int bus, |
159 | int dev_fn, int cap); | |
160 | ||
5531e41b | 161 | extern void setup_indirect_pci(struct pci_controller* hose, |
d94bad82 VB |
162 | resource_size_t cfg_addr, |
163 | resource_size_t cfg_data, u32 flags); | |
5531e41b | 164 | extern void setup_grackle(struct pci_controller *hose); |
7cd1de6b | 165 | #else /* CONFIG_PPC64 */ |
1da177e4 | 166 | |
1635317f PM |
167 | /* |
168 | * PCI stuff, for nodes representing PCI devices, pointed to | |
169 | * by device_node->data. | |
170 | */ | |
1635317f PM |
171 | struct iommu_table; |
172 | ||
173 | struct pci_dn { | |
7684b40c | 174 | int busno; /* pci bus number */ |
7684b40c | 175 | int devfn; /* pci device and function number */ |
b5166cc2 | 176 | |
c2e221e8 LV |
177 | struct pci_controller *phb; /* for pci devices */ |
178 | struct iommu_table *iommu_table; /* for phb's or bridges */ | |
c2e221e8 LV |
179 | struct device_node *node; /* back-pointer to the device_node */ |
180 | ||
181 | int pci_ext_config_space; /* for pci devices */ | |
182 | ||
183 | #ifdef CONFIG_EEH | |
b6ed42a7 | 184 | struct pci_dev *pcidev; /* back-pointer to the pci device */ |
86bcab49 | 185 | int class_code; /* pci device class */ |
1635317f PM |
186 | int eeh_mode; /* See eeh.h for possible EEH_MODEs */ |
187 | int eeh_config_addr; | |
25e591f6 | 188 | int eeh_pe_config_addr; /* new-style partition endpoint address */ |
7cd1de6b SR |
189 | int eeh_check_count; /* # times driver ignored error */ |
190 | int eeh_freeze_count; /* # times this device froze up. */ | |
191 | int eeh_false_positives; /* # times this device reported #ff's */ | |
1635317f | 192 | u32 config_space[16]; /* saved PCI config space */ |
c2e221e8 | 193 | #endif |
1635317f PM |
194 | }; |
195 | ||
196 | /* Get the pointer to a device_node's pci_dn */ | |
197 | #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) | |
198 | ||
7cd1de6b | 199 | extern struct device_node *fetch_dev_dn(struct pci_dev *dev); |
1da177e4 | 200 | |
1635317f PM |
201 | /* Get a device_node from a pci_dev. This code must be fast except |
202 | * in the case where the sysdata is incorrect and needs to be fixed | |
203 | * up (this will only happen once). | |
204 | * In this case the sysdata will have been inherited from a PCI host | |
205 | * bridge or a PCI-PCI bridge further up the tree, so it will point | |
206 | * to a valid struct pci_dn, just not the one we want. | |
1da177e4 LT |
207 | */ |
208 | static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) | |
209 | { | |
210 | struct device_node *dn = dev->sysdata; | |
1635317f | 211 | struct pci_dn *pdn = dn->data; |
1da177e4 | 212 | |
1635317f | 213 | if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number) |
1da177e4 | 214 | return dn; /* fast path. sysdata is good */ |
1635317f | 215 | return fetch_dev_dn(dev); |
1da177e4 LT |
216 | } |
217 | ||
40ef8cbc PM |
218 | static inline int pci_device_from_OF_node(struct device_node *np, |
219 | u8 *bus, u8 *devfn) | |
220 | { | |
221 | if (!PCI_DN(np)) | |
222 | return -ENODEV; | |
223 | *bus = PCI_DN(np)->busno; | |
224 | *devfn = PCI_DN(np)->devfn; | |
225 | return 0; | |
226 | } | |
227 | ||
1da177e4 LT |
228 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
229 | { | |
230 | if (bus->self) | |
231 | return pci_device_to_OF_node(bus->self); | |
232 | else | |
233 | return bus->sysdata; /* Must be root bus (PHB) */ | |
234 | } | |
235 | ||
2bf6a8fa | 236 | /** Find the bus corresponding to the indicated device node */ |
7cd1de6b | 237 | extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); |
2bf6a8fa | 238 | |
2bf6a8fa | 239 | /** Remove all of the PCI devices under this bus */ |
7cd1de6b | 240 | extern void pcibios_remove_pci_devices(struct pci_bus *bus); |
2bf6a8fa LV |
241 | |
242 | /** Discover new pci devices under this bus, and add them */ | |
7cd1de6b | 243 | extern void pcibios_add_pci_devices(struct pci_bus *bus); |
1da177e4 | 244 | |
f13f4ca8 | 245 | static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) |
1da177e4 LT |
246 | { |
247 | struct device_node *busdn = bus->sysdata; | |
248 | ||
249 | BUG_ON(busdn == NULL); | |
1635317f | 250 | return PCI_DN(busdn)->phb; |
1da177e4 LT |
251 | } |
252 | ||
b5166cc2 | 253 | |
3d5134ee BH |
254 | extern void isa_bridge_find_early(struct pci_controller *hose); |
255 | ||
6dfbde20 BH |
256 | static inline int isa_vaddr_is_ioport(void __iomem *address) |
257 | { | |
258 | /* Check if address hits the reserved legacy IO range */ | |
259 | unsigned long ea = (unsigned long)address; | |
260 | return ea >= ISA_IO_BASE && ea < ISA_IO_END; | |
261 | } | |
262 | ||
3d5134ee BH |
263 | extern int pcibios_unmap_io_space(struct pci_bus *bus); |
264 | extern int pcibios_map_io_space(struct pci_bus *bus); | |
265 | ||
4267292b PM |
266 | /* Return values for ppc_md.pci_probe_mode function */ |
267 | #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ | |
268 | #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ | |
269 | #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ | |
270 | ||
357518fa AB |
271 | #ifdef CONFIG_NUMA |
272 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) | |
273 | #else | |
274 | #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) | |
275 | #endif | |
276 | ||
7cd1de6b | 277 | #endif /* CONFIG_PPC64 */ |
5531e41b KG |
278 | |
279 | /* Get the PCI host controller for an OF device */ | |
7cd1de6b SR |
280 | extern struct pci_controller *pci_find_hose_for_OF_device( |
281 | struct device_node* node); | |
5531e41b KG |
282 | |
283 | /* Fill up host controller resources from the OF node */ | |
7cd1de6b SR |
284 | extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
285 | struct device_node *dev, int primary); | |
5531e41b | 286 | |
5131d4d8 | 287 | /* Allocate & free a PCI host bridge structure */ |
7cd1de6b | 288 | extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); |
5131d4d8 | 289 | extern void pcibios_free_controller(struct pci_controller *phb); |
53280323 | 290 | extern void pcibios_setup_phb_resources(struct pci_controller *hose); |
5131d4d8 | 291 | |
5531e41b KG |
292 | #ifdef CONFIG_PCI |
293 | extern unsigned long pci_address_to_pio(phys_addr_t address); | |
6dfbde20 | 294 | extern int pcibios_vaddr_is_ioport(void __iomem *address); |
5531e41b KG |
295 | #else |
296 | static inline unsigned long pci_address_to_pio(phys_addr_t address) | |
297 | { | |
298 | return (unsigned long)-1; | |
299 | } | |
6dfbde20 BH |
300 | static inline int pcibios_vaddr_is_ioport(void __iomem *address) |
301 | { | |
302 | return 0; | |
303 | } | |
7cd1de6b | 304 | #endif /* CONFIG_PCI */ |
5531e41b | 305 | |
7cd1de6b SR |
306 | #endif /* __KERNEL__ */ |
307 | #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ |