[mirror_ubuntu-artful-kernel.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>

struct device_node;

enum {
	/* Force re-assigning all resources (ignore firmware
	 * setup completely)
	 */
	PPC_PCI_REASSIGN_ALL_RSRC	= 0x00000001,

	/* Re-assign all bus numbers */
	PPC_PCI_REASSIGN_ALL_BUS	= 0x00000002,

	/* Do not try to assign, just use existing setup */
	PPC_PCI_PROBE_ONLY		= 0x00000004,

	/* Don't bother with ISA alignment unless the bridge has
	 * ISA forwarding enabled
	 */
	PPC_PCI_CAN_SKIP_ISA_ALIGN	= 0x00000008,

	/* Enable domain numbers in /proc */
	PPC_PCI_ENABLE_PROC_DOMAINS	= 0x00000010,
	/* ... except for domain 0 */
	PPC_PCI_COMPAT_DOMAIN_0		= 0x00000020,
};
#ifdef CONFIG_PCI
extern unsigned int ppc_pci_flags;

static inline void ppc_pci_set_flags(int flags)
{
	ppc_pci_flags = flags;
}

static inline void ppc_pci_add_flags(int flags)
{
	ppc_pci_flags |= flags;
}

static inline int ppc_pci_has_flag(int flag)
{
	return (ppc_pci_flags & flag);
}
#else
static inline void ppc_pci_set_flags(int flags) { }
static inline void ppc_pci_add_flags(int flags) { }
static inline int ppc_pci_has_flag(int flag)
{
	return 0;
}
#endif


/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
#ifndef CONFIG_PPC64
	int self_busno;
#endif

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines (PReP) have a non 1:1 mapping of
	 * the PCI memory space in the CPU bus space
	 */
	resource_size_t pci_mem_offset;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

#ifndef CONFIG_PPC64
	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
	u32 indirect_type;
#endif	/* !CONFIG_PPC64 */
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;

	void *private_data;
#endif	/* CONFIG_PPC64 */
};

#ifndef CONFIG_PPC64

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);
#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */

	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

#ifdef CONFIG_EEH
	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
	int	class_code;		/* pci device class */
	int	eeh_mode;		/* See eeh.h for possible EEH_MODEs */
	int	eeh_config_addr;
	int	eeh_pe_config_addr; /* new-style partition endpoint address */
	int	eeh_check_count;	/* # times driver ignored error */
	int	eeh_freeze_count;	/* # times this device froze up. */
	int	eeh_false_positives;	/* # times this device reported #ff's */
	u32	config_space[16];	/* saved PCI config space */
#endif
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
extern void * update_dn_pci_info(struct device_node *dn, void *data);

/* Get a device_node from a pci_dev.  This code must be fast except
 * in the case where the sysdata is incorrect and needs to be fixed
 * up (this will only happen once).
 * In this case the sysdata will have been inherited from a PCI host
 * bridge or a PCI-PCI bridge further up the tree, so it will point
 * to a valid struct pci_dn, just not the one we want.
 */
static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
{
	struct device_node *dn = dev->sysdata;
	struct pci_dn *pdn = dn->data;

	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
		return dn;	/* fast path.  sysdata is good */
	return fetch_dev_dn(dev);
}

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
{
	if (bus->self)
		return pci_device_to_OF_node(bus->self);
	else
		return bus->sysdata; /* Must be root bus (PHB) */
}

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	struct device_node *busdn = bus->sysdata;

	BUG_ON(busdn == NULL);
	return PCI_DN(busdn)->phb;
}


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_setup_phb_resources(struct pci_controller *hose);

#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
	return (unsigned long)-1;
}
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
	12	#include <linux/ioport.h>
	13
44ef3390 SR	14	struct device_node;
44ef3390 SR	15
fc3fb71c BH	16	enum {
	17	/* Force re-assigning all resources (ignore firmware
	18	* setup completely)
	19	*/
	20	PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
	21
	22	/* Re-assign all bus numbers */
	23	PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
	24
	25	/* Do not try to assign, just use existing setup */
	26	PPC_PCI_PROBE_ONLY = 0x00000004,
	27
	28	/* Don't bother with ISA alignment unless the bridge has
	29	* ISA forwarding enabled
	30	*/
	31	PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
fa462f2d BH	32
	33	/* Enable domain numbers in /proc */
	34	PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
	35	/* ... except for domain 0 */
	36	PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
fc3fb71c	37	};
7fe519c2 JB	38	#ifdef CONFIG_PCI
	39	extern unsigned int ppc_pci_flags;
	40
	41	static inline void ppc_pci_set_flags(int flags)
	42	{
	43	ppc_pci_flags = flags;
	44	}
	45
	46	static inline void ppc_pci_add_flags(int flags)
	47	{
	48	ppc_pci_flags \|= flags;
	49	}
	50
	51	static inline int ppc_pci_has_flag(int flag)
	52	{
	53	return (ppc_pci_flags & flag);
	54	}
	55	#else
	56	static inline void ppc_pci_set_flags(int flags) { }
	57	static inline void ppc_pci_add_flags(int flags) { }
	58	static inline int ppc_pci_has_flag(int flag)
	59	{
	60	return 0;
	61	}
	62	#endif
fc3fb71c BH	63
fc3fb71c BH	64
5531e41b KG	65	/*
	66	* Structure of a PCI controller (host bridge)
	67	*/
	68	struct pci_controller {
	69	struct pci_bus *bus;
a4c9e328	70	char is_dynamic;
7211991f SR	71	#ifdef CONFIG_PPC64
	72	int node;
	73	#endif
44ef3390	74	struct device_node *dn;
a4c9e328	75	struct list_head list_node;
5531e41b KG	76	struct device *parent;
	77
	78	int first_busno;
	79	int last_busno;
7211991f	80	#ifndef CONFIG_PPC64
5531e41b	81	int self_busno;
7211991f	82	#endif
5531e41b KG	83
5531e41b KG	84	void __iomem *io_base_virt;
7211991f SR	85	#ifdef CONFIG_PPC64
	86	void *io_base_alloc;
	87	#endif
5531e41b	88	resource_size_t io_base_phys;
13dccb9e	89	resource_size_t pci_io_size;
5531e41b KG	90
	91	/* Some machines (PReP) have a non 1:1 mapping of
	92	* the PCI memory space in the CPU bus space
	93	*/
	94	resource_size_t pci_mem_offset;
	95
e9f82cb7 BH	96	/* Some machines have a special region to forward the ISA
	97	* "memory" cycles such as VGA memory regions. Left to 0
	98	* if unsupported
	99	*/
	100	resource_size_t isa_mem_phys;
	101	resource_size_t isa_mem_size;
	102
5531e41b	103	struct pci_ops *ops;
70fbb938 SR	104	unsigned int __iomem *cfg_addr;
70fbb938 SR	105	void __iomem *cfg_data;
5531e41b	106
7211991f	107	#ifndef CONFIG_PPC64
5531e41b KG	108	/*
	109	* Used for variants of PCI indirect handling and possible quirks:
	110	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	111	* EXT_REG - provides access to PCI-e extended registers
	112	* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
	113	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	114	* to determine which bus number to match on when generating type0
	115	* config cycles
62c66c8e KG	116	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	117	* hanging if we don't have link and try to do config cycles to
	118	* anything but the PHB. Only allow talking to the PHB if this is
	119	* set.
2e56ff20	120	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	121	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	122	* the PLB4. Effectively disable MRM commands by setting this.
5531e41b	123	*/
7cd1de6b SR	124	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	125	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	126	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	127	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	128	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	129	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
5531e41b	130	u32 indirect_type;
7211991f	131	#endif /* !CONFIG_PPC64 */
5531e41b KG	132	/* Currently, we limit ourselves to 1 IO range and 3 mem
	133	* ranges since the common pci_bus structure can't handle more
	134	*/
	135	struct resource io_resource;
	136	struct resource mem_resources[3];
5516b540	137	int global_number; /* PCI domain number */
89d93347 BB	138
	139	resource_size_t dma_window_base_cur;
	140	resource_size_t dma_window_size;
	141
7211991f SR	142	#ifdef CONFIG_PPC64
7211991f SR	143	unsigned long buid;
7211991f SR	144
	145	void *private_data;
	146	#endif /* CONFIG_PPC64 */
5531e41b KG	147	};
5531e41b KG	148
7211991f SR	149	#ifndef CONFIG_PPC64
7211991f SR	150
f13f4ca8	151	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
5531e41b KG	152	{
	153	return bus->sysdata;
	154	}
	155
6dfbde20 BH	156	static inline int isa_vaddr_is_ioport(void __iomem *address)
	157	{
	158	/* No specific ISA handling on ppc32 at this stage, it
	159	* all goes through PCI
	160	*/
	161	return 0;
	162	}
	163
5531e41b KG	164	/* These are used for config access before all the PCI probing
5531e41b KG	165	has been done. */
7cd1de6b SR	166	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	167	int dev_fn, int where, u8 *val);
	168	extern int early_read_config_word(struct pci_controller *hose, int bus,
	169	int dev_fn, int where, u16 *val);
	170	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	171	int dev_fn, int where, u32 *val);
	172	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	173	int dev_fn, int where, u8 val);
	174	extern int early_write_config_word(struct pci_controller *hose, int bus,
	175	int dev_fn, int where, u16 val);
	176	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	177	int dev_fn, int where, u32 val);
5531e41b	178
38805e5f KG	179	extern int early_find_capability(struct pci_controller *hose, int bus,
	180	int dev_fn, int cap);
	181
5531e41b	182	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	183	resource_size_t cfg_addr,
d94bad82 VB	184	resource_size_t cfg_data, u32 flags);
7cd1de6b	185	#else /* CONFIG_PPC64 */
1da177e4	186
1635317f PM	187	/*
	188	* PCI stuff, for nodes representing PCI devices, pointed to
	189	* by device_node->data.
	190	*/
1635317f PM	191	struct iommu_table;
	192
	193	struct pci_dn {
7684b40c	194	int busno; /* pci bus number */
7684b40c	195	int devfn; /* pci device and function number */
b5166cc2	196
c2e221e8 LV	197	struct pci_controller phb; / for pci devices */
c2e221e8 LV	198	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	199	struct device_node node; / back-pointer to the device_node */
	200
	201	int pci_ext_config_space; /* for pci devices */
	202
	203	#ifdef CONFIG_EEH
b6ed42a7	204	struct pci_dev pcidev; / back-pointer to the pci device */
86bcab49	205	int class_code; /* pci device class */
1635317f PM	206	int eeh_mode; /* See eeh.h for possible EEH_MODEs */
1635317f PM	207	int eeh_config_addr;
25e591f6	208	int eeh_pe_config_addr; /* new-style partition endpoint address */
7cd1de6b SR	209	int eeh_check_count; /* # times driver ignored error */
	210	int eeh_freeze_count; /* # times this device froze up. */
	211	int eeh_false_positives; /* # times this device reported #ff's */
1635317f	212	u32 config_space[16]; /* saved PCI config space */
c2e221e8	213	#endif
1635317f PM	214	};
	215
	216	/* Get the pointer to a device_node's pci_dn */
	217	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	218
7cd1de6b	219	extern struct device_node fetch_dev_dn(struct pci_dev dev);
2eb4afb6	220	extern void * update_dn_pci_info(struct device_node dn, void data);
1da177e4	221
1635317f PM	222	/* Get a device_node from a pci_dev. This code must be fast except
	223	* in the case where the sysdata is incorrect and needs to be fixed
	224	* up (this will only happen once).
	225	* In this case the sysdata will have been inherited from a PCI host
	226	* bridge or a PCI-PCI bridge further up the tree, so it will point
	227	* to a valid struct pci_dn, just not the one we want.
1da177e4 LT	228	*/
	229	static inline struct device_node pci_device_to_OF_node(struct pci_dev dev)
	230	{
	231	struct device_node *dn = dev->sysdata;
1635317f	232	struct pci_dn *pdn = dn->data;
1da177e4	233
1635317f	234	if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
1da177e4	235	return dn; /* fast path. sysdata is good */
1635317f	236	return fetch_dev_dn(dev);
1da177e4 LT	237	}
1da177e4 LT	238
40ef8cbc PM	239	static inline int pci_device_from_OF_node(struct device_node *np,
	240	u8 bus, u8 devfn)
	241	{
	242	if (!PCI_DN(np))
	243	return -ENODEV;
	244	*bus = PCI_DN(np)->busno;
	245	*devfn = PCI_DN(np)->devfn;
	246	return 0;
	247	}
	248
1da177e4 LT	249	static inline struct device_node pci_bus_to_OF_node(struct pci_bus bus)
	250	{
	251	if (bus->self)
	252	return pci_device_to_OF_node(bus->self);
	253	else
	254	return bus->sysdata; /* Must be root bus (PHB) */
	255	}
	256
2bf6a8fa	257	/** Find the bus corresponding to the indicated device node */
7cd1de6b	258	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	259
2bf6a8fa	260	/** Remove all of the PCI devices under this bus */
7cd1de6b	261	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	262
2bf6a8fa LV	263	/** Discover new pci devices under this bus, and add them */
7cd1de6b	264	extern void pcibios_add_pci_devices(struct pci_bus *bus);
1da177e4	265
f13f4ca8	266	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
1da177e4 LT	267	{
	268	struct device_node *busdn = bus->sysdata;
	269
	270	BUG_ON(busdn == NULL);
1635317f	271	return PCI_DN(busdn)->phb;
1da177e4 LT	272	}
1da177e4 LT	273
b5166cc2	274
3d5134ee BH	275	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	276
6dfbde20 BH	277	static inline int isa_vaddr_is_ioport(void __iomem *address)
	278	{
	279	/* Check if address hits the reserved legacy IO range */
	280	unsigned long ea = (unsigned long)address;
	281	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	282	}
	283
3d5134ee BH	284	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	285	extern int pcibios_map_io_space(struct pci_bus *bus);
	286
357518fa AB	287	#ifdef CONFIG_NUMA
	288	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	289	#else
	290	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	291	#endif
	292
7cd1de6b	293	#endif /* CONFIG_PPC64 */
5531e41b KG	294
5531e41b KG	295	/* Get the PCI host controller for an OF device */
7cd1de6b SR	296	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	297	struct device_node* node);
5531e41b KG	298
5531e41b KG	299	/* Fill up host controller resources from the OF node */
7cd1de6b SR	300	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	301	struct device_node *dev, int primary);
5531e41b	302
5131d4d8	303	/* Allocate & free a PCI host bridge structure */
7cd1de6b	304	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8	305	extern void pcibios_free_controller(struct pci_controller *phb);
53280323	306	extern void pcibios_setup_phb_resources(struct pci_controller *hose);
5131d4d8	307
5531e41b KG	308	#ifdef CONFIG_PCI
5531e41b KG	309	extern unsigned long pci_address_to_pio(phys_addr_t address);
6dfbde20	310	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b KG	311	#else
	312	static inline unsigned long pci_address_to_pio(phys_addr_t address)
	313	{
	314	return (unsigned long)-1;
	315	}
6dfbde20 BH	316	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	317	{
	318	return 0;
	319	}
7cd1de6b	320	#endif /* CONFIG_PCI */
5531e41b	321
7cd1de6b SR	322	#endif /* __KERNEL__ */
7cd1de6b SR	323	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */