[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / include / asm / pci-bridge.h

#ifndef _ASM_POWERPC_PCI_BRIDGE_H
#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <asm-generic/pci-bridge.h>

/* Return values for pci_controller_ops.probe_mode function */
#define PCI_PROBE_NONE		-1	/* Don't look at this bus at all */
#define PCI_PROBE_NORMAL	0	/* Do normal PCI probing */
#define PCI_PROBE_DEVTREE	1	/* Instantiate from device tree */

struct device_node;

/*
 * PCI controller operations
 */
struct pci_controller_ops {
	void		(*dma_dev_setup)(struct pci_dev *dev);
	void		(*dma_bus_setup)(struct pci_bus *bus);

	int		(*probe_mode)(struct pci_bus *);
};

/*
 * Structure of a PCI controller (host bridge)
 */
struct pci_controller {
	struct pci_bus *bus;
	char is_dynamic;
#ifdef CONFIG_PPC64
	int node;
#endif
	struct device_node *dn;
	struct list_head list_node;
	struct device *parent;

	int first_busno;
	int last_busno;
	int self_busno;
	struct resource busn;

	void __iomem *io_base_virt;
#ifdef CONFIG_PPC64
	void *io_base_alloc;
#endif
	resource_size_t io_base_phys;
	resource_size_t pci_io_size;

	/* Some machines have a special region to forward the ISA
	 * "memory" cycles such as VGA memory regions. Left to 0
	 * if unsupported
	 */
	resource_size_t	isa_mem_phys;
	resource_size_t	isa_mem_size;

	struct pci_controller_ops controller_ops;
	struct pci_ops *ops;
	unsigned int __iomem *cfg_addr;
	void __iomem *cfg_data;

	/*
	 * Used for variants of PCI indirect handling and possible quirks:
	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	 *  EXT_REG - provides access to PCI-e extended registers
	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	 *   to determine which bus number to match on when generating type0
	 *   config cycles
	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	 *   hanging if we don't have link and try to do config cycles to
	 *   anything but the PHB.  Only allow talking to the PHB if this is
	 *   set.
	 *  BIG_ENDIAN - cfg_addr is a big endian register
	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
	 *   the PLB4.  Effectively disable MRM commands by setting this.
	 *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
	 *   link status is in a RC PCIe cfg register (vs being a SoC register)
	 */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
#define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
#define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
#define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK	0x00000040
	u32 indirect_type;
	/* Currently, we limit ourselves to 1 IO range and 3 mem
	 * ranges since the common pci_bus structure can't handle more
	 */
	struct resource	io_resource;
	struct resource mem_resources[3];
	resource_size_t mem_offset[3];
	int global_number;		/* PCI domain number */

	resource_size_t dma_window_base_cur;
	resource_size_t dma_window_size;

#ifdef CONFIG_PPC64
	unsigned long buid;
	struct pci_dn *pci_data;
#endif	/* CONFIG_PPC64 */

	void *private_data;
};

/* These are used for config access before all the PCI probing
   has been done. */
extern int early_read_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 *val);
extern int early_read_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 *val);
extern int early_read_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 *val);
extern int early_write_config_byte(struct pci_controller *hose, int bus,
			int dev_fn, int where, u8 val);
extern int early_write_config_word(struct pci_controller *hose, int bus,
			int dev_fn, int where, u16 val);
extern int early_write_config_dword(struct pci_controller *hose, int bus,
			int dev_fn, int where, u32 val);

extern int early_find_capability(struct pci_controller *hose, int bus,
				 int dev_fn, int cap);

extern void setup_indirect_pci(struct pci_controller* hose,
			       resource_size_t cfg_addr,
			       resource_size_t cfg_data, u32 flags);

extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
				int offset, int len, u32 *val);

extern int __indirect_read_config(struct pci_controller *hose,
				  unsigned char bus_number, unsigned int devfn,
				  int offset, int len, u32 *val);

extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
				 int offset, int len, u32 val);

static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
{
	return bus->sysdata;
}

#ifndef CONFIG_PPC64

extern int pci_device_from_OF_node(struct device_node *node,
				   u8 *bus, u8 *devfn);
extern void pci_create_OF_bus_map(void);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* No specific ISA handling on ppc32 at this stage, it
	 * all goes through PCI
	 */
	return 0;
}

#else	/* CONFIG_PPC64 */

/*
 * PCI stuff, for nodes representing PCI devices, pointed to
 * by device_node->data.
 */
struct iommu_table;

struct pci_dn {
	int     flags;

	int	busno;			/* pci bus number */
	int	devfn;			/* pci device and function number */
	int	vendor_id;		/* Vendor ID */
	int	device_id;		/* Device ID */
	int	class_code;		/* Device class code */

	struct  pci_dn *parent;
	struct  pci_controller *phb;	/* for pci devices */
	struct	iommu_table *iommu_table;	/* for phb's or bridges */
	struct	device_node *node;	/* back-pointer to the device_node */

	int	pci_ext_config_space;	/* for pci devices */

	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
#ifdef CONFIG_EEH
	struct eeh_dev *edev;		/* eeh device */
#endif
#define IODA_INVALID_PE		(-1)
#ifdef CONFIG_PPC_POWERNV
	int	pe_number;
#endif
	struct list_head child_list;
	struct list_head list;
};

/* Get the pointer to a device_node's pci_dn */
#define PCI_DN(dn)	((struct pci_dn *) (dn)->data)

extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
					   int devfn);
extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
extern void *update_dn_pci_info(struct device_node *dn, void *data);

static inline int pci_device_from_OF_node(struct device_node *np,
					  u8 *bus, u8 *devfn)
{
	if (!PCI_DN(np))
		return -ENODEV;
	*bus = PCI_DN(np)->busno;
	*devfn = PCI_DN(np)->devfn;
	return 0;
}

#if defined(CONFIG_EEH)
static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
{
	return pdn ? pdn->edev : NULL;
}
#else
#define pdn_to_eeh_dev(x)	(NULL)
#endif

/** Find the bus corresponding to the indicated device node */
extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);

/** Remove all of the PCI devices under this bus */
extern void pcibios_remove_pci_devices(struct pci_bus *bus);

/** Discover new pci devices under this bus, and add them */
extern void pcibios_add_pci_devices(struct pci_bus *bus);


extern void isa_bridge_find_early(struct pci_controller *hose);

static inline int isa_vaddr_is_ioport(void __iomem *address)
{
	/* Check if address hits the reserved legacy IO range */
	unsigned long ea = (unsigned long)address;
	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
}

extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);

#ifdef CONFIG_NUMA
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
#else
#define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
#endif

#endif	/* CONFIG_PPC64 */

/* Get the PCI host controller for an OF device */
extern struct pci_controller *pci_find_hose_for_OF_device(
			struct device_node* node);

/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
			struct device_node *dev, int primary);

/* Allocate & free a PCI host bridge structure */
extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);

#ifdef CONFIG_PCI
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
	return 0;
}
#endif	/* CONFIG_PCI */

/*
 * Shims to prefer pci_controller version over ppc_md where available.
 */
static inline void pci_dma_dev_setup(struct pci_dev *dev)
{
	struct pci_controller *phb = pci_bus_to_host(dev->bus);

	if (phb->controller_ops.dma_dev_setup)
		phb->controller_ops.dma_dev_setup(dev);
	else if (ppc_md.pci_dma_dev_setup)
		ppc_md.pci_dma_dev_setup(dev);
}

static inline void pci_dma_bus_setup(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (phb->controller_ops.dma_bus_setup)
		phb->controller_ops.dma_bus_setup(bus);
	else if (ppc_md.pci_dma_bus_setup)
		ppc_md.pci_dma_bus_setup(bus);
}

static inline int pci_probe_mode(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);

	if (phb->controller_ops.probe_mode)
		return phb->controller_ops.probe_mode(bus);
	if (ppc_md.pci_probe_mode)
		return ppc_md.pci_probe_mode(bus);
	return PCI_PROBE_NORMAL;
}

#endif	/* __KERNEL__ */
#endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_PCI_BRIDGE_H
047ea784 PM	2	#define _ASM_POWERPC_PCI_BRIDGE_H
88ced031	3	#ifdef __KERNEL__
7cd1de6b SR	4	/*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
5531e41b	10	#include <linux/pci.h>
a4c9e328 KG	11	#include <linux/list.h>
a4c9e328 KG	12	#include <linux/ioport.h>
f4ffd5e5	13	#include <asm-generic/pci-bridge.h>
a4c9e328	14
ff9df8c8 DA	15	/* Return values for pci_controller_ops.probe_mode function */
	16	#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
	17	#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
	18	#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
	19
44ef3390 SR	20	struct device_node;
44ef3390 SR	21
e02def5b DA	22	/*
	23	* PCI controller operations
	24	*/
	25	struct pci_controller_ops {
	26	void (dma_dev_setup)(struct pci_dev dev);
b122c954	27	void (dma_bus_setup)(struct pci_bus bus);
ff9df8c8 DA	28
ff9df8c8 DA	29	int (probe_mode)(struct pci_bus );
e02def5b DA	30	};
e02def5b DA	31
5531e41b KG	32	/*
	33	* Structure of a PCI controller (host bridge)
	34	*/
	35	struct pci_controller {
	36	struct pci_bus *bus;
a4c9e328	37	char is_dynamic;
7211991f SR	38	#ifdef CONFIG_PPC64
	39	int node;
	40	#endif
44ef3390	41	struct device_node *dn;
a4c9e328	42	struct list_head list_node;
5531e41b KG	43	struct device *parent;
	44
	45	int first_busno;
	46	int last_busno;
	47	int self_busno;
be8e60d8	48	struct resource busn;
5531e41b KG	49
5531e41b KG	50	void __iomem *io_base_virt;
7211991f SR	51	#ifdef CONFIG_PPC64
	52	void *io_base_alloc;
	53	#endif
5531e41b	54	resource_size_t io_base_phys;
13dccb9e	55	resource_size_t pci_io_size;
5531e41b	56
e9f82cb7 BH	57	/* Some machines have a special region to forward the ISA
	58	* "memory" cycles such as VGA memory regions. Left to 0
	59	* if unsupported
	60	*/
	61	resource_size_t isa_mem_phys;
	62	resource_size_t isa_mem_size;
	63
e02def5b	64	struct pci_controller_ops controller_ops;
5531e41b	65	struct pci_ops *ops;
70fbb938 SR	66	unsigned int __iomem *cfg_addr;
70fbb938 SR	67	void __iomem *cfg_data;
5531e41b KG	68
	69	/*
	70	* Used for variants of PCI indirect handling and possible quirks:
	71	* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
	72	* EXT_REG - provides access to PCI-e extended registers
25985edc	73	* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
5531e41b KG	74	* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
	75	* to determine which bus number to match on when generating type0
	76	* config cycles
62c66c8e KG	77	* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
	78	* hanging if we don't have link and try to do config cycles to
	79	* anything but the PHB. Only allow talking to the PHB if this is
	80	* set.
2e56ff20	81	* BIG_ENDIAN - cfg_addr is a big endian register
5ce4b596 JB	82	* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
5ce4b596 JB	83	* the PLB4. Effectively disable MRM commands by setting this.
34642bbb KG	84	* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
34642bbb KG	85	* link status is in a RC PCIe cfg register (vs being a SoC register)
5531e41b	86	*/
7cd1de6b SR	87	#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
	88	#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
	89	#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
	90	#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
	91	#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
5ce4b596	92	#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
34642bbb	93	#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
5531e41b	94	u32 indirect_type;
5531e41b KG	95	/* Currently, we limit ourselves to 1 IO range and 3 mem
	96	* ranges since the common pci_bus structure can't handle more
	97	*/
	98	struct resource io_resource;
	99	struct resource mem_resources[3];
3fd47f06	100	resource_size_t mem_offset[3];
5516b540	101	int global_number; /* PCI domain number */
89d93347 BB	102
	103	resource_size_t dma_window_base_cur;
	104	resource_size_t dma_window_size;
	105
7211991f SR	106	#ifdef CONFIG_PPC64
7211991f SR	107	unsigned long buid;
cca87d30	108	struct pci_dn *pci_data;
34642bbb	109	#endif /* CONFIG_PPC64 */
7211991f SR	110
7211991f SR	111	void *private_data;
5531e41b KG	112	};
5531e41b KG	113
5531e41b KG	114	/* These are used for config access before all the PCI probing
5531e41b KG	115	has been done. */
7cd1de6b SR	116	extern int early_read_config_byte(struct pci_controller *hose, int bus,
	117	int dev_fn, int where, u8 *val);
	118	extern int early_read_config_word(struct pci_controller *hose, int bus,
	119	int dev_fn, int where, u16 *val);
	120	extern int early_read_config_dword(struct pci_controller *hose, int bus,
	121	int dev_fn, int where, u32 *val);
	122	extern int early_write_config_byte(struct pci_controller *hose, int bus,
	123	int dev_fn, int where, u8 val);
	124	extern int early_write_config_word(struct pci_controller *hose, int bus,
	125	int dev_fn, int where, u16 val);
	126	extern int early_write_config_dword(struct pci_controller *hose, int bus,
	127	int dev_fn, int where, u32 val);
5531e41b	128
38805e5f KG	129	extern int early_find_capability(struct pci_controller *hose, int bus,
	130	int dev_fn, int cap);
	131
5531e41b	132	extern void setup_indirect_pci(struct pci_controller* hose,
d94bad82 VB	133	resource_size_t cfg_addr,
d94bad82 VB	134	resource_size_t cfg_data, u32 flags);
89c2dd62	135
50d8f87d RI	136	extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
	137	int offset, int len, u32 *val);
	138
6d5f6a0e KP	139	extern int __indirect_read_config(struct pci_controller *hose,
	140	unsigned char bus_number, unsigned int devfn,
	141	int offset, int len, u32 *val);
	142
50d8f87d RI	143	extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
	144	int offset, int len, u32 val);
	145
89c2dd62 KG	146	static inline struct pci_controller pci_bus_to_host(const struct pci_bus bus)
	147	{
	148	return bus->sysdata;
	149	}
	150
98d9f30c BH	151	#ifndef CONFIG_PPC64
	152
	153	extern int pci_device_from_OF_node(struct device_node *node,
	154	u8 bus, u8 devfn);
	155	extern void pci_create_OF_bus_map(void);
	156
89c2dd62 KG	157	static inline int isa_vaddr_is_ioport(void __iomem *address)
	158	{
	159	/* No specific ISA handling on ppc32 at this stage, it
	160	* all goes through PCI
	161	*/
	162	return 0;
	163	}
	164
7cd1de6b	165	#else /* CONFIG_PPC64 */
1da177e4	166
1635317f PM	167	/*
	168	* PCI stuff, for nodes representing PCI devices, pointed to
	169	* by device_node->data.
	170	*/
1635317f PM	171	struct iommu_table;
	172
	173	struct pci_dn {
cca87d30 GS	174	int flags;
cca87d30 GS	175
7684b40c	176	int busno; /* pci bus number */
7684b40c	177	int devfn; /* pci device and function number */
c035ff1d GS	178	int vendor_id; /* Vendor ID */
	179	int device_id; /* Device ID */
	180	int class_code; /* Device class code */
b5166cc2	181
cca87d30	182	struct pci_dn *parent;
c2e221e8 LV	183	struct pci_controller phb; / for pci devices */
c2e221e8 LV	184	struct iommu_table iommu_table; / for phb's or bridges */
c2e221e8 LV	185	struct device_node node; / back-pointer to the device_node */
	186
	187	int pci_ext_config_space; /* for pci devices */
	188
b6ed42a7	189	struct pci_dev pcidev; / back-pointer to the pci device */
184cd4a3	190	#ifdef CONFIG_EEH
2a0352fa	191	struct eeh_dev edev; / eeh device */
c2e221e8	192	#endif
184cd4a3 BH	193	#define IODA_INVALID_PE (-1)
	194	#ifdef CONFIG_PPC_POWERNV
	195	int pe_number;
	196	#endif
cca87d30 GS	197	struct list_head child_list;
cca87d30 GS	198	struct list_head list;
1635317f PM	199	};
	200
	201	/* Get the pointer to a device_node's pci_dn */
	202	#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
	203
cca87d30 GS	204	extern struct pci_dn pci_get_pdn_by_devfn(struct pci_bus bus,
cca87d30 GS	205	int devfn);
b72c1f65	206	extern struct pci_dn pci_get_pdn(struct pci_dev pdev);
cca87d30	207	extern void update_dn_pci_info(struct device_node dn, void *data);
1da177e4	208
40ef8cbc PM	209	static inline int pci_device_from_OF_node(struct device_node *np,
	210	u8 bus, u8 devfn)
	211	{
	212	if (!PCI_DN(np))
	213	return -ENODEV;
	214	*bus = PCI_DN(np)->busno;
	215	*devfn = PCI_DN(np)->devfn;
	216	return 0;
	217	}
	218
2a0352fa	219	#if defined(CONFIG_EEH)
e8e9b34c GS	220	static inline struct eeh_dev pdn_to_eeh_dev(struct pci_dn pdn)
	221	{
	222	return pdn ? pdn->edev : NULL;
	223	}
f8f7d63f	224	#else
e8e9b34c	225	#define pdn_to_eeh_dev(x) (NULL)
2a0352fa GS	226	#endif
2a0352fa GS	227
2bf6a8fa	228	/** Find the bus corresponding to the indicated device node */
7cd1de6b	229	extern struct pci_bus pcibios_find_pci_bus(struct device_node dn);
2bf6a8fa	230
2bf6a8fa	231	/** Remove all of the PCI devices under this bus */
7cd1de6b	232	extern void pcibios_remove_pci_devices(struct pci_bus *bus);
2bf6a8fa LV	233
2bf6a8fa LV	234	/** Discover new pci devices under this bus, and add them */
7cd1de6b	235	extern void pcibios_add_pci_devices(struct pci_bus *bus);
1da177e4	236
b5166cc2	237
3d5134ee BH	238	extern void isa_bridge_find_early(struct pci_controller *hose);
3d5134ee BH	239
6dfbde20 BH	240	static inline int isa_vaddr_is_ioport(void __iomem *address)
	241	{
	242	/* Check if address hits the reserved legacy IO range */
	243	unsigned long ea = (unsigned long)address;
	244	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
	245	}
	246
3d5134ee BH	247	extern int pcibios_unmap_io_space(struct pci_bus *bus);
	248	extern int pcibios_map_io_space(struct pci_bus *bus);
	249
357518fa AB	250	#ifdef CONFIG_NUMA
	251	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
	252	#else
	253	#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
	254	#endif
	255
7cd1de6b	256	#endif /* CONFIG_PPC64 */
5531e41b KG	257
5531e41b KG	258	/* Get the PCI host controller for an OF device */
7cd1de6b SR	259	extern struct pci_controller *pci_find_hose_for_OF_device(
7cd1de6b SR	260	struct device_node* node);
5531e41b KG	261
5531e41b KG	262	/* Fill up host controller resources from the OF node */
7cd1de6b SR	263	extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
7cd1de6b SR	264	struct device_node *dev, int primary);
5531e41b	265
5131d4d8	266	/* Allocate & free a PCI host bridge structure */
7cd1de6b	267	extern struct pci_controller pcibios_alloc_controller(struct device_node dev);
5131d4d8 BH	268	extern void pcibios_free_controller(struct pci_controller *phb);
5131d4d8 BH	269
5531e41b	270	#ifdef CONFIG_PCI
6dfbde20	271	extern int pcibios_vaddr_is_ioport(void __iomem *address);
5531e41b	272	#else
6dfbde20 BH	273	static inline int pcibios_vaddr_is_ioport(void __iomem *address)
	274	{
	275	return 0;
	276	}
7cd1de6b	277	#endif /* CONFIG_PCI */
5531e41b	278
e02def5b DA	279	/*
	280	* Shims to prefer pci_controller version over ppc_md where available.
	281	*/
	282	static inline void pci_dma_dev_setup(struct pci_dev *dev)
	283	{
	284	struct pci_controller *phb = pci_bus_to_host(dev->bus);
	285
	286	if (phb->controller_ops.dma_dev_setup)
	287	phb->controller_ops.dma_dev_setup(dev);
	288	else if (ppc_md.pci_dma_dev_setup)
	289	ppc_md.pci_dma_dev_setup(dev);
	290	}
	291
b122c954 DA	292	static inline void pci_dma_bus_setup(struct pci_bus *bus)
	293	{
	294	struct pci_controller *phb = pci_bus_to_host(bus);
	295
	296	if (phb->controller_ops.dma_bus_setup)
	297	phb->controller_ops.dma_bus_setup(bus);
	298	else if (ppc_md.pci_dma_bus_setup)
	299	ppc_md.pci_dma_bus_setup(bus);
	300	}
	301
ff9df8c8 DA	302	static inline int pci_probe_mode(struct pci_bus *bus)
	303	{
	304	struct pci_controller *phb = pci_bus_to_host(bus);
	305
	306	if (phb->controller_ops.probe_mode)
	307	return phb->controller_ops.probe_mode(bus);
	308	if (ppc_md.pci_probe_mode)
	309	return ppc_md.pci_probe_mode(bus);
	310	return PCI_PROBE_NORMAL;
	311	}
	312
7cd1de6b SR	313	#endif /* __KERNEL__ */
7cd1de6b SR	314	#endif /* _ASM_POWERPC_PCI_BRIDGE_H */