]>
Commit | Line | Data |
---|---|---|
f8ef2705 PM |
1 | #ifndef __ASM_POWERPC_PCI_H |
2 | #define __ASM_POWERPC_PCI_H | |
1da177e4 LT |
3 | #ifdef __KERNEL__ |
4 | ||
5 | /* | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/dma-mapping.h> | |
16 | ||
17 | #include <asm/machdep.h> | |
18 | #include <asm/scatterlist.h> | |
19 | #include <asm/io.h> | |
20 | #include <asm/prom.h> | |
f8ef2705 | 21 | #include <asm/pci-bridge.h> |
1da177e4 LT |
22 | |
23 | #include <asm-generic/pci-dma-compat.h> | |
24 | ||
fbe65447 GL |
25 | /* Return values for ppc_md.pci_probe_mode function */ |
26 | #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ | |
27 | #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ | |
28 | #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ | |
29 | ||
1da177e4 LT |
30 | #define PCIBIOS_MIN_IO 0x1000 |
31 | #define PCIBIOS_MIN_MEM 0x10000000 | |
32 | ||
33 | struct pci_dev; | |
34 | ||
f8ef2705 PM |
35 | /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ |
36 | #define IOBASE_BRIDGE_NUMBER 0 | |
37 | #define IOBASE_MEMORY 1 | |
38 | #define IOBASE_IO 2 | |
39 | #define IOBASE_ISA_IO 3 | |
40 | #define IOBASE_ISA_MEM 4 | |
41 | ||
42 | /* | |
43 | * Set this to 1 if you want the kernel to re-assign all PCI | |
3fd94c6b | 44 | * bus numbers (don't do that on ppc64 yet !) |
f8ef2705 | 45 | */ |
7fe519c2 JB |
46 | #define pcibios_assign_all_busses() \ |
47 | (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS)) | |
1da177e4 | 48 | #define pcibios_scan_all_fns(a, b) 0 |
1da177e4 LT |
49 | |
50 | static inline void pcibios_set_master(struct pci_dev *dev) | |
51 | { | |
52 | /* No special bus mastering setup handling */ | |
53 | } | |
54 | ||
c9c3e457 | 55 | static inline void pcibios_penalize_isa_irq(int irq, int active) |
1da177e4 LT |
56 | { |
57 | /* We don't do dynamic PCI IRQ allocation */ | |
58 | } | |
59 | ||
60 | #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ | |
61 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) | |
62 | { | |
63 | if (ppc_md.pci_get_legacy_ide_irq) | |
64 | return ppc_md.pci_get_legacy_ide_irq(dev, channel); | |
65 | return channel ? 15 : 14; | |
66 | } | |
67 | ||
4fc665b8 | 68 | #ifdef CONFIG_PCI |
45223c54 FT |
69 | extern void set_pci_dma_ops(struct dma_map_ops *dma_ops); |
70 | extern struct dma_map_ops *get_pci_dma_ops(void); | |
4fc665b8 BB |
71 | #else /* CONFIG_PCI */ |
72 | #define set_pci_dma_ops(d) | |
73 | #define get_pci_dma_ops() NULL | |
74 | #endif | |
75 | ||
f8ef2705 | 76 | #ifdef CONFIG_PPC64 |
edb2d97e MW |
77 | |
78 | /* | |
79 | * We want to avoid touching the cacheline size or MWI bit. | |
80 | * pSeries firmware sets the cacheline size (which is not the cpu cacheline | |
81 | * size in all cases) and hardware treats MWI the same as memory write. | |
82 | */ | |
83 | #define PCI_DISABLE_MWI | |
1da177e4 | 84 | |
98747770 | 85 | #ifdef CONFIG_PCI |
e24c2d96 DM |
86 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, |
87 | enum pci_dma_burst_strategy *strat, | |
88 | unsigned long *strategy_parameter) | |
89 | { | |
90 | unsigned long cacheline_size; | |
91 | u8 byte; | |
92 | ||
93 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); | |
94 | if (byte == 0) | |
95 | cacheline_size = 1024; | |
96 | else | |
97 | cacheline_size = (int) byte * 4; | |
98 | ||
99 | *strat = PCI_DMA_BURST_MULTIPLE; | |
100 | *strategy_parameter = cacheline_size; | |
101 | } | |
bb4a61b6 | 102 | #endif |
e24c2d96 | 103 | |
f8ef2705 PM |
104 | #else /* 32-bit */ |
105 | ||
106 | #ifdef CONFIG_PCI | |
107 | static inline void pci_dma_burst_advice(struct pci_dev *pdev, | |
108 | enum pci_dma_burst_strategy *strat, | |
109 | unsigned long *strategy_parameter) | |
110 | { | |
111 | *strat = PCI_DMA_BURST_INFINITY; | |
112 | *strategy_parameter = ~0UL; | |
113 | } | |
114 | #endif | |
f8ef2705 PM |
115 | #endif /* CONFIG_PPC64 */ |
116 | ||
5516b540 KG |
117 | extern int pci_domain_nr(struct pci_bus *bus); |
118 | ||
fa462f2d BH |
119 | /* Decide whether to display the domain number in /proc */ |
120 | extern int pci_proc_domain(struct pci_bus *bus); | |
121 | ||
11df1f05 ME |
122 | /* MSI arch hooks */ |
123 | #define arch_setup_msi_irqs arch_setup_msi_irqs | |
124 | #define arch_teardown_msi_irqs arch_teardown_msi_irqs | |
125 | #define arch_msi_check_device arch_msi_check_device | |
fa462f2d | 126 | |
1da177e4 LT |
127 | struct vm_area_struct; |
128 | /* Map a range of PCI memory or I/O space for a device into user space */ | |
129 | int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, | |
130 | enum pci_mmap_state mmap_state, int write_combine); | |
131 | ||
132 | /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ | |
133 | #define HAVE_PCI_MMAP 1 | |
134 | ||
e9f82cb7 BH |
135 | extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, |
136 | size_t count); | |
137 | extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, | |
138 | size_t count); | |
139 | extern int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
140 | struct vm_area_struct *vma, | |
141 | enum pci_mmap_state mmap_state); | |
142 | ||
143 | #define HAVE_PCI_LEGACY 1 | |
144 | ||
1d4454e7 RD |
145 | #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE) |
146 | /* | |
147 | * For 64-bit kernels, pci_unmap_{single,page} is not a nop. | |
148 | * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and | |
149 | * so on are not nops. | |
150 | * and thus... | |
151 | */ | |
1da177e4 LT |
152 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ |
153 | dma_addr_t ADDR_NAME; | |
154 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ | |
155 | __u32 LEN_NAME; | |
156 | #define pci_unmap_addr(PTR, ADDR_NAME) \ | |
157 | ((PTR)->ADDR_NAME) | |
158 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ | |
159 | (((PTR)->ADDR_NAME) = (VAL)) | |
160 | #define pci_unmap_len(PTR, LEN_NAME) \ | |
161 | ((PTR)->LEN_NAME) | |
162 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ | |
163 | (((PTR)->LEN_NAME) = (VAL)) | |
164 | ||
1d4454e7 RD |
165 | #else /* 32-bit && coherent */ |
166 | ||
167 | /* pci_unmap_{page,single} is a nop so... */ | |
168 | #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) | |
169 | #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) | |
170 | #define pci_unmap_addr(PTR, ADDR_NAME) (0) | |
171 | #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) | |
172 | #define pci_unmap_len(PTR, LEN_NAME) (0) | |
173 | #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) | |
174 | ||
175 | #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */ | |
176 | ||
177 | #ifdef CONFIG_PPC64 | |
178 | ||
f8ef2705 PM |
179 | /* The PCI address space does not equal the physical memory address |
180 | * space (we have an IOMMU). The IDE and SCSI device layers use | |
1da177e4 LT |
181 | * this boolean for bounce buffer decisions. |
182 | */ | |
183 | #define PCI_DMA_BUS_IS_PHYS (0) | |
f8ef2705 PM |
184 | |
185 | #else /* 32-bit */ | |
186 | ||
187 | /* The PCI address space does equal the physical memory | |
188 | * address space (no IOMMU). The IDE and SCSI device layers use | |
189 | * this boolean for bounce buffer decisions. | |
190 | */ | |
191 | #define PCI_DMA_BUS_IS_PHYS (1) | |
192 | ||
f8ef2705 | 193 | #endif /* CONFIG_PPC64 */ |
1d4454e7 | 194 | |
f8ef2705 PM |
195 | extern void pcibios_resource_to_bus(struct pci_dev *dev, |
196 | struct pci_bus_region *region, | |
1da177e4 LT |
197 | struct resource *res); |
198 | ||
f8ef2705 PM |
199 | extern void pcibios_bus_to_resource(struct pci_dev *dev, |
200 | struct resource *res, | |
43c34735 DB |
201 | struct pci_bus_region *region); |
202 | ||
facf0787 LV |
203 | extern void pcibios_claim_one_bus(struct pci_bus *b); |
204 | ||
fd6852c8 | 205 | extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); |
e90a1318 | 206 | |
3fd94c6b BH |
207 | extern void pcibios_resource_survey(void); |
208 | ||
1da177e4 | 209 | extern struct pci_controller *init_phb_dynamic(struct device_node *dn); |
fd6852c8 | 210 | extern int remove_phb_dynamic(struct pci_controller *phb); |
1da177e4 | 211 | |
ead83717 JR |
212 | extern struct pci_dev *of_create_pci_dev(struct device_node *node, |
213 | struct pci_bus *bus, int devfn); | |
214 | ||
215 | extern void of_scan_pci_bridge(struct device_node *node, | |
216 | struct pci_dev *dev); | |
217 | ||
218 | extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); | |
8b8da358 | 219 | extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); |
ead83717 | 220 | |
1da177e4 LT |
221 | extern int pci_read_irq_line(struct pci_dev *dev); |
222 | ||
1da177e4 LT |
223 | struct file; |
224 | extern pgprot_t pci_phys_mem_access_prot(struct file *file, | |
8b150478 | 225 | unsigned long pfn, |
1da177e4 LT |
226 | unsigned long size, |
227 | pgprot_t prot); | |
228 | ||
2311b1f2 ME |
229 | #define HAVE_ARCH_PCI_RESOURCE_TO_USER |
230 | extern void pci_resource_to_user(const struct pci_dev *dev, int bar, | |
231 | const struct resource *rsrc, | |
e31dd6e4 | 232 | resource_size_t *start, resource_size_t *end); |
1da177e4 | 233 | |
8b8da358 BH |
234 | extern void pcibios_setup_bus_devices(struct pci_bus *bus); |
235 | extern void pcibios_setup_bus_self(struct pci_bus *bus); | |
e9f82cb7 | 236 | |
1da177e4 | 237 | #endif /* __KERNEL__ */ |
f8ef2705 | 238 | #endif /* __ASM_POWERPC_PCI_H */ |