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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
80c49c7e IM |
2 | /* |
3 | * Copyright 2014 IBM Corp. | |
80c49c7e IM |
4 | */ |
5 | ||
6 | #ifndef _ASM_PNV_PCI_H | |
7 | #define _ASM_PNV_PCI_H | |
8 | ||
9 | #include <linux/pci.h> | |
89379f16 | 10 | #include <linux/pci_hotplug.h> |
4ee11c1a | 11 | #include <linux/irq.h> |
ec249dd8 | 12 | #include <misc/cxl-base.h> |
ea0d856c | 13 | #include <asm/opal-api.h> |
80c49c7e | 14 | |
066bcd78 | 15 | #define PCI_SLOT_ID_PREFIX (1UL << 63) |
ebe22531 GS |
16 | #define PCI_SLOT_ID(phb_id, bdfn) \ |
17 | (PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb_id)) | |
18 | ||
7e19bf32 | 19 | extern int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id); |
ea0d856c GS |
20 | extern int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len); |
21 | extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state); | |
22 | extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state); | |
23 | extern int pnv_pci_set_power_state(uint64_t id, uint8_t state, | |
24 | struct opal_msg *msg); | |
25529100 FB |
25 | extern int pnv_pci_set_p2p(struct pci_dev *initiator, struct pci_dev *target, |
26 | u64 desc); | |
7e19bf32 | 27 | |
d6a90bb8 PB |
28 | extern int pnv_pci_enable_tunnel(struct pci_dev *dev, uint64_t *asnind); |
29 | extern int pnv_pci_disable_tunnel(struct pci_dev *dev); | |
30 | extern int pnv_pci_set_tunnel_bar(struct pci_dev *dev, uint64_t addr, | |
31 | int enable); | |
32 | extern int pnv_pci_get_as_notify_info(struct task_struct *task, u32 *lpid, | |
33 | u32 *pid, u32 *tid); | |
1212aa1c | 34 | int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode); |
80c49c7e IM |
35 | int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq, |
36 | unsigned int virq); | |
37 | int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num); | |
38 | void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num); | |
39 | int pnv_cxl_get_irq_count(struct pci_dev *dev); | |
6f963ec2 | 40 | struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev); |
4ee11c1a SW |
41 | int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq); |
42 | bool is_pnv_opal_msi(struct irq_chip *chip); | |
80c49c7e IM |
43 | |
44 | #ifdef CONFIG_CXL_BASE | |
45 | int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
46 | struct pci_dev *dev, int num); | |
47 | void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs, | |
48 | struct pci_dev *dev); | |
49 | #endif | |
50 | ||
89379f16 AD |
51 | struct pnv_php_slot { |
52 | struct hotplug_slot slot; | |
89379f16 AD |
53 | uint64_t id; |
54 | char *name; | |
55 | int slot_no; | |
454593e5 GS |
56 | unsigned int flags; |
57 | #define PNV_PHP_FLAG_BROKEN_PDC 0x1 | |
89379f16 AD |
58 | struct kref kref; |
59 | #define PNV_PHP_STATE_INITIALIZED 0 | |
60 | #define PNV_PHP_STATE_REGISTERED 1 | |
61 | #define PNV_PHP_STATE_POPULATED 2 | |
62 | #define PNV_PHP_STATE_OFFLINE 3 | |
63 | int state; | |
360aebd8 GS |
64 | int irq; |
65 | struct workqueue_struct *wq; | |
89379f16 AD |
66 | struct device_node *dn; |
67 | struct pci_dev *pdev; | |
68 | struct pci_bus *bus; | |
69 | bool power_state_check; | |
a7da2161 | 70 | u8 attention_state; |
89379f16 AD |
71 | void *fdt; |
72 | void *dt; | |
73 | struct of_changeset ocs; | |
74 | struct pnv_php_slot *parent; | |
75 | struct list_head children; | |
76 | struct list_head link; | |
77 | }; | |
78 | extern struct pnv_php_slot *pnv_php_find_slot(struct device_node *dn); | |
79 | extern int pnv_php_set_slot_power_state(struct hotplug_slot *slot, | |
80 | uint8_t state); | |
81 | ||
80c49c7e | 82 | #endif |