[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / include / asm / ppc-opcode.h

/*
 * Copyright 2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * provides masks and opcode images for use by code generation, emulation
 * and for instructions that older assemblers might not know about
 */
#ifndef _ASM_POWERPC_PPC_OPCODE_H
#define _ASM_POWERPC_PPC_OPCODE_H

#include <linux/stringify.h>
#include <asm/asm-compat.h>

#define	__REG_R0	0
#define	__REG_R1	1
#define	__REG_R2	2
#define	__REG_R3	3
#define	__REG_R4	4
#define	__REG_R5	5
#define	__REG_R6	6
#define	__REG_R7	7
#define	__REG_R8	8
#define	__REG_R9	9
#define	__REG_R10	10
#define	__REG_R11	11
#define	__REG_R12	12
#define	__REG_R13	13
#define	__REG_R14	14
#define	__REG_R15	15
#define	__REG_R16	16
#define	__REG_R17	17
#define	__REG_R18	18
#define	__REG_R19	19
#define	__REG_R20	20
#define	__REG_R21	21
#define	__REG_R22	22
#define	__REG_R23	23
#define	__REG_R24	24
#define	__REG_R25	25
#define	__REG_R26	26
#define	__REG_R27	27
#define	__REG_R28	28
#define	__REG_R29	29
#define	__REG_R30	30
#define	__REG_R31	31

#define	__REGA0_0	0
#define	__REGA0_R1	1
#define	__REGA0_R2	2
#define	__REGA0_R3	3
#define	__REGA0_R4	4
#define	__REGA0_R5	5
#define	__REGA0_R6	6
#define	__REGA0_R7	7
#define	__REGA0_R8	8
#define	__REGA0_R9	9
#define	__REGA0_R10	10
#define	__REGA0_R11	11
#define	__REGA0_R12	12
#define	__REGA0_R13	13
#define	__REGA0_R14	14
#define	__REGA0_R15	15
#define	__REGA0_R16	16
#define	__REGA0_R17	17
#define	__REGA0_R18	18
#define	__REGA0_R19	19
#define	__REGA0_R20	20
#define	__REGA0_R21	21
#define	__REGA0_R22	22
#define	__REGA0_R23	23
#define	__REGA0_R24	24
#define	__REGA0_R25	25
#define	__REGA0_R26	26
#define	__REGA0_R27	27
#define	__REGA0_R28	28
#define	__REGA0_R29	29
#define	__REGA0_R30	30
#define	__REGA0_R31	31

/* opcode and xopcode for instructions */
#define OP_TRAP 3
#define OP_TRAP_64 2

#define OP_31_XOP_TRAP      4
#define OP_31_XOP_LWZX      23
#define OP_31_XOP_DCBST     54
#define OP_31_XOP_LWZUX     55
#define OP_31_XOP_TRAP_64   68
#define OP_31_XOP_DCBF      86
#define OP_31_XOP_LBZX      87
#define OP_31_XOP_STWX      151
#define OP_31_XOP_STBX      215
#define OP_31_XOP_LBZUX     119
#define OP_31_XOP_STBUX     247
#define OP_31_XOP_LHZX      279
#define OP_31_XOP_LHZUX     311
#define OP_31_XOP_MFSPR     339
#define OP_31_XOP_LHAX      343
#define OP_31_XOP_LHAUX     375
#define OP_31_XOP_STHX      407
#define OP_31_XOP_STHUX     439
#define OP_31_XOP_MTSPR     467
#define OP_31_XOP_DCBI      470
#define OP_31_XOP_LWBRX     534
#define OP_31_XOP_TLBSYNC   566
#define OP_31_XOP_STWBRX    662
#define OP_31_XOP_LHBRX     790
#define OP_31_XOP_STHBRX    918

#define OP_LWZ  32
#define OP_LD   58
#define OP_LWZU 33
#define OP_LBZ  34
#define OP_LBZU 35
#define OP_STW  36
#define OP_STWU 37
#define OP_STD  62
#define OP_STB  38
#define OP_STBU 39
#define OP_LHZ  40
#define OP_LHZU 41
#define OP_LHA  42
#define OP_LHAU 43
#define OP_STH  44
#define OP_STHU 45

/* sorted alphabetically */
#define PPC_INST_BHRBE			0x7c00025c
#define PPC_INST_CLRBHRB		0x7c00035c
#define PPC_INST_COPY			0x7c00060c
#define PPC_INST_COPY_FIRST		0x7c20060c
#define PPC_INST_CP_ABORT		0x7c00068c
#define PPC_INST_DCBA			0x7c0005ec
#define PPC_INST_DCBA_MASK		0xfc0007fe
#define PPC_INST_DCBAL			0x7c2005ec
#define PPC_INST_DCBZL			0x7c2007ec
#define PPC_INST_ICBT			0x7c00002c
#define PPC_INST_ICSWX			0x7c00032d
#define PPC_INST_ICSWEPX		0x7c00076d
#define PPC_INST_ISEL			0x7c00001e
#define PPC_INST_ISEL_MASK		0xfc00003e
#define PPC_INST_LDARX			0x7c0000a8
#define PPC_INST_STDCX			0x7c0001ad
#define PPC_INST_LSWI			0x7c0004aa
#define PPC_INST_LSWX			0x7c00042a
#define PPC_INST_LWARX			0x7c000028
#define PPC_INST_STWCX			0x7c00012d
#define PPC_INST_LWSYNC			0x7c2004ac
#define PPC_INST_SYNC			0x7c0004ac
#define PPC_INST_SYNC_MASK		0xfc0007fe
#define PPC_INST_ISYNC			0x4c00012c
#define PPC_INST_LXVD2X			0x7c000698
#define PPC_INST_MCRXR			0x7c000400
#define PPC_INST_MCRXR_MASK		0xfc0007fe
#define PPC_INST_MFSPR_PVR		0x7c1f42a6
#define PPC_INST_MFSPR_PVR_MASK		0xfc1ffffe
#define PPC_INST_MFTMR			0x7c0002dc
#define PPC_INST_MSGSND			0x7c00019c
#define PPC_INST_MSGCLR			0x7c0001dc
#define PPC_INST_MSGSYNC		0x7c0006ec
#define PPC_INST_MSGSNDP		0x7c00011c
#define PPC_INST_MTTMR			0x7c0003dc
#define PPC_INST_NOP			0x60000000
#define PPC_INST_PASTE			0x7c00070c
#define PPC_INST_PASTE_LAST		0x7c20070d
#define PPC_INST_POPCNTB		0x7c0000f4
#define PPC_INST_POPCNTB_MASK		0xfc0007fe
#define PPC_INST_POPCNTD		0x7c0003f4
#define PPC_INST_POPCNTW		0x7c0002f4
#define PPC_INST_RFCI			0x4c000066
#define PPC_INST_RFDI			0x4c00004e
#define PPC_INST_RFMCI			0x4c00004c
#define PPC_INST_MFSPR_DSCR		0x7c1102a6
#define PPC_INST_MFSPR_DSCR_MASK	0xfc1ffffe
#define PPC_INST_MTSPR_DSCR		0x7c1103a6
#define PPC_INST_MTSPR_DSCR_MASK	0xfc1ffffe
#define PPC_INST_MFSPR_DSCR_USER	0x7c0302a6
#define PPC_INST_MFSPR_DSCR_USER_MASK	0xfc1ffffe
#define PPC_INST_MTSPR_DSCR_USER	0x7c0303a6
#define PPC_INST_MTSPR_DSCR_USER_MASK	0xfc1ffffe
#define PPC_INST_MFVSRD			0x7c000066
#define PPC_INST_MTVSRD			0x7c000166
#define PPC_INST_SLBFEE			0x7c0007a7
#define PPC_INST_SLBIA			0x7c0003e4

#define PPC_INST_STRING			0x7c00042a
#define PPC_INST_STRING_MASK		0xfc0007fe
#define PPC_INST_STRING_GEN_MASK	0xfc00067e

#define PPC_INST_STSWI			0x7c0005aa
#define PPC_INST_STSWX			0x7c00052a
#define PPC_INST_STXVD2X		0x7c000798
#define PPC_INST_TLBIE			0x7c000264
#define PPC_INST_TLBIEL			0x7c000224
#define PPC_INST_TLBILX			0x7c000024
#define PPC_INST_WAIT			0x7c00007c
#define PPC_INST_TLBIVAX		0x7c000624
#define PPC_INST_TLBSRX_DOT		0x7c0006a5
#define PPC_INST_VPMSUMW		0x10000488
#define PPC_INST_VPMSUMD		0x100004c8
#define PPC_INST_XXLOR			0xf0000510
#define PPC_INST_XXSWAPD		0xf0000250
#define PPC_INST_XVCPSGNDP		0xf0000780
#define PPC_INST_TRECHKPT		0x7c0007dd
#define PPC_INST_TRECLAIM		0x7c00075d
#define PPC_INST_TABORT			0x7c00071d

#define PPC_INST_NAP			0x4c000364
#define PPC_INST_SLEEP			0x4c0003a4
#define PPC_INST_WINKLE			0x4c0003e4

#define PPC_INST_STOP			0x4c0002e4

/* A2 specific instructions */
#define PPC_INST_ERATWE			0x7c0001a6
#define PPC_INST_ERATRE			0x7c000166
#define PPC_INST_ERATILX		0x7c000066
#define PPC_INST_ERATIVAX		0x7c000666
#define PPC_INST_ERATSX			0x7c000126
#define PPC_INST_ERATSX_DOT		0x7c000127

/* Misc instructions for BPF compiler */
#define PPC_INST_LBZ			0x88000000
#define PPC_INST_LD			0xe8000000
#define PPC_INST_LHZ			0xa0000000
#define PPC_INST_LWZ			0x80000000
#define PPC_INST_LHBRX			0x7c00062c
#define PPC_INST_LDBRX			0x7c000428
#define PPC_INST_STB			0x98000000
#define PPC_INST_STH			0xb0000000
#define PPC_INST_STD			0xf8000000
#define PPC_INST_STDU			0xf8000001
#define PPC_INST_STW			0x90000000
#define PPC_INST_STWU			0x94000000
#define PPC_INST_MFLR			0x7c0802a6
#define PPC_INST_MTLR			0x7c0803a6
#define PPC_INST_MTCTR			0x7c0903a6
#define PPC_INST_CMPWI			0x2c000000
#define PPC_INST_CMPDI			0x2c200000
#define PPC_INST_CMPW			0x7c000000
#define PPC_INST_CMPD			0x7c200000
#define PPC_INST_CMPLW			0x7c000040
#define PPC_INST_CMPLD			0x7c200040
#define PPC_INST_CMPLWI			0x28000000
#define PPC_INST_CMPLDI			0x28200000
#define PPC_INST_ADDI			0x38000000
#define PPC_INST_ADDIS			0x3c000000
#define PPC_INST_ADD			0x7c000214
#define PPC_INST_SUB			0x7c000050
#define PPC_INST_BLR			0x4e800020
#define PPC_INST_BLRL			0x4e800021
#define PPC_INST_BCTR			0x4e800420
#define PPC_INST_MULLD			0x7c0001d2
#define PPC_INST_MULLW			0x7c0001d6
#define PPC_INST_MULHWU			0x7c000016
#define PPC_INST_MULLI			0x1c000000
#define PPC_INST_DIVWU			0x7c000396
#define PPC_INST_DIVD			0x7c0003d2
#define PPC_INST_RLWINM			0x54000000
#define PPC_INST_RLWIMI			0x50000000
#define PPC_INST_RLDICL			0x78000000
#define PPC_INST_RLDICR			0x78000004
#define PPC_INST_SLW			0x7c000030
#define PPC_INST_SLD			0x7c000036
#define PPC_INST_SRW			0x7c000430
#define PPC_INST_SRD			0x7c000436
#define PPC_INST_SRAD			0x7c000634
#define PPC_INST_SRADI			0x7c000674
#define PPC_INST_AND			0x7c000038
#define PPC_INST_ANDDOT			0x7c000039
#define PPC_INST_OR			0x7c000378
#define PPC_INST_XOR			0x7c000278
#define PPC_INST_ANDI			0x70000000
#define PPC_INST_ORI			0x60000000
#define PPC_INST_ORIS			0x64000000
#define PPC_INST_XORI			0x68000000
#define PPC_INST_XORIS			0x6c000000
#define PPC_INST_NEG			0x7c0000d0
#define PPC_INST_EXTSW			0x7c0007b4
#define PPC_INST_BRANCH			0x48000000
#define PPC_INST_BRANCH_COND		0x40800000
#define PPC_INST_LBZCIX			0x7c0006aa
#define PPC_INST_STBCIX			0x7c0007aa

/* macros to insert fields into opcodes */
#define ___PPC_RA(a)	(((a) & 0x1f) << 16)
#define ___PPC_RB(b)	(((b) & 0x1f) << 11)
#define ___PPC_RS(s)	(((s) & 0x1f) << 21)
#define ___PPC_RT(t)	___PPC_RS(t)
#define ___PPC_R(r)	(((r) & 0x1) << 16)
#define ___PPC_PRS(prs)	(((prs) & 0x1) << 17)
#define ___PPC_RIC(ric)	(((ric) & 0x3) << 18)
#define __PPC_RA(a)	___PPC_RA(__REG_##a)
#define __PPC_RA0(a)	___PPC_RA(__REGA0_##a)
#define __PPC_RB(b)	___PPC_RB(__REG_##b)
#define __PPC_RS(s)	___PPC_RS(__REG_##s)
#define __PPC_RT(t)	___PPC_RT(__REG_##t)
#define __PPC_XA(a)	((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
#define __PPC_XB(b)	((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
#define __PPC_XS(s)	((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
#define __PPC_XT(s)	__PPC_XS(s)
#define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
#define __PPC_WC(w)	(((w) & 0x3) << 21)
#define __PPC_WS(w)	(((w) & 0x1f) << 11)
#define __PPC_SH(s)	__PPC_WS(s)
#define __PPC_SH64(s)	(__PPC_SH(s) | (((s) & 0x20) >> 4))
#define __PPC_MB(s)	(((s) & 0x1f) << 6)
#define __PPC_ME(s)	(((s) & 0x1f) << 1)
#define __PPC_MB64(s)	(__PPC_MB(s) | ((s) & 0x20))
#define __PPC_ME64(s)	__PPC_MB64(s)
#define __PPC_BI(s)	(((s) & 0x1f) << 16)
#define __PPC_CT(t)	(((t) & 0x0f) << 21)

/*
 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
 * larx with EH set as an illegal instruction.
 */
#ifdef CONFIG_PPC64
#define __PPC_EH(eh)	(((eh) & 0x1) << 0)
#else
#define __PPC_EH(eh)	0
#endif

/* Deal with instructions that older assemblers aren't aware of */
#define	PPC_CP_ABORT		stringify_in_c(.long PPC_INST_CP_ABORT)
#define	PPC_DCBAL(a, b)		stringify_in_c(.long PPC_INST_DCBAL | \
					__PPC_RA(a) | __PPC_RB(b))
#define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_INST_DCBZL | \
					__PPC_RA(a) | __PPC_RB(b))
#define PPC_LDARX(t, a, b, eh)	stringify_in_c(.long PPC_INST_LDARX | \
					___PPC_RT(t) | ___PPC_RA(a) | \
					___PPC_RB(b) | __PPC_EH(eh))
#define PPC_LWARX(t, a, b, eh)	stringify_in_c(.long PPC_INST_LWARX | \
					___PPC_RT(t) | ___PPC_RA(a) | \
					___PPC_RB(b) | __PPC_EH(eh))
#define PPC_MSGSND(b)		stringify_in_c(.long PPC_INST_MSGSND | \
					___PPC_RB(b))
#define PPC_MSGSYNC		stringify_in_c(.long PPC_INST_MSGSYNC)
#define PPC_MSGCLR(b)		stringify_in_c(.long PPC_INST_MSGCLR | \
					___PPC_RB(b))
#define PPC_MSGSNDP(b)		stringify_in_c(.long PPC_INST_MSGSNDP | \
					___PPC_RB(b))
#define PPC_POPCNTB(a, s)	stringify_in_c(.long PPC_INST_POPCNTB | \
					__PPC_RA(a) | __PPC_RS(s))
#define PPC_POPCNTD(a, s)	stringify_in_c(.long PPC_INST_POPCNTD | \
					__PPC_RA(a) | __PPC_RS(s))
#define PPC_POPCNTW(a, s)	stringify_in_c(.long PPC_INST_POPCNTW | \
					__PPC_RA(a) | __PPC_RS(s))
#define PPC_RFCI		stringify_in_c(.long PPC_INST_RFCI)
#define PPC_RFDI		stringify_in_c(.long PPC_INST_RFDI)
#define PPC_RFMCI		stringify_in_c(.long PPC_INST_RFMCI)
#define PPC_TLBILX(t, a, b)	stringify_in_c(.long PPC_INST_TLBILX | \
					__PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBILX_ALL(a, b)	PPC_TLBILX(0, a, b)
#define PPC_TLBILX_PID(a, b)	PPC_TLBILX(1, a, b)
#define PPC_TLBILX_VA(a, b)	PPC_TLBILX(3, a, b)
#define PPC_WAIT(w)		stringify_in_c(.long PPC_INST_WAIT | \
					__PPC_WC(w))
#define PPC_TLBIE(lp,a) 	stringify_in_c(.long PPC_INST_TLBIE | \
					       ___PPC_RB(a) | ___PPC_RS(lp))
#define	PPC_TLBIE_5(rb,rs,ric,prs,r) \
				stringify_in_c(.long PPC_INST_TLBIE | \
					___PPC_RB(rb) | ___PPC_RS(rs) | \
					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
					___PPC_R(r))
#define	PPC_TLBIEL(rb,rs,ric,prs,r) \
				stringify_in_c(.long PPC_INST_TLBIEL | \
					___PPC_RB(rb) | ___PPC_RS(rs) | \
					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
					___PPC_R(r))
#define PPC_TLBSRX_DOT(a,b)	stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
					__PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBIVAX(a,b)	stringify_in_c(.long PPC_INST_TLBIVAX | \
					__PPC_RA0(a) | __PPC_RB(b))

#define PPC_ERATWE(s, a, w)	stringify_in_c(.long PPC_INST_ERATWE | \
					__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
#define PPC_ERATRE(s, a, w)	stringify_in_c(.long PPC_INST_ERATRE | \
					__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
#define PPC_ERATILX(t, a, b)	stringify_in_c(.long PPC_INST_ERATILX | \
					__PPC_T_TLB(t) | __PPC_RA0(a) | \
					__PPC_RB(b))
#define PPC_ERATIVAX(s, a, b)	stringify_in_c(.long PPC_INST_ERATIVAX | \
					__PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_ERATSX(t, a, w)	stringify_in_c(.long PPC_INST_ERATSX | \
					__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_ERATSX_DOT(t, a, w)	stringify_in_c(.long PPC_INST_ERATSX_DOT | \
					__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
#define PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long PPC_INST_SLBFEE | \
					__PPC_RT(t) | __PPC_RB(b))
#define PPC_ICBT(c,a,b)		stringify_in_c(.long PPC_INST_ICBT | \
				       __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
/* PASemi instructions */
#define LBZCIX(t,a,b)		stringify_in_c(.long PPC_INST_LBZCIX | \
				       __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
#define STBCIX(s,a,b)		stringify_in_c(.long PPC_INST_STBCIX | \
				       __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))

/*
 * Define what the VSX XX1 form instructions will look like, then add
 * the 128 bit load store instructions based on that.
 */
#define VSX_XX1(s, a, b)	(__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
#define VSX_XX3(t, a, b)	(__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
#define STXVD2X(s, a, b)	stringify_in_c(.long PPC_INST_STXVD2X | \
					       VSX_XX1((s), a, b))
#define LXVD2X(s, a, b)		stringify_in_c(.long PPC_INST_LXVD2X | \
					       VSX_XX1((s), a, b))
#define MFVRD(a, t)		stringify_in_c(.long PPC_INST_MFVSRD | \
					       VSX_XX1((t)+32, a, R0))
#define MTVRD(t, a)		stringify_in_c(.long PPC_INST_MTVSRD | \
					       VSX_XX1((t)+32, a, R0))
#define VPMSUMW(t, a, b)	stringify_in_c(.long PPC_INST_VPMSUMW | \
					       VSX_XX3((t), a, b))
#define VPMSUMD(t, a, b)	stringify_in_c(.long PPC_INST_VPMSUMD | \
					       VSX_XX3((t), a, b))
#define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
					       VSX_XX3((t), a, b))
#define XXSWAPD(t, a)		stringify_in_c(.long PPC_INST_XXSWAPD | \
					       VSX_XX3((t), a, a))
#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
					       VSX_XX3((t), (a), (b))))

#define PPC_NAP			stringify_in_c(.long PPC_INST_NAP)
#define PPC_SLEEP		stringify_in_c(.long PPC_INST_SLEEP)
#define PPC_WINKLE		stringify_in_c(.long PPC_INST_WINKLE)

#define PPC_STOP		stringify_in_c(.long PPC_INST_STOP)

/* BHRB instructions */
#define PPC_CLRBHRB		stringify_in_c(.long PPC_INST_CLRBHRB)
#define PPC_MFBHRBE(r, n)	stringify_in_c(.long PPC_INST_BHRBE | \
						__PPC_RT(r) | \
							(((n) & 0x3ff) << 11))

/* Transactional memory instructions */
#define TRECHKPT		stringify_in_c(.long PPC_INST_TRECHKPT)
#define TRECLAIM(r)		stringify_in_c(.long PPC_INST_TRECLAIM \
					       | __PPC_RA(r))
#define TABORT(r)		stringify_in_c(.long PPC_INST_TABORT \
					       | __PPC_RA(r))

/* book3e thread control instructions */
#define TMRN(x)			((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
#define MTTMR(tmr, r)		stringify_in_c(.long PPC_INST_MTTMR | \
					       TMRN(tmr) | ___PPC_RS(r))
#define MFTMR(tmr, r)		stringify_in_c(.long PPC_INST_MFTMR | \
					       TMRN(tmr) | ___PPC_RT(r))

/* Coprocessor instructions */
#define PPC_ICSWX(s, a, b)	stringify_in_c(.long PPC_INST_ICSWX |	\
					       ___PPC_RS(s) |		\
					       ___PPC_RA(a) |		\
					       ___PPC_RB(b))
#define PPC_ICSWEPX(s, a, b)	stringify_in_c(.long PPC_INST_ICSWEPX | \
					       ___PPC_RS(s) |		\
					       ___PPC_RA(a) |		\
					       ___PPC_RB(b))

#define PPC_SLBIA(IH)	stringify_in_c(.long PPC_INST_SLBIA | \
				       ((IH & 0x7) << 21))
#define PPC_INVALIDATE_ERAT	PPC_SLBIA(7)

#endif /* _ASM_POWERPC_PPC_OPCODE_H */
Commit	Line	Data
16c57b36	1	/*
8a56e1ee	2	* Copyright 2009 Freescale Semiconductor, Inc.
16c57b36 KG	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version
	7	* 2 of the License, or (at your option) any later version.
	8	*
	9	* provides masks and opcode images for use by code generation, emulation
	10	* and for instructions that older assemblers might not know about
	11	*/
	12	#ifndef _ASM_POWERPC_PPC_OPCODE_H
	13	#define _ASM_POWERPC_PPC_OPCODE_H
	14
	15	#include <linux/stringify.h>
	16	#include <asm/asm-compat.h>
	17
0972def4 MN	18	#define __REG_R0 0
	19	#define __REG_R1 1
	20	#define __REG_R2 2
	21	#define __REG_R3 3
	22	#define __REG_R4 4
	23	#define __REG_R5 5
	24	#define __REG_R6 6
	25	#define __REG_R7 7
	26	#define __REG_R8 8
	27	#define __REG_R9 9
	28	#define __REG_R10 10
	29	#define __REG_R11 11
	30	#define __REG_R12 12
	31	#define __REG_R13 13
	32	#define __REG_R14 14
	33	#define __REG_R15 15
	34	#define __REG_R16 16
	35	#define __REG_R17 17
	36	#define __REG_R18 18
	37	#define __REG_R19 19
	38	#define __REG_R20 20
	39	#define __REG_R21 21
	40	#define __REG_R22 22
	41	#define __REG_R23 23
	42	#define __REG_R24 24
	43	#define __REG_R25 25
	44	#define __REG_R26 26
	45	#define __REG_R27 27
	46	#define __REG_R28 28
	47	#define __REG_R29 29
	48	#define __REG_R30 30
	49	#define __REG_R31 31
	50
f4c01579 MN	51	#define __REGA0_0 0
	52	#define __REGA0_R1 1
	53	#define __REGA0_R2 2
	54	#define __REGA0_R3 3
	55	#define __REGA0_R4 4
	56	#define __REGA0_R5 5
	57	#define __REGA0_R6 6
	58	#define __REGA0_R7 7
	59	#define __REGA0_R8 8
	60	#define __REGA0_R9 9
	61	#define __REGA0_R10 10
	62	#define __REGA0_R11 11
	63	#define __REGA0_R12 12
	64	#define __REGA0_R13 13
	65	#define __REGA0_R14 14
	66	#define __REGA0_R15 15
	67	#define __REGA0_R16 16
	68	#define __REGA0_R17 17
	69	#define __REGA0_R18 18
	70	#define __REGA0_R19 19
	71	#define __REGA0_R20 20
	72	#define __REGA0_R21 21
	73	#define __REGA0_R22 22
	74	#define __REGA0_R23 23
	75	#define __REGA0_R24 24
	76	#define __REGA0_R25 25
	77	#define __REGA0_R26 26
	78	#define __REGA0_R27 27
	79	#define __REGA0_R28 28
	80	#define __REGA0_R29 29
	81	#define __REGA0_R30 30
	82	#define __REGA0_R31 31
	83
9123c5ed HJ	84	/* opcode and xopcode for instructions */
	85	#define OP_TRAP 3
	86	#define OP_TRAP_64 2
	87
	88	#define OP_31_XOP_TRAP 4
	89	#define OP_31_XOP_LWZX 23
	90	#define OP_31_XOP_DCBST 54
	91	#define OP_31_XOP_LWZUX 55
	92	#define OP_31_XOP_TRAP_64 68
	93	#define OP_31_XOP_DCBF 86
	94	#define OP_31_XOP_LBZX 87
	95	#define OP_31_XOP_STWX 151
	96	#define OP_31_XOP_STBX 215
	97	#define OP_31_XOP_LBZUX 119
	98	#define OP_31_XOP_STBUX 247
	99	#define OP_31_XOP_LHZX 279
	100	#define OP_31_XOP_LHZUX 311
	101	#define OP_31_XOP_MFSPR 339
	102	#define OP_31_XOP_LHAX 343
	103	#define OP_31_XOP_LHAUX 375
	104	#define OP_31_XOP_STHX 407
	105	#define OP_31_XOP_STHUX 439
	106	#define OP_31_XOP_MTSPR 467
	107	#define OP_31_XOP_DCBI 470
	108	#define OP_31_XOP_LWBRX 534
	109	#define OP_31_XOP_TLBSYNC 566
	110	#define OP_31_XOP_STWBRX 662
	111	#define OP_31_XOP_LHBRX 790
	112	#define OP_31_XOP_STHBRX 918
	113
	114	#define OP_LWZ 32
	115	#define OP_LD 58
	116	#define OP_LWZU 33
	117	#define OP_LBZ 34
	118	#define OP_LBZU 35
	119	#define OP_STW 36
	120	#define OP_STWU 37
	121	#define OP_STD 62
	122	#define OP_STB 38
	123	#define OP_STBU 39
	124	#define OP_LHZ 40
	125	#define OP_LHZU 41
	126	#define OP_LHA 42
	127	#define OP_LHAU 43
	128	#define OP_STH 44
	129	#define OP_STHU 45
	130
16c57b36	131	/* sorted alphabetically */
95213959 AK	132	#define PPC_INST_BHRBE 0x7c00025c
95213959 AK	133	#define PPC_INST_CLRBHRB 0x7c00035c
ae26b36f CS	134	#define PPC_INST_COPY 0x7c00060c
ae26b36f CS	135	#define PPC_INST_COPY_FIRST 0x7c20060c
8a649045	136	#define PPC_INST_CP_ABORT 0x7c00068c
16c57b36 KG	137	#define PPC_INST_DCBA 0x7c0005ec
	138	#define PPC_INST_DCBA_MASK 0xfc0007fe
	139	#define PPC_INST_DCBAL 0x7c2005ec
	140	#define PPC_INST_DCBZL 0x7c2007ec
1afc149d	141	#define PPC_INST_ICBT 0x7c00002c
edc424f8 DS	142	#define PPC_INST_ICSWX 0x7c00032d
edc424f8 DS	143	#define PPC_INST_ICSWEPX 0x7c00076d
16c57b36 KG	144	#define PPC_INST_ISEL 0x7c00001e
16c57b36 KG	145	#define PPC_INST_ISEL_MASK 0xfc00003e
864b9e6f	146	#define PPC_INST_LDARX 0x7c0000a8
156d0e29	147	#define PPC_INST_STDCX 0x7c0001ad
16c57b36 KG	148	#define PPC_INST_LSWI 0x7c0004aa
16c57b36 KG	149	#define PPC_INST_LSWX 0x7c00042a
d6ccb1f5	150	#define PPC_INST_LWARX 0x7c000028
156d0e29	151	#define PPC_INST_STWCX 0x7c00012d
16c57b36	152	#define PPC_INST_LWSYNC 0x7c2004ac
9863c28a JY	153	#define PPC_INST_SYNC 0x7c0004ac
9863c28a JY	154	#define PPC_INST_SYNC_MASK 0xfc0007fe
ddc6cd0d	155	#define PPC_INST_ISYNC 0x4c00012c
dfb432cb	156	#define PPC_INST_LXVD2X 0x7c000698
16c57b36 KG	157	#define PPC_INST_MCRXR 0x7c000400
	158	#define PPC_INST_MCRXR_MASK 0xfc0007fe
	159	#define PPC_INST_MFSPR_PVR 0x7c1f42a6
178f3582	160	#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
e16c8765	161	#define PPC_INST_MFTMR 0x7c0002dc
16c57b36	162	#define PPC_INST_MSGSND 0x7c00019c
755563bc	163	#define PPC_INST_MSGCLR 0x7c0001dc
cd450c6d	164	#define PPC_INST_MSGSYNC 0x7c0006ec
42d02b81	165	#define PPC_INST_MSGSNDP 0x7c00011c
e16c8765	166	#define PPC_INST_MTTMR 0x7c0003dc
16c57b36	167	#define PPC_INST_NOP 0x60000000
ae26b36f CS	168	#define PPC_INST_PASTE 0x7c00070c
ae26b36f CS	169	#define PPC_INST_PASTE_LAST 0x7c20070d
16c57b36 KG	170	#define PPC_INST_POPCNTB 0x7c0000f4
16c57b36 KG	171	#define PPC_INST_POPCNTB_MASK 0xfc0007fe
b5f9b666 AB	172	#define PPC_INST_POPCNTD 0x7c0003f4
b5f9b666 AB	173	#define PPC_INST_POPCNTW 0x7c0002f4
16c57b36 KG	174	#define PPC_INST_RFCI 0x4c000066
	175	#define PPC_INST_RFDI 0x4c00004e
	176	#define PPC_INST_RFMCI 0x4c00004c
efcac658	177	#define PPC_INST_MFSPR_DSCR 0x7c1102a6
178f3582	178	#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
efcac658	179	#define PPC_INST_MTSPR_DSCR 0x7c1103a6
178f3582	180	#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
73d2fb75	181	#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
178f3582	182	#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
73d2fb75	183	#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
178f3582	184	#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
6dd7a82c AB	185	#define PPC_INST_MFVSRD 0x7c000066
6dd7a82c AB	186	#define PPC_INST_MTVSRD 0x7c000166
697d3899	187	#define PPC_INST_SLBFEE 0x7c0007a7
09cf5bcb	188	#define PPC_INST_SLBIA 0x7c0003e4
16c57b36 KG	189
	190	#define PPC_INST_STRING 0x7c00042a
	191	#define PPC_INST_STRING_MASK 0xfc0007fe
	192	#define PPC_INST_STRING_GEN_MASK 0xfc00067e
	193
	194	#define PPC_INST_STSWI 0x7c0005aa
	195	#define PPC_INST_STSWX 0x7c00052a
dfb432cb	196	#define PPC_INST_STXVD2X 0x7c000798
60dbf438	197	#define PPC_INST_TLBIE 0x7c000264
8cd6d3c2	198	#define PPC_INST_TLBIEL 0x7c000224
7281f5dc	199	#define PPC_INST_TLBILX 0x7c000024
16c57b36	200	#define PPC_INST_WAIT 0x7c00007c
29c09e8f BH	201	#define PPC_INST_TLBIVAX 0x7c000624
29c09e8f BH	202	#define PPC_INST_TLBSRX_DOT 0x7c0006a5
6dd7a82c AB	203	#define PPC_INST_VPMSUMW 0x10000488
6dd7a82c AB	204	#define PPC_INST_VPMSUMD 0x100004c8
0016a4cf	205	#define PPC_INST_XXLOR 0xf0000510
926f160f	206	#define PPC_INST_XXSWAPD 0xf0000250
b92a66a6	207	#define PPC_INST_XVCPSGNDP 0xf0000780
14c39a4c MN	208	#define PPC_INST_TRECHKPT 0x7c0007dd
	209	#define PPC_INST_TRECLAIM 0x7c00075d
	210	#define PPC_INST_TABORT 0x7c00071d
16c57b36	211
948cf67c BH	212	#define PPC_INST_NAP 0x4c000364
948cf67c BH	213	#define PPC_INST_SLEEP 0x4c0003a4
77b54e9f	214	#define PPC_INST_WINKLE 0x4c0003e4
948cf67c	215
bcef83a0 SP	216	#define PPC_INST_STOP 0x4c0002e4
bcef83a0 SP	217
931e1241 BH	218	/* A2 specific instructions */
	219	#define PPC_INST_ERATWE 0x7c0001a6
	220	#define PPC_INST_ERATRE 0x7c000166
	221	#define PPC_INST_ERATILX 0x7c000066
	222	#define PPC_INST_ERATIVAX 0x7c000666
	223	#define PPC_INST_ERATSX 0x7c000126
	224	#define PPC_INST_ERATSX_DOT 0x7c000127
	225
0ca87f05	226	/* Misc instructions for BPF compiler */
4e235761	227	#define PPC_INST_LBZ 0x88000000
0ca87f05 ME	228	#define PPC_INST_LD 0xe8000000
	229	#define PPC_INST_LHZ 0xa0000000
	230	#define PPC_INST_LWZ 0x80000000
156d0e29 NR	231	#define PPC_INST_LHBRX 0x7c00062c
	232	#define PPC_INST_LDBRX 0x7c000428
	233	#define PPC_INST_STB 0x98000000
	234	#define PPC_INST_STH 0xb0000000
0ca87f05 ME	235	#define PPC_INST_STD 0xf8000000
0ca87f05 ME	236	#define PPC_INST_STDU 0xf8000001
693930d6 DK	237	#define PPC_INST_STW 0x90000000
693930d6 DK	238	#define PPC_INST_STWU 0x94000000
0ca87f05 ME	239	#define PPC_INST_MFLR 0x7c0802a6
0ca87f05 ME	240	#define PPC_INST_MTLR 0x7c0803a6
ce076141	241	#define PPC_INST_MTCTR 0x7c0903a6
0ca87f05 ME	242	#define PPC_INST_CMPWI 0x2c000000
0ca87f05 ME	243	#define PPC_INST_CMPDI 0x2c200000
156d0e29 NR	244	#define PPC_INST_CMPW 0x7c000000
156d0e29 NR	245	#define PPC_INST_CMPD 0x7c200000
0ca87f05	246	#define PPC_INST_CMPLW 0x7c000040
156d0e29	247	#define PPC_INST_CMPLD 0x7c200040
0ca87f05	248	#define PPC_INST_CMPLWI 0x28000000
156d0e29	249	#define PPC_INST_CMPLDI 0x28200000
0ca87f05 ME	250	#define PPC_INST_ADDI 0x38000000
	251	#define PPC_INST_ADDIS 0x3c000000
	252	#define PPC_INST_ADD 0x7c000214
	253	#define PPC_INST_SUB 0x7c000050
	254	#define PPC_INST_BLR 0x4e800020
	255	#define PPC_INST_BLRL 0x4e800021
ce076141	256	#define PPC_INST_BCTR 0x4e800420
156d0e29	257	#define PPC_INST_MULLD 0x7c0001d2
0ca87f05 ME	258	#define PPC_INST_MULLW 0x7c0001d6
	259	#define PPC_INST_MULHWU 0x7c000016
	260	#define PPC_INST_MULLI 0x1c000000
a40a2b67	261	#define PPC_INST_DIVWU 0x7c000396
156d0e29	262	#define PPC_INST_DIVD 0x7c0003d2
0ca87f05	263	#define PPC_INST_RLWINM 0x54000000
156d0e29 NR	264	#define PPC_INST_RLWIMI 0x50000000
156d0e29 NR	265	#define PPC_INST_RLDICL 0x78000000
0ca87f05 ME	266	#define PPC_INST_RLDICR 0x78000004
0ca87f05 ME	267	#define PPC_INST_SLW 0x7c000030
156d0e29	268	#define PPC_INST_SLD 0x7c000036
0ca87f05	269	#define PPC_INST_SRW 0x7c000430
156d0e29 NR	270	#define PPC_INST_SRD 0x7c000436
	271	#define PPC_INST_SRAD 0x7c000634
	272	#define PPC_INST_SRADI 0x7c000674
0ca87f05 ME	273	#define PPC_INST_AND 0x7c000038
	274	#define PPC_INST_ANDDOT 0x7c000039
	275	#define PPC_INST_OR 0x7c000378
02871903	276	#define PPC_INST_XOR 0x7c000278
0ca87f05 ME	277	#define PPC_INST_ANDI 0x70000000
	278	#define PPC_INST_ORI 0x60000000
	279	#define PPC_INST_ORIS 0x64000000
02871903 DB	280	#define PPC_INST_XORI 0x68000000
02871903 DB	281	#define PPC_INST_XORIS 0x6c000000
0ca87f05	282	#define PPC_INST_NEG 0x7c0000d0
156d0e29	283	#define PPC_INST_EXTSW 0x7c0007b4
0ca87f05 ME	284	#define PPC_INST_BRANCH 0x48000000
0ca87f05 ME	285	#define PPC_INST_BRANCH_COND 0x40800000
4404a9f9 MN	286	#define PPC_INST_LBZCIX 0x7c0006aa
4404a9f9 MN	287	#define PPC_INST_STBCIX 0x7c0007aa
0ca87f05	288
16c57b36	289	/* macros to insert fields into opcodes */
55a5db18 MN	290	#define ___PPC_RA(a) (((a) & 0x1f) << 16)
	291	#define ___PPC_RB(b) (((b) & 0x1f) << 11)
	292	#define ___PPC_RS(s) (((s) & 0x1f) << 21)
	293	#define ___PPC_RT(t) ___PPC_RS(t)
8cd6d3c2 BS	294	#define ___PPC_R(r) (((r) & 0x1) << 16)
	295	#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
	296	#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
0b7673c3	297	#define __PPC_RA(a) ___PPC_RA(__REG_##a)
f4c01579	298	#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
0b7673c3 MN	299	#define __PPC_RB(b) ___PPC_RB(__REG_##b)
	300	#define __PPC_RS(s) ___PPC_RS(__REG_##s)
	301	#define __PPC_RT(t) ___PPC_RT(__REG_##t)
0016a4cf PM	302	#define __PPC_XA(a) ((((a) & 0x1f) << 16) \| (((a) & 0x20) >> 3))
0016a4cf PM	303	#define __PPC_XB(b) ((((b) & 0x1f) << 11) \| (((b) & 0x20) >> 4))
dfb432cb	304	#define __PPC_XS(s) ((((s) & 0x1f) << 21) \| (((s) & 0x20) >> 5))
0016a4cf	305	#define __PPC_XT(s) __PPC_XS(s)
da6b43c8 MN	306	#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
da6b43c8 MN	307	#define __PPC_WC(w) (((w) & 0x3) << 21)
931e1241	308	#define __PPC_WS(w) (((w) & 0x1f) << 11)
0ca87f05	309	#define __PPC_SH(s) __PPC_WS(s)
f0cd8240	310	#define __PPC_SH64(s) (__PPC_SH(s) \| (((s) & 0x20) >> 4))
0ca87f05 ME	311	#define __PPC_MB(s) (((s) & 0x1f) << 6)
0ca87f05 ME	312	#define __PPC_ME(s) (((s) & 0x1f) << 1)
277285b8 NR	313	#define __PPC_MB64(s) (__PPC_MB(s) \| ((s) & 0x20))
277285b8 NR	314	#define __PPC_ME64(s) __PPC_MB64(s)
0ca87f05	315	#define __PPC_BI(s) (((s) & 0x1f) << 16)
1afc149d	316	#define __PPC_CT(t) (((t) & 0x0f) << 21)
931e1241	317
4e14a4d1	318	/*
d6ccb1f5 KG	319	* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
d6ccb1f5 KG	320	* larx with EH set as an illegal instruction.
4e14a4d1 AB	321	*/
	322	#ifdef CONFIG_PPC64
	323	#define __PPC_EH(eh) (((eh) & 0x1) << 0)
	324	#else
	325	#define __PPC_EH(eh) 0
	326	#endif
16c57b36 KG	327
16c57b36 KG	328	/* Deal with instructions that older assemblers aren't aware of */
8a649045	329	#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
16c57b36 KG	330	#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL \| \
	331	__PPC_RA(a) \| __PPC_RB(b))
	332	#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL \| \
	333	__PPC_RA(a) \| __PPC_RB(b))
864b9e6f	334	#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX \| \
cdaade71 MN	335	___PPC_RT(t) \| ___PPC_RA(a) \| \
cdaade71 MN	336	___PPC_RB(b) \| __PPC_EH(eh))
4e14a4d1	337	#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX \| \
cdaade71 MN	338	___PPC_RT(t) \| ___PPC_RA(a) \| \
cdaade71 MN	339	___PPC_RB(b) \| __PPC_EH(eh))
16c57b36	340	#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND \| \
cdaade71	341	___PPC_RB(b))
cd450c6d	342	#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC)
755563bc PM	343	#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR \| \
755563bc PM	344	___PPC_RB(b))
42d02b81 IM	345	#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP \| \
42d02b81 IM	346	___PPC_RB(b))
b5f9b666 AB	347	#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB \| \
	348	__PPC_RA(a) \| __PPC_RS(s))
	349	#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD \| \
	350	__PPC_RA(a) \| __PPC_RS(s))
	351	#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW \| \
	352	__PPC_RA(a) \| __PPC_RS(s))
16c57b36 KG	353	#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
	354	#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
	355	#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
	356	#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX \| \
962cffbd	357	__PPC_T_TLB(t) \| __PPC_RA0(a) \| __PPC_RB(b))
16c57b36 KG	358	#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
	359	#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
	360	#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
	361	#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT \| \
	362	__PPC_WC(w))
60dbf438	363	#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE \| \
cdaade71	364	___PPC_RB(a) \| ___PPC_RS(lp))
8cd6d3c2 BS	365	#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
	366	stringify_in_c(.long PPC_INST_TLBIE \| \
	367	___PPC_RB(rb) \| ___PPC_RS(rs) \| \
	368	___PPC_RIC(ric) \| ___PPC_PRS(prs) \| \
	369	___PPC_R(r))
	370	#define PPC_TLBIEL(rb,rs,ric,prs,r) \
	371	stringify_in_c(.long PPC_INST_TLBIEL \| \
	372	___PPC_RB(rb) \| ___PPC_RS(rs) \| \
	373	___PPC_RIC(ric) \| ___PPC_PRS(prs) \| \
	374	___PPC_R(r))
29c09e8f	375	#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT \| \
962cffbd	376	__PPC_RA0(a) \| __PPC_RB(b))
29c09e8f	377	#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX \| \
962cffbd	378	__PPC_RA0(a) \| __PPC_RB(b))
16c57b36	379
931e1241 BH	380	#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE \| \
	381	__PPC_RS(s) \| __PPC_RA(a) \| __PPC_WS(w))
	382	#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE \| \
	383	__PPC_RS(s) \| __PPC_RA(a) \| __PPC_WS(w))
	384	#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX \| \
962cffbd	385	__PPC_T_TLB(t) \| __PPC_RA0(a) \| \
931e1241 BH	386	__PPC_RB(b))
931e1241 BH	387	#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX \| \
962cffbd	388	__PPC_RS(s) \| __PPC_RA0(a) \| __PPC_RB(b))
931e1241	389	#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX \| \
962cffbd	390	__PPC_RS(t) \| __PPC_RA0(a) \| __PPC_RB(b))
931e1241	391	#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT \| \
962cffbd	392	__PPC_RS(t) \| __PPC_RA0(a) \| __PPC_RB(b))
697d3899 PM	393	#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE \| \
697d3899 PM	394	__PPC_RT(t) \| __PPC_RB(b))
1afc149d TB	395	#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT \| \
1afc149d TB	396	__PPC_CT(c) \| __PPC_RA0(a) \| __PPC_RB(b))
4404a9f9 MN	397	/* PASemi instructions */
	398	#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX \| \
	399	__PPC_RT(t) \| __PPC_RA(a) \| __PPC_RB(b))
	400	#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX \| \
	401	__PPC_RS(s) \| __PPC_RA(a) \| __PPC_RB(b))
931e1241	402
dfb432cb MN	403	/*
	404	* Define what the VSX XX1 form instructions will look like, then add
	405	* the 128 bit load store instructions based on that.
	406	*/
	407	#define VSX_XX1(s, a, b) (__PPC_XS(s) \| __PPC_RA(a) \| __PPC_RB(b))
0016a4cf	408	#define VSX_XX3(t, a, b) (__PPC_XT(t) \| __PPC_XA(a) \| __PPC_XB(b))
dfb432cb	409	#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X \| \
178f2ae0	410	VSX_XX1((s), a, b))
dfb432cb	411	#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X \| \
178f2ae0	412	VSX_XX1((s), a, b))
6dd7a82c AB	413	#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD \| \
	414	VSX_XX1((t)+32, a, R0))
	415	#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD \| \
	416	VSX_XX1((t)+32, a, R0))
	417	#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW \| \
	418	VSX_XX3((t), a, b))
	419	#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD \| \
	420	VSX_XX3((t), a, b))
0016a4cf	421	#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR \| \
178f2ae0	422	VSX_XX3((t), a, b))
926f160f AB	423	#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD \| \
926f160f AB	424	VSX_XX3((t), a, a))
b92a66a6 MN	425	#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP \| \
b92a66a6 MN	426	VSX_XX3((t), (a), (b))))
dfb432cb	427
948cf67c BH	428	#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
948cf67c BH	429	#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
77b54e9f	430	#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
948cf67c	431
bcef83a0 SP	432	#define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
bcef83a0 SP	433
95213959 AK	434	/* BHRB instructions */
	435	#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
	436	#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE \| \
	437	__PPC_RT(r) \| \
	438	(((n) & 0x3ff) << 11))
	439
14c39a4c MN	440	/* Transactional memory instructions */
	441	#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
	442	#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
	443	\| __PPC_RA(r))
	444	#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
	445	\| __PPC_RA(r))
	446
e16c8765 AF	447	/* book3e thread control instructions */
	448	#define TMRN(x) ((((x) & 0x1f) << 16) \| (((x) & 0x3e0) << 6))
	449	#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR \| \
	450	TMRN(tmr) \| ___PPC_RS(r))
	451	#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR \| \
	452	TMRN(tmr) \| ___PPC_RT(r))
	453
edc424f8 DS	454	/* Coprocessor instructions */
	455	#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX \| \
	456	___PPC_RS(s) \| \
	457	___PPC_RA(a) \| \
	458	___PPC_RB(b))
	459	#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX \| \
	460	___PPC_RS(s) \| \
	461	___PPC_RA(a) \| \
	462	___PPC_RB(b))
	463
09cf5bcb AK	464	#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA \| \
09cf5bcb AK	465	((IH & 0x7) << 21))
96ed1fe5	466	#define PPC_INVALIDATE_ERAT PPC_SLBIA(7)
edc424f8	467
16c57b36	468	#endif /* _ASM_POWERPC_PPC_OPCODE_H */