[mirror_ubuntu-artful-kernel.git] / arch / powerpc / include / asm / qe_ic.h

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Authors: 	Shlomi Gridish <gridish@freescale.com>
 * 		Li Yang <leoli@freescale.com>
 *
 * Description:
 * QE IC external definitions and structure.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#ifndef _ASM_POWERPC_QE_IC_H
#define _ASM_POWERPC_QE_IC_H

#include <linux/irq.h>

struct device_node;
struct qe_ic;

#define NUM_OF_QE_IC_GROUPS	6

/* Flags when we init the QE IC */
#define QE_IC_SPREADMODE_GRP_W			0x00000001
#define QE_IC_SPREADMODE_GRP_X			0x00000002
#define QE_IC_SPREADMODE_GRP_Y			0x00000004
#define QE_IC_SPREADMODE_GRP_Z			0x00000008
#define QE_IC_SPREADMODE_GRP_RISCA		0x00000010
#define QE_IC_SPREADMODE_GRP_RISCB		0x00000020

#define QE_IC_LOW_SIGNAL			0x00000100
#define QE_IC_HIGH_SIGNAL			0x00000200

#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH	0x00001000
#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH	0x00002000
#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH	0x00004000
#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH	0x00008000
#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH	0x00010000
#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH	0x00020000
#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH	0x00040000
#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH	0x00080000
#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH	0x00100000
#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH	0x00200000
#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH	0x00400000
#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH	0x00800000
#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT		(12)

/* QE interrupt sources groups */
enum qe_ic_grp_id {
	QE_IC_GRP_W = 0,	/* QE interrupt controller group W */
	QE_IC_GRP_X,		/* QE interrupt controller group X */
	QE_IC_GRP_Y,		/* QE interrupt controller group Y */
	QE_IC_GRP_Z,		/* QE interrupt controller group Z */
	QE_IC_GRP_RISCA,	/* QE interrupt controller RISC group A */
	QE_IC_GRP_RISCB		/* QE interrupt controller RISC group B */
};

#ifdef CONFIG_QUICC_ENGINE
void qe_ic_init(struct device_node *node, unsigned int flags,
		void (*low_handler)(struct irq_desc *desc),
		void (*high_handler)(struct irq_desc *desc));
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
#else
static inline void qe_ic_init(struct device_node *node, unsigned int flags,
		void (*low_handler)(struct irq_desc *desc),
		void (*high_handler)(struct irq_desc *desc))
{}
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{ return 0; }
static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{ return 0; }
#endif /* CONFIG_QUICC_ENGINE */

void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);

static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
{
	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
}

static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
{
	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);
}

static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
{
	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	chip->irq_eoi(&desc->irq_data);
}

static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
{
	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	chip->irq_eoi(&desc->irq_data);
}

static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
{
	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
	unsigned int cascade_irq;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	cascade_irq = qe_ic_get_high_irq(qe_ic);
	if (cascade_irq == NO_IRQ)
		cascade_irq = qe_ic_get_low_irq(qe_ic);

	if (cascade_irq != NO_IRQ)
		generic_handle_irq(cascade_irq);

	chip->irq_eoi(&desc->irq_data);
}

#endif /* _ASM_POWERPC_QE_IC_H */
Commit	Line	Data
98658538	1	/*
8a56e1ee	2	* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
98658538 LY	3	*
	4	* Authors: Shlomi Gridish <gridish@freescale.com>
	5	* Li Yang <leoli@freescale.com>
	6	*
	7	* Description:
	8	* QE IC external definitions and structure.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15	#ifndef _ASM_POWERPC_QE_IC_H
	16	#define _ASM_POWERPC_QE_IC_H
	17
	18	#include <linux/irq.h>
	19
be11d3b3 AV	20	struct device_node;
	21	struct qe_ic;
	22
98658538 LY	23	#define NUM_OF_QE_IC_GROUPS 6
	24
	25	/* Flags when we init the QE IC */
	26	#define QE_IC_SPREADMODE_GRP_W 0x00000001
	27	#define QE_IC_SPREADMODE_GRP_X 0x00000002
	28	#define QE_IC_SPREADMODE_GRP_Y 0x00000004
	29	#define QE_IC_SPREADMODE_GRP_Z 0x00000008
	30	#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
	31	#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
	32
	33	#define QE_IC_LOW_SIGNAL 0x00000100
	34	#define QE_IC_HIGH_SIGNAL 0x00000200
	35
	36	#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
	37	#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
	38	#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
	39	#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
	40	#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
	41	#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
	42	#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
	43	#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
	44	#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
	45	#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
	46	#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
	47	#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
	48	#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
	49
	50	/* QE interrupt sources groups */
	51	enum qe_ic_grp_id {
	52	QE_IC_GRP_W = 0, /* QE interrupt controller group W */
	53	QE_IC_GRP_X, /* QE interrupt controller group X */
	54	QE_IC_GRP_Y, /* QE interrupt controller group Y */
	55	QE_IC_GRP_Z, /* QE interrupt controller group Z */
	56	QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
	57	QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
	58	};
	59
be11d3b3	60	#ifdef CONFIG_QUICC_ENGINE
cccd2102	61	void qe_ic_init(struct device_node *node, unsigned int flags,
bd0b9ac4 TG	62	void (low_handler)(struct irq_desc desc),
bd0b9ac4 TG	63	void (high_handler)(struct irq_desc desc));
be11d3b3 AV	64	unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
	65	unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
	66	#else
	67	static inline void qe_ic_init(struct device_node *node, unsigned int flags,
bd0b9ac4 TG	68	void (low_handler)(struct irq_desc desc),
bd0b9ac4 TG	69	void (high_handler)(struct irq_desc desc))
be11d3b3 AV	70	{}
	71	static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
	72	{ return 0; }
	73	static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
	74	{ return 0; }
	75	#endif /* CONFIG_QUICC_ENGINE */
	76
98658538 LY	77	void qe_ic_set_highest_priority(unsigned int virq, int high);
	78	int qe_ic_set_priority(unsigned int virq, unsigned int priority);
	79	int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
	80
bd0b9ac4	81	static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
cccd2102	82	{
eead4d5c	83	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
cccd2102 AV	84	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
	85
	86	if (cascade_irq != NO_IRQ)
	87	generic_handle_irq(cascade_irq);
	88	}
	89
bd0b9ac4	90	static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
cccd2102	91	{
eead4d5c	92	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
cccd2102 AV	93	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
	94
	95	if (cascade_irq != NO_IRQ)
	96	generic_handle_irq(cascade_irq);
	97	}
	98
bd0b9ac4	99	static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
cccd2102	100	{
eead4d5c	101	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
cccd2102	102	unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
eead4d5c	103	struct irq_chip *chip = irq_desc_get_chip(desc);
cccd2102 AV	104
	105	if (cascade_irq != NO_IRQ)
	106	generic_handle_irq(cascade_irq);
	107
3a0adfab	108	chip->irq_eoi(&desc->irq_data);
cccd2102 AV	109	}
cccd2102 AV	110
bd0b9ac4	111	static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
cccd2102	112	{
eead4d5c	113	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
cccd2102	114	unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
eead4d5c	115	struct irq_chip *chip = irq_desc_get_chip(desc);
cccd2102 AV	116
	117	if (cascade_irq != NO_IRQ)
	118	generic_handle_irq(cascade_irq);
	119
3a0adfab	120	chip->irq_eoi(&desc->irq_data);
cccd2102 AV	121	}
cccd2102 AV	122
bd0b9ac4	123	static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
cccd2102	124	{
eead4d5c	125	struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
cccd2102	126	unsigned int cascade_irq;
eead4d5c	127	struct irq_chip *chip = irq_desc_get_chip(desc);
cccd2102 AV	128
	129	cascade_irq = qe_ic_get_high_irq(qe_ic);
	130	if (cascade_irq == NO_IRQ)
	131	cascade_irq = qe_ic_get_low_irq(qe_ic);
	132
	133	if (cascade_irq != NO_IRQ)
	134	generic_handle_irq(cascade_irq);
	135
3a0adfab	136	chip->irq_eoi(&desc->irq_data);
cccd2102 AV	137	}
cccd2102 AV	138
98658538	139	#endif /* _ASM_POWERPC_QE_IC_H */