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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * Contains the definition of registers common to all PowerPC variants. | |
3 | * If a register definition has been changed in a different PowerPC | |
4 | * variant, we will case it in #ifndef XXX ... #endif, and have the | |
5 | * number used in the Programming Environments Manual For 32-Bit | |
6 | * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. | |
7 | */ | |
8 | ||
9f04b9e3 PM |
9 | #ifndef _ASM_POWERPC_REG_H |
10 | #define _ASM_POWERPC_REG_H | |
14cf11af | 11 | #ifdef __KERNEL__ |
14cf11af PM |
12 | |
13 | #include <linux/stringify.h> | |
9f04b9e3 | 14 | #include <asm/cputable.h> |
14cf11af PM |
15 | |
16 | /* Pickup Book E specific registers. */ | |
17 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) | |
18 | #include <asm/reg_booke.h> | |
26ef5c09 DG |
19 | #endif /* CONFIG_BOOKE || CONFIG_40x */ |
20 | ||
39aef685 AF |
21 | #ifdef CONFIG_FSL_EMB_PERFMON |
22 | #include <asm/reg_fsl_emb.h> | |
23 | #endif | |
24 | ||
26ef5c09 DG |
25 | #ifdef CONFIG_8xx |
26 | #include <asm/reg_8xx.h> | |
27 | #endif /* CONFIG_8xx */ | |
14cf11af | 28 | |
9f04b9e3 PM |
29 | #define MSR_SF_LG 63 /* Enable 64 bit mode */ |
30 | #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ | |
31 | #define MSR_HV_LG 60 /* Hypervisor state */ | |
97a0aac9 MN |
32 | #define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ |
33 | #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ | |
34 | #define MSR_TS_LG 33 /* Trans Mem state (2 bits) */ | |
35 | #define MSR_TM_LG 32 /* Trans Mem Available */ | |
9f04b9e3 | 36 | #define MSR_VEC_LG 25 /* Enable AltiVec */ |
ce48b210 | 37 | #define MSR_VSX_LG 23 /* Enable VSX */ |
9f04b9e3 PM |
38 | #define MSR_POW_LG 18 /* Enable Power Management */ |
39 | #define MSR_WE_LG 18 /* Wait State Enable */ | |
40 | #define MSR_TGPR_LG 17 /* TLB Update registers in use */ | |
41 | #define MSR_CE_LG 17 /* Critical Interrupt Enable */ | |
42 | #define MSR_ILE_LG 16 /* Interrupt Little Endian */ | |
43 | #define MSR_EE_LG 15 /* External Interrupt Enable */ | |
44 | #define MSR_PR_LG 14 /* Problem State / Privilege Level */ | |
45 | #define MSR_FP_LG 13 /* Floating Point enable */ | |
46 | #define MSR_ME_LG 12 /* Machine Check Enable */ | |
47 | #define MSR_FE0_LG 11 /* Floating Exception mode 0 */ | |
48 | #define MSR_SE_LG 10 /* Single Step */ | |
49 | #define MSR_BE_LG 9 /* Branch Trace */ | |
50 | #define MSR_DE_LG 9 /* Debug Exception Enable */ | |
51 | #define MSR_FE1_LG 8 /* Floating Exception mode 1 */ | |
52 | #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ | |
53 | #define MSR_IR_LG 5 /* Instruction Relocate */ | |
54 | #define MSR_DR_LG 4 /* Data Relocate */ | |
55 | #define MSR_PE_LG 3 /* Protection Enable */ | |
56 | #define MSR_PX_LG 2 /* Protection Exclusive Mode */ | |
57 | #define MSR_PMM_LG 2 /* Performance monitor */ | |
58 | #define MSR_RI_LG 1 /* Recoverable Exception */ | |
59 | #define MSR_LE_LG 0 /* Little Endian */ | |
14cf11af | 60 | |
9f04b9e3 PM |
61 | #ifdef __ASSEMBLY__ |
62 | #define __MASK(X) (1<<(X)) | |
63 | #else | |
64 | #define __MASK(X) (1UL<<(X)) | |
65 | #endif | |
66 | ||
c032524f | 67 | #ifdef CONFIG_PPC64 |
9f04b9e3 PM |
68 | #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ |
69 | #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ | |
70 | #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ | |
c032524f PM |
71 | #else |
72 | /* so tests for these bits fail on 32-bit */ | |
73 | #define MSR_SF 0 | |
74 | #define MSR_ISF 0 | |
75 | #define MSR_HV 0 | |
76 | #endif | |
77 | ||
de2a20aa CB |
78 | /* |
79 | * To be used in shared book E/book S, this avoids needing to worry about | |
80 | * book S/book E in shared code | |
81 | */ | |
82 | #ifndef MSR_SPE | |
83 | #define MSR_SPE 0 | |
84 | #endif | |
85 | ||
9f04b9e3 | 86 | #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ |
ce48b210 | 87 | #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ |
9f04b9e3 PM |
88 | #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ |
89 | #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ | |
90 | #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ | |
91 | #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ | |
92 | #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ | |
93 | #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ | |
94 | #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ | |
95 | #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ | |
96 | #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ | |
97 | #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ | |
98 | #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ | |
99 | #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ | |
100 | #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ | |
101 | #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ | |
102 | #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ | |
103 | #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ | |
104 | #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ | |
105 | #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ | |
106 | #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ | |
fd582ec8 | 107 | #ifndef MSR_PMM |
9f04b9e3 | 108 | #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ |
fd582ec8 | 109 | #endif |
9f04b9e3 PM |
110 | #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ |
111 | #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ | |
112 | ||
97a0aac9 MN |
113 | #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ |
114 | #define MSR_TS_N 0 /* Non-transactional */ | |
115 | #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */ | |
116 | #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */ | |
117 | #define MSR_TS_MASK (MSR_TS_T | MSR_TS_S) /* Transaction State bits */ | |
118 | #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */ | |
d2b9d2a5 | 119 | #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */ |
97a0aac9 MN |
120 | #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T) |
121 | #define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S) | |
122 | ||
0257c99c | 123 | #if defined(CONFIG_PPC_BOOK3S_64) |
9d4a2925 ME |
124 | #define MSR_64BIT MSR_SF |
125 | ||
0257c99c | 126 | /* Server variant */ |
ef1967ff AB |
127 | #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV) |
128 | #ifdef __BIG_ENDIAN__ | |
129 | #define MSR_ __MSR | |
8117ac6a | 130 | #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV) |
ef1967ff AB |
131 | #else |
132 | #define MSR_ (__MSR | MSR_LE) | |
8117ac6a | 133 | #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV | MSR_LE) |
ef1967ff | 134 | #endif |
594bd383 AB |
135 | #define MSR_KERNEL (MSR_ | MSR_64BIT) |
136 | #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE) | |
137 | #define MSR_USER64 (MSR_USER32 | MSR_64BIT) | |
0257c99c | 138 | #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) |
14cf11af | 139 | /* Default MSR for kernel mode. */ |
14cf11af | 140 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) |
14cf11af | 141 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) |
9f04b9e3 | 142 | #endif |
14cf11af | 143 | |
9d4a2925 ME |
144 | #ifndef MSR_64BIT |
145 | #define MSR_64BIT 0 | |
146 | #endif | |
147 | ||
14cf11af PM |
148 | /* Floating Point Status and Control Register (FPSCR) Fields */ |
149 | #define FPSCR_FX 0x80000000 /* FPU exception summary */ | |
150 | #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ | |
151 | #define FPSCR_VX 0x20000000 /* Invalid operation summary */ | |
152 | #define FPSCR_OX 0x10000000 /* Overflow exception summary */ | |
153 | #define FPSCR_UX 0x08000000 /* Underflow exception summary */ | |
154 | #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ | |
155 | #define FPSCR_XX 0x02000000 /* Inexact exception summary */ | |
156 | #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ | |
157 | #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ | |
158 | #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ | |
159 | #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ | |
160 | #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ | |
161 | #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ | |
162 | #define FPSCR_FR 0x00040000 /* Fraction rounded */ | |
163 | #define FPSCR_FI 0x00020000 /* Fraction inexact */ | |
164 | #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ | |
165 | #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ | |
166 | #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ | |
167 | #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ | |
168 | #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ | |
169 | #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ | |
170 | #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ | |
171 | #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ | |
172 | #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ | |
173 | #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ | |
174 | #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ | |
175 | #define FPSCR_RN 0x00000003 /* FPU rounding control */ | |
176 | ||
39fd0932 KG |
177 | /* Bit definitions for SPEFSCR. */ |
178 | #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ | |
179 | #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ | |
180 | #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ | |
181 | #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ | |
182 | #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ | |
183 | #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ | |
184 | #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ | |
185 | #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ | |
186 | #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ | |
187 | #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ | |
188 | #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ | |
189 | #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ | |
190 | #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ | |
191 | #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ | |
192 | #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ | |
193 | #define SPEFSCR_OV 0x00004000 /* Integer overflow */ | |
194 | #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ | |
195 | #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ | |
196 | #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ | |
197 | #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ | |
198 | #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ | |
199 | #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ | |
200 | #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ | |
201 | #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ | |
202 | #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ | |
203 | #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ | |
204 | #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ | |
205 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | |
206 | ||
14cf11af | 207 | /* Special Purpose Registers (SPRNs)*/ |
6edc642e THFL |
208 | |
209 | #ifdef CONFIG_40x | |
210 | #define SPRN_PID 0x3B1 /* Process ID */ | |
211 | #else | |
212 | #define SPRN_PID 0x030 /* Process ID */ | |
213 | #ifdef CONFIG_BOOKE | |
214 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | |
215 | #endif | |
216 | #endif | |
217 | ||
14cf11af | 218 | #define SPRN_CTR 0x009 /* Count Register */ |
4c198557 | 219 | #define SPRN_DSCR 0x11 |
48404f2e | 220 | #define SPRN_CFAR 0x1c /* Come From Address Register */ |
de56a948 PM |
221 | #define SPRN_AMR 0x1d /* Authority Mask Register */ |
222 | #define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */ | |
223 | #define SPRN_AMOR 0x15d /* Authority Mask Override Register */ | |
851d2e2f | 224 | #define SPRN_ACOP 0x1F /* Available Coprocessor Register */ |
97a0aac9 MN |
225 | #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ |
226 | #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ | |
227 | #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ | |
56758e3c | 228 | #define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ |
97a0aac9 | 229 | #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ |
9f04b9e3 PM |
230 | #define SPRN_CTRLF 0x088 |
231 | #define SPRN_CTRLT 0x098 | |
c902be71 AB |
232 | #define CTRL_CT 0xc0000000 /* current thread */ |
233 | #define CTRL_CT0 0x80000000 /* thread 0 */ | |
234 | #define CTRL_CT1 0x40000000 /* thread 1 */ | |
235 | #define CTRL_TE 0x00c00000 /* thread enable */ | |
9f04b9e3 | 236 | #define CTRL_RUNLATCH 0x1 |
a8190a59 | 237 | #define SPRN_DAWR 0xB4 |
e2186023 | 238 | #define SPRN_RPR 0xBA /* Relative Priority Register */ |
b005255e MN |
239 | #define SPRN_CIABR 0xBB |
240 | #define CIABR_PRIV 0x3 | |
241 | #define CIABR_PRIV_USER 1 | |
242 | #define CIABR_PRIV_SUPER 2 | |
243 | #define CIABR_PRIV_HYPER 3 | |
a8190a59 | 244 | #define SPRN_DAWRX 0xBC |
8563bf52 PM |
245 | #define DAWRX_USER __MASK(0) |
246 | #define DAWRX_KERNEL __MASK(1) | |
247 | #define DAWRX_HYP __MASK(2) | |
248 | #define DAWRX_WTI __MASK(3) | |
249 | #define DAWRX_WT __MASK(4) | |
250 | #define DAWRX_DR __MASK(5) | |
251 | #define DAWRX_DW __MASK(6) | |
14cf11af | 252 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |
d49747bd | 253 | #define SPRN_DABR2 0x13D /* e300 */ |
9176c0b1 | 254 | #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ |
8563bf52 PM |
255 | #define DABRX_USER __MASK(0) |
256 | #define DABRX_KERNEL __MASK(1) | |
257 | #define DABRX_HYP __MASK(2) | |
258 | #define DABRX_BTI __MASK(3) | |
4474ef05 | 259 | #define DABRX_ALL (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER) |
14cf11af | 260 | #define SPRN_DAR 0x013 /* Data Address Register */ |
d49747bd | 261 | #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ |
d6b89a19 | 262 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ |
14cf11af PM |
263 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ |
264 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ | |
265 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ | |
266 | #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ | |
376af594 | 267 | #define DSISR_NOSEGMENT 0x00200000 /* SLB miss */ |
697d3899 | 268 | #define DSISR_KEYFAULT 0x00200000 /* Key fault */ |
14cf11af PM |
269 | #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ |
270 | #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ | |
271 | #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ | |
272 | #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ | |
93b0f4dc | 273 | #define SPRN_TBU40 0x11E /* Timebase upper 40 bits (hyper, R/W) */ |
f050982a | 274 | #define SPRN_SPURR 0x134 /* Scaled PURR */ |
50fb8ebe BH |
275 | #define SPRN_HSPRG0 0x130 /* Hypervisor Scratch 0 */ |
276 | #define SPRN_HSPRG1 0x131 /* Hypervisor Scratch 1 */ | |
277 | #define SPRN_HDSISR 0x132 | |
278 | #define SPRN_HDAR 0x133 | |
279 | #define SPRN_HDEC 0x136 /* Hypervisor Decrementer */ | |
14cf11af | 280 | #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ |
50fb8ebe BH |
281 | #define SPRN_RMOR 0x138 /* Real mode offset register */ |
282 | #define SPRN_HRMOR 0x139 /* Real mode offset register */ | |
283 | #define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */ | |
284 | #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ | |
b005255e MN |
285 | #define SPRN_IC 0x350 /* Virtual Instruction Count */ |
286 | #define SPRN_VTB 0x351 /* Virtual Time Base */ | |
e2186023 | 287 | #define SPRN_LDBAR 0x352 /* LD Base Address Register */ |
b3d627a5 VS |
288 | #define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */ |
289 | #define SPRN_PMSR 0x355 /* Power Management Status Reg */ | |
e2186023 | 290 | #define SPRN_PMMAR 0x356 /* Power Management Memory Activity Register */ |
b3d627a5 VS |
291 | #define SPRN_PMCR 0x374 /* Power Management Control Register */ |
292 | ||
74e400ce MN |
293 | /* HFSCR and FSCR bit numbers are the same */ |
294 | #define FSCR_TAR_LG 8 /* Enable Target Address Register */ | |
295 | #define FSCR_EBB_LG 7 /* Enable Event Based Branching */ | |
296 | #define FSCR_TM_LG 5 /* Enable Transactional Memory */ | |
9f24b0c9 PM |
297 | #define FSCR_BHRB_LG 4 /* Enable Branch History Rolling Buffer*/ |
298 | #define FSCR_PM_LG 3 /* Enable prob/priv access to PMU SPRs */ | |
74e400ce MN |
299 | #define FSCR_DSCR_LG 2 /* Enable Data Stream Control Register */ |
300 | #define FSCR_VECVSX_LG 1 /* Enable VMX/VSX */ | |
301 | #define FSCR_FP_LG 0 /* Enable Floating Point */ | |
2468dcf6 | 302 | #define SPRN_FSCR 0x099 /* Facility Status & Control Register */ |
74e400ce MN |
303 | #define FSCR_TAR __MASK(FSCR_TAR_LG) |
304 | #define FSCR_EBB __MASK(FSCR_EBB_LG) | |
305 | #define FSCR_DSCR __MASK(FSCR_DSCR_LG) | |
04b418c9 | 306 | #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ |
74e400ce MN |
307 | #define HFSCR_TAR __MASK(FSCR_TAR_LG) |
308 | #define HFSCR_EBB __MASK(FSCR_EBB_LG) | |
309 | #define HFSCR_TM __MASK(FSCR_TM_LG) | |
310 | #define HFSCR_PM __MASK(FSCR_PM_LG) | |
311 | #define HFSCR_BHRB __MASK(FSCR_BHRB_LG) | |
312 | #define HFSCR_DSCR __MASK(FSCR_DSCR_LG) | |
313 | #define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG) | |
314 | #define HFSCR_FP __MASK(FSCR_FP_LG) | |
2468dcf6 | 315 | #define SPRN_TAR 0x32f /* Target Address Register */ |
1199919b | 316 | #define SPRN_LPCR 0x13E /* LPAR Control Register */ |
50fb8ebe BH |
317 | #define LPCR_VPM0 (1ul << (63-0)) |
318 | #define LPCR_VPM1 (1ul << (63-1)) | |
319 | #define LPCR_ISL (1ul << (63-2)) | |
923c53ca | 320 | #define LPCR_VC_SH (63-2) |
50fb8ebe | 321 | #define LPCR_DPFD_SH (63-11) |
a0144e2a | 322 | #define LPCR_DPFD (7ul << LPCR_DPFD_SH) |
da9d1d7f | 323 | #define LPCR_VRMASD (0x1ful << (63-16)) |
50fb8ebe BH |
324 | #define LPCR_VRMA_L (1ul << (63-12)) |
325 | #define LPCR_VRMA_LP0 (1ul << (63-15)) | |
326 | #define LPCR_VRMA_LP1 (1ul << (63-16)) | |
923c53ca | 327 | #define LPCR_VRMASD_SH (63-16) |
50fb8ebe | 328 | #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ |
aa04b4cc | 329 | #define LPCR_RMLS_SH (63-37) |
50fb8ebe | 330 | #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ |
e0622bd9 | 331 | #define LPCR_AIL 0x01800000 /* Alternate interrupt location */ |
b0302722 MN |
332 | #define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ |
333 | #define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ | |
e0622bd9 | 334 | #define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */ |
aa31e843 PM |
335 | #define LPCR_PECE 0x0001f000 /* powersave exit cause enable */ |
336 | #define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */ | |
337 | #define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */ | |
50fb8ebe BH |
338 | #define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ |
339 | #define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ | |
340 | #define LPCR_PECE2 0x00001000 /* machine check etc can cause exit */ | |
341 | #define LPCR_MER 0x00000800 /* Mediated External Exception */ | |
4619ac88 | 342 | #define LPCR_MER_SH 11 |
a0144e2a | 343 | #define LPCR_TC 0x00000200 /* Translation control */ |
923c53ca | 344 | #define LPCR_LPES 0x0000000c |
50fb8ebe BH |
345 | #define LPCR_LPES0 0x00000008 /* LPAR Env selector 0 */ |
346 | #define LPCR_LPES1 0x00000004 /* LPAR Env selector 1 */ | |
923c53ca | 347 | #define LPCR_LPES_SH 2 |
50fb8ebe BH |
348 | #define LPCR_RMI 0x00000002 /* real mode is cache inhibit */ |
349 | #define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */ | |
2bfd65e4 | 350 | #define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */ |
d30f6e48 | 351 | #ifndef SPRN_LPID |
50fb8ebe | 352 | #define SPRN_LPID 0x13F /* Logical Partition Identifier */ |
d30f6e48 | 353 | #endif |
de56a948 | 354 | #define LPID_RSVD 0x3ff /* Reserved LPID for partn switching */ |
50fb8ebe BH |
355 | #define SPRN_HMER 0x150 /* Hardware m? error recovery */ |
356 | #define SPRN_HMEER 0x151 /* Hardware m? enable error recovery */ | |
388cc6e1 PM |
357 | #define SPRN_PCR 0x152 /* Processor compatibility register */ |
358 | #define PCR_VEC_DIS (1ul << (63-0)) /* Vec. disable (bit NA since POWER8) */ | |
359 | #define PCR_VSX_DIS (1ul << (63-1)) /* VSX disable (bit NA since POWER8) */ | |
5557ae0e PM |
360 | #define PCR_TM_DIS (1ul << (63-2)) /* Trans. memory disable (POWER8) */ |
361 | #define PCR_ARCH_206 0x4 /* Architecture 2.06 */ | |
388cc6e1 | 362 | #define PCR_ARCH_205 0x2 /* Architecture 2.05 */ |
50fb8ebe BH |
363 | #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */ |
364 | #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */ | |
365 | #define SPRN_TLBVPNR 0x155 /* P7 TLB control register */ | |
366 | #define SPRN_TLBRPNR 0x156 /* P7 TLB control register */ | |
367 | #define SPRN_TLBLPIDR 0x157 /* P7 TLB control register */ | |
14cf11af PM |
368 | #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ |
369 | #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ | |
370 | #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ | |
371 | #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ | |
372 | #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ | |
373 | #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ | |
374 | #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ | |
375 | #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ | |
376 | #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ | |
377 | #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ | |
378 | #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ | |
379 | #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ | |
380 | #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ | |
381 | #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ | |
382 | #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ | |
383 | #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ | |
13e7a8e8 | 384 | #define SPRN_PPR 0x380 /* SMT Thread status Register */ |
77b54e9f | 385 | #define SPRN_TSCR 0x399 /* Thread Switch Control Register */ |
14cf11af PM |
386 | |
387 | #define SPRN_DEC 0x016 /* Decrement Register */ | |
446957ba | 388 | #define SPRN_DER 0x095 /* Debug Enable Register */ |
14cf11af PM |
389 | #define DER_RSTE 0x40000000 /* Reset Interrupt */ |
390 | #define DER_CHSTPE 0x20000000 /* Check Stop */ | |
391 | #define DER_MCIE 0x10000000 /* Machine Check Interrupt */ | |
392 | #define DER_EXTIE 0x02000000 /* External Interrupt */ | |
393 | #define DER_ALIE 0x01000000 /* Alignment Interrupt */ | |
394 | #define DER_PRIE 0x00800000 /* Program Interrupt */ | |
395 | #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ | |
396 | #define DER_DECIE 0x00200000 /* Decrementer Interrupt */ | |
397 | #define DER_SYSIE 0x00040000 /* System Call Interrupt */ | |
398 | #define DER_TRE 0x00020000 /* Trace Interrupt */ | |
399 | #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ | |
400 | #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ | |
401 | #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ | |
402 | #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ | |
403 | #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ | |
404 | #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ | |
405 | #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ | |
406 | #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ | |
407 | #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ | |
408 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | |
b005255e MN |
409 | #define SPRN_DHDES 0x0B1 /* Directed Hyp. Doorbell Exc. State */ |
410 | #define SPRN_DPDES 0x0B0 /* Directed Priv. Doorbell Exc. State */ | |
14cf11af PM |
411 | #define SPRN_EAR 0x11A /* External Address Register */ |
412 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | |
446957ba | 413 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Register */ |
14cf11af | 414 | #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ |
969391c5 | 415 | #define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */ |
14cf11af PM |
416 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ |
417 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ | |
418 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ | |
419 | #define HID0_SBCLK (1<<27) | |
420 | #define HID0_EICE (1<<26) | |
421 | #define HID0_TBEN (1<<26) /* Timebase enable - 745x */ | |
422 | #define HID0_ECLK (1<<25) | |
423 | #define HID0_PAR (1<<24) | |
424 | #define HID0_STEN (1<<24) /* Software table search enable - 745x */ | |
425 | #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ | |
426 | #define HID0_DOZE (1<<23) | |
427 | #define HID0_NAP (1<<22) | |
428 | #define HID0_SLEEP (1<<21) | |
429 | #define HID0_DPM (1<<20) | |
430 | #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ | |
431 | #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ | |
432 | #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ | |
433 | #define HID0_ICE (1<<15) /* Instruction Cache Enable */ | |
434 | #define HID0_DCE (1<<14) /* Data Cache Enable */ | |
435 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ | |
436 | #define HID0_DLOCK (1<<12) /* Data Cache Lock */ | |
437 | #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ | |
438 | #define HID0_DCI (1<<10) /* Data Cache Invalidate */ | |
439 | #define HID0_SPD (1<<9) /* Speculative disable */ | |
440 | #define HID0_DAPUEN (1<<8) /* Debug APU enable */ | |
441 | #define HID0_SGE (1<<7) /* Store Gathering Enable */ | |
442 | #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ | |
fc4033b2 | 443 | #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ |
14cf11af PM |
444 | #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ |
445 | #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ | |
446 | #define HID0_ABE (1<<3) /* Address Broadcast Enable */ | |
447 | #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ | |
448 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ | |
449 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ | |
450 | #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ | |
451 | #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ | |
e2186023 ME |
452 | /* POWER8 HID0 bits */ |
453 | #define HID0_POWER8_4LPARMODE __MASK(61) | |
454 | #define HID0_POWER8_2LPARMODE __MASK(57) | |
455 | #define HID0_POWER8_1TO2LPAR __MASK(52) | |
456 | #define HID0_POWER8_1TO4LPAR __MASK(51) | |
457 | #define HID0_POWER8_DYNLPARDIS __MASK(48) | |
14cf11af PM |
458 | |
459 | #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | |
86985db6 | 460 | #ifdef CONFIG_6xx |
14cf11af PM |
461 | #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ |
462 | #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ | |
463 | #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ | |
464 | #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ | |
465 | #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ | |
466 | #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ | |
467 | #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ | |
468 | #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ | |
469 | #define HID1_PS (1<<16) /* 750FX PLL selection */ | |
86985db6 | 470 | #endif |
14cf11af | 471 | #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ |
d6d549b2 | 472 | #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ |
14cf11af | 473 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ |
d49747bd SW |
474 | #define SPRN_IABR2 0x3FA /* 83xx */ |
475 | #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ | |
b005255e | 476 | #define SPRN_IAMR 0x03D /* Instr. Authority Mask Reg */ |
14cf11af | 477 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ |
969391c5 PM |
478 | #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */ |
479 | #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */ | |
480 | #define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */ | |
481 | #define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */ | |
a0144e2a | 482 | #define HID4_RMOR (0xFFFFul << HID4_RMOR_SH) |
969391c5 PM |
483 | #define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */ |
484 | #define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */ | |
485 | #define HID4_LPID1_SH 0 /* partition ID top 2 bits */ | |
d6d549b2 | 486 | #define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ |
14cf11af | 487 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ |
d6b89a19 MN |
488 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ |
489 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ | |
490 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ | |
491 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ | |
492 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ | |
493 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ | |
494 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ | |
495 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ | |
496 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ | |
497 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ | |
14cf11af PM |
498 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) |
499 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ | |
500 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | |
501 | #endif | |
502 | #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ | |
503 | #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ | |
504 | #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ | |
505 | #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ | |
506 | #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ | |
507 | #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ | |
508 | #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ | |
509 | #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ | |
510 | #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ | |
511 | #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ | |
512 | #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ | |
513 | #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ | |
514 | #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ | |
515 | #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ | |
516 | #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ | |
517 | #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ | |
518 | #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ | |
519 | #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ | |
520 | #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ | |
521 | #define ICTRL_EICE 0x08000000 /* enable icache parity errs */ | |
522 | #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ | |
523 | #define ICTRL_EICP 0x00000100 /* enable icache par. check */ | |
524 | #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ | |
525 | #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ | |
446957ba | 526 | #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */ |
14cf11af PM |
527 | #define SPRN_L2CR2 0x3f8 |
528 | #define L2CR_L2E 0x80000000 /* L2 enable */ | |
529 | #define L2CR_L2PE 0x40000000 /* L2 parity enable */ | |
530 | #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ | |
531 | #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ | |
532 | #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ | |
533 | #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ | |
534 | #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ | |
535 | #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ | |
536 | #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ | |
537 | #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ | |
538 | #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ | |
539 | #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ | |
540 | #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ | |
541 | #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ | |
542 | #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ | |
543 | #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ | |
544 | #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ | |
545 | #define L2CR_L2DO 0x00400000 /* L2 data only */ | |
546 | #define L2CR_L2I 0x00200000 /* L2 global invalidate */ | |
547 | #define L2CR_L2CTL 0x00100000 /* L2 RAM control */ | |
548 | #define L2CR_L2WT 0x00080000 /* L2 write-through */ | |
549 | #define L2CR_L2TS 0x00040000 /* L2 test support */ | |
550 | #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ | |
551 | #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ | |
552 | #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ | |
553 | #define L2CR_L2SL 0x00008000 /* L2 DLL slow */ | |
554 | #define L2CR_L2DF 0x00004000 /* L2 differential clock */ | |
555 | #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ | |
556 | #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ | |
557 | #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ | |
558 | #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ | |
559 | #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ | |
560 | #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ | |
446957ba | 561 | #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Register */ |
14cf11af PM |
562 | #define L3CR_L3E 0x80000000 /* L3 enable */ |
563 | #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ | |
564 | #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ | |
565 | #define L3CR_L3SIZ 0x10000000 /* L3 size */ | |
566 | #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ | |
567 | #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ | |
568 | #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ | |
569 | #define L3CR_L3IO 0x00400000 /* L3 instruction only */ | |
570 | #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ | |
571 | #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ | |
572 | #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ | |
573 | #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ | |
574 | #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ | |
575 | #define L3CR_L3I 0x00000400 /* L3 global invalidate */ | |
576 | #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ | |
577 | #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ | |
578 | #define L3CR_L3DO 0x00000040 /* L3 data only mode */ | |
579 | #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ | |
580 | #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ | |
9f04b9e3 | 581 | |
14cf11af PM |
582 | #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ |
583 | #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ | |
584 | #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ | |
585 | #define SPRN_LDSTDB 0x3f4 /* */ | |
586 | #define SPRN_LR 0x008 /* Link Register */ | |
14cf11af PM |
587 | #ifndef SPRN_PIR |
588 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | |
589 | #endif | |
42d02b81 | 590 | #define SPRN_TIR 0x1BE /* Thread Identification Register */ |
e9983344 | 591 | #define SPRN_PTCR 0x1D0 /* Partition table control Register */ |
b005255e | 592 | #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ |
14cf11af PM |
593 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
594 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | |
d6b89a19 | 595 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ |
14cf11af PM |
596 | #define SPRN_PVR 0x11F /* Processor Version Register */ |
597 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | |
598 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | |
599 | #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ | |
799d6046 | 600 | #define SPRN_ASR 0x118 /* Address Space Register */ |
14cf11af PM |
601 | #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ |
602 | #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ | |
603 | #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ | |
604 | #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ | |
605 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | |
18ad51dd | 606 | #define SPRN_USPRG3 0x103 /* SPRG3 userspace read */ |
14cf11af | 607 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ |
9d378dfa | 608 | #define SPRN_USPRG4 0x104 /* SPRG4 userspace read */ |
14cf11af | 609 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ |
9d378dfa | 610 | #define SPRN_USPRG5 0x105 /* SPRG5 userspace read */ |
14cf11af | 611 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ |
9d378dfa | 612 | #define SPRN_USPRG6 0x106 /* SPRG6 userspace read */ |
14cf11af | 613 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ |
9d378dfa | 614 | #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ |
14cf11af PM |
615 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ |
616 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | |
342d3db7 PM |
617 | #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ |
618 | #define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ | |
619 | #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ | |
c902be71 | 620 | #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ |
755563bc | 621 | #define SRR1_WAKEMASK_P8 0x003c0000 /* reason for wakeup on POWER8 */ |
c902be71 AB |
622 | #define SRR1_WAKESYSERR 0x00300000 /* System error */ |
623 | #define SRR1_WAKEEE 0x00200000 /* External interrupt */ | |
624 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ | |
50fb8ebe | 625 | #define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ |
c902be71 | 626 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ |
755563bc | 627 | #define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell on P8 */ |
c902be71 | 628 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ |
50fb8ebe | 629 | #define SRR1_WAKERESET 0x00100000 /* System reset */ |
755563bc | 630 | #define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell on P8 */ |
50fb8ebe BH |
631 | #define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask [46:47] */ |
632 | #define SRR1_WS_DEEPEST 0x00030000 /* Some resources not maintained, | |
633 | * may not be recoverable */ | |
634 | #define SRR1_WS_DEEPER 0x00020000 /* Some resources not maintained */ | |
635 | #define SRR1_WS_DEEP 0x00010000 /* All resources maintained */ | |
25a8a02d | 636 | #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ |
28c483b6 | 637 | #define SRR1_PROGILL 0x00080000 /* Illegal instruction */ |
25a8a02d AG |
638 | #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ |
639 | #define SRR1_PROGTRAP 0x00020000 /* Trap */ | |
640 | #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ | |
50fb8ebe | 641 | |
acf7d768 BH |
642 | #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ |
643 | #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ | |
b92a66a6 | 644 | #define HSRR1_DENORM 0x00100000 /* Denorm exception */ |
c902be71 | 645 | |
c388cfeb OJ |
646 | #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ |
647 | #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ | |
648 | #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ | |
649 | #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ | |
650 | #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ | |
651 | ||
14cf11af PM |
652 | #ifndef SPRN_SVR |
653 | #define SPRN_SVR 0x11E /* System Version Register */ | |
654 | #endif | |
655 | #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ | |
656 | /* these bits were defined in inverted endian sense originally, ugh, confusing */ | |
657 | #define THRM1_TIN (1 << 31) | |
658 | #define THRM1_TIV (1 << 30) | |
659 | #define THRM1_THRES(x) ((x&0x7f)<<23) | |
660 | #define THRM3_SITV(x) ((x&0x3fff)<<1) | |
661 | #define THRM1_TID (1<<2) | |
662 | #define THRM1_TIE (1<<1) | |
663 | #define THRM1_V (1<<0) | |
664 | #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ | |
665 | #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ | |
666 | #define THRM3_E (1<<0) | |
667 | #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ | |
668 | #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ | |
669 | #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ | |
670 | #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ | |
671 | #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ | |
672 | #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ | |
673 | #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ | |
674 | #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ | |
675 | #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ | |
676 | #define SPRN_XER 0x001 /* Fixed Point Exception Register */ | |
677 | ||
d6d549b2 AG |
678 | #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ |
679 | #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ | |
680 | #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ | |
681 | #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ | |
682 | #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ | |
683 | #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ | |
684 | #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ | |
685 | ||
4350147a BH |
686 | #define SPRN_SCOMC 0x114 /* SCOM Access Control */ |
687 | #define SPRN_SCOMD 0x115 /* SCOM Access DATA */ | |
688 | ||
9f04b9e3 PM |
689 | /* Performance monitor SPRs */ |
690 | #ifdef CONFIG_PPC64 | |
691 | #define SPRN_MMCR0 795 | |
692 | #define MMCR0_FC 0x80000000UL /* freeze counters */ | |
693 | #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ | |
694 | #define MMCR0_KERNEL_DISABLE MMCR0_FCS | |
695 | #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ | |
696 | #define MMCR0_PROBLEM_DISABLE MMCR0_FCP | |
697 | #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ | |
698 | #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ | |
9bc01a9b PM |
699 | #define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */ |
700 | #define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */ | |
9f04b9e3 | 701 | #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ |
76cb8a78 | 702 | #define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */ |
330a1eb7 ME |
703 | #define MMCR0_EBE 0x00100000UL /* Event based branch enable */ |
704 | #define MMCR0_PMCC 0x000c0000UL /* PMC control */ | |
705 | #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */ | |
9f04b9e3 | 706 | #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ |
9bc01a9b | 707 | #define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/ |
9f04b9e3 | 708 | #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ |
9bc01a9b PM |
709 | #define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */ |
710 | #define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */ | |
711 | /* performance monitor alert has occurred, set to 0 after handling exception */ | |
712 | #define MMCR0_PMAO ASM_CONST(0x00000080) | |
9f04b9e3 | 713 | #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ |
7a7a41f9 | 714 | #define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */ |
9f04b9e3 PM |
715 | #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ |
716 | #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ | |
717 | #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ | |
718 | #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ | |
719 | #define SPRN_MMCR1 798 | |
8dd75ccb | 720 | #define SPRN_MMCR2 785 |
9f04b9e3 | 721 | #define SPRN_MMCRA 0x312 |
0bbd0d4b | 722 | #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ |
81cd5ae3 AB |
723 | #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL |
724 | #define MMCRA_SDAR_ERAT_MISS 0x20000000UL | |
9f04b9e3 PM |
725 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ |
726 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ | |
078f1940 | 727 | #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ |
728 | #define MMCRA_SLOT_SHIFT 24 | |
9f04b9e3 | 729 | #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ |
0bbd0d4b | 730 | #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ |
e78dbc80 MN |
731 | #define POWER6_MMCRA_SIHV 0x0000040000000000ULL |
732 | #define POWER6_MMCRA_SIPR 0x0000020000000000ULL | |
733 | #define POWER6_MMCRA_THRM 0x00000020UL | |
734 | #define POWER6_MMCRA_OTHER 0x0000000EUL | |
e6878835 | 735 | |
736 | #define POWER7P_MMCRA_SIAR_VALID 0x10000000 /* P7+ SIAR contents valid */ | |
737 | #define POWER7P_MMCRA_SDAR_VALID 0x08000000 /* P7+ SDAR contents valid */ | |
738 | ||
240686c1 ME |
739 | #define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ |
740 | #define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ | |
741 | #define SPRN_MMCRC 851 /* Core monitor mode control register */ | |
9353374b ME |
742 | #define SPRN_EBBHR 804 /* Event based branch handler register */ |
743 | #define SPRN_EBBRR 805 /* Event based branch return register */ | |
744 | #define SPRN_BESCR 806 /* Branch event status and control register */ | |
c2e37a26 | 745 | #define BESCR_GE 0x8000000000000000ULL /* Global Enable */ |
b005255e | 746 | #define SPRN_WORT 895 /* Workload optimization register - thread */ |
77b54e9f | 747 | #define SPRN_WORC 863 /* Workload optimization register - core */ |
240686c1 | 748 | |
9f04b9e3 PM |
749 | #define SPRN_PMC1 787 |
750 | #define SPRN_PMC2 788 | |
751 | #define SPRN_PMC3 789 | |
752 | #define SPRN_PMC4 790 | |
753 | #define SPRN_PMC5 791 | |
754 | #define SPRN_PMC6 792 | |
755 | #define SPRN_PMC7 793 | |
756 | #define SPRN_PMC8 794 | |
8f61aa32 ME |
757 | #define SPRN_SIER 784 |
758 | #define SIER_SIPR 0x2000000 /* Sampled MSR_PR */ | |
759 | #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ | |
760 | #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ | |
761 | #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ | |
d23fac2b TH |
762 | #define SPRN_SIAR 796 |
763 | #define SPRN_SDAR 797 | |
b005255e MN |
764 | #define SPRN_TACR 888 |
765 | #define SPRN_TCSCR 889 | |
766 | #define SPRN_CSIGR 890 | |
767 | #define SPRN_SPMC1 892 | |
768 | #define SPRN_SPMC2 893 | |
9f04b9e3 | 769 | |
330a1eb7 ME |
770 | /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */ |
771 | #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO) | |
772 | #define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */ | |
773 | #define SIER_USER_MASK 0x7fffffUL | |
774 | ||
25fc530e OJ |
775 | #define SPRN_PA6T_MMCR0 795 |
776 | #define PA6T_MMCR0_EN0 0x0000000000000001UL | |
777 | #define PA6T_MMCR0_EN1 0x0000000000000002UL | |
778 | #define PA6T_MMCR0_EN2 0x0000000000000004UL | |
779 | #define PA6T_MMCR0_EN3 0x0000000000000008UL | |
780 | #define PA6T_MMCR0_EN4 0x0000000000000010UL | |
781 | #define PA6T_MMCR0_EN5 0x0000000000000020UL | |
782 | #define PA6T_MMCR0_SUPEN 0x0000000000000040UL | |
783 | #define PA6T_MMCR0_PREN 0x0000000000000080UL | |
784 | #define PA6T_MMCR0_HYPEN 0x0000000000000100UL | |
785 | #define PA6T_MMCR0_FCM0 0x0000000000000200UL | |
786 | #define PA6T_MMCR0_FCM1 0x0000000000000400UL | |
787 | #define PA6T_MMCR0_INTGEN 0x0000000000000800UL | |
788 | #define PA6T_MMCR0_INTEN0 0x0000000000001000UL | |
789 | #define PA6T_MMCR0_INTEN1 0x0000000000002000UL | |
790 | #define PA6T_MMCR0_INTEN2 0x0000000000004000UL | |
791 | #define PA6T_MMCR0_INTEN3 0x0000000000008000UL | |
792 | #define PA6T_MMCR0_INTEN4 0x0000000000010000UL | |
793 | #define PA6T_MMCR0_INTEN5 0x0000000000020000UL | |
794 | #define PA6T_MMCR0_DISCNT 0x0000000000040000UL | |
795 | #define PA6T_MMCR0_UOP 0x0000000000080000UL | |
796 | #define PA6T_MMCR0_TRG 0x0000000000100000UL | |
797 | #define PA6T_MMCR0_TRGEN 0x0000000000200000UL | |
798 | #define PA6T_MMCR0_TRGREG 0x0000000001600000UL | |
799 | #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL | |
800 | #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL | |
801 | #define PA6T_MMCR0_PROEN 0x0000000008000000UL | |
802 | #define PA6T_MMCR0_PROLOG 0x0000000010000000UL | |
803 | #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL | |
804 | #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL | |
805 | #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL | |
806 | #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL | |
807 | #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL | |
808 | #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL | |
809 | #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL | |
810 | #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL | |
811 | #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL | |
812 | #define PA6T_MMCR0_PCTEN 0x0000004000000000UL | |
813 | #define PA6T_MMCR0_SOCEN 0x0000008000000000UL | |
814 | #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL | |
815 | ||
816 | #define SPRN_PA6T_MMCR1 798 | |
817 | #define PA6T_MMCR1_ES2 0x00000000000000ffUL | |
818 | #define PA6T_MMCR1_ES3 0x000000000000ff00UL | |
819 | #define PA6T_MMCR1_ES4 0x0000000000ff0000UL | |
820 | #define PA6T_MMCR1_ES5 0x00000000ff000000UL | |
821 | ||
2e1957fd OJ |
822 | #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ |
823 | #define SPRN_PA6T_UPMC1 772 /* ... */ | |
25fc530e OJ |
824 | #define SPRN_PA6T_UPMC2 773 |
825 | #define SPRN_PA6T_UPMC3 774 | |
826 | #define SPRN_PA6T_UPMC4 775 | |
827 | #define SPRN_PA6T_UPMC5 776 | |
2e1957fd OJ |
828 | #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ |
829 | #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ | |
830 | #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ | |
831 | #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ | |
832 | #define SPRN_PA6T_PMC0 787 | |
833 | #define SPRN_PA6T_PMC1 788 | |
834 | #define SPRN_PA6T_PMC2 789 | |
835 | #define SPRN_PA6T_PMC3 790 | |
836 | #define SPRN_PA6T_PMC4 791 | |
837 | #define SPRN_PA6T_PMC5 792 | |
838 | #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ | |
839 | #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ | |
840 | #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ | |
841 | #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ | |
842 | ||
843 | #define SPRN_PA6T_IER 981 /* Icache Error Register */ | |
844 | #define SPRN_PA6T_DER 982 /* Dcache Error Register */ | |
845 | #define SPRN_PA6T_BER 862 /* BIU Error Address Register */ | |
846 | #define SPRN_PA6T_MER 849 /* MMU Error Register */ | |
847 | ||
848 | #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ | |
849 | #define SPRN_PA6T_IMA1 881 /* ... */ | |
850 | #define SPRN_PA6T_IMA2 882 | |
851 | #define SPRN_PA6T_IMA3 883 | |
852 | #define SPRN_PA6T_IMA4 884 | |
853 | #define SPRN_PA6T_IMA5 885 | |
854 | #define SPRN_PA6T_IMA6 886 | |
855 | #define SPRN_PA6T_IMA7 887 | |
856 | #define SPRN_PA6T_IMA8 888 | |
857 | #define SPRN_PA6T_IMA9 889 | |
858 | #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ | |
859 | #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ | |
860 | #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ | |
cda563fb | 861 | #define SPRN_BKMK 1020 /* Cell Bookmark Register */ |
2e1957fd OJ |
862 | #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ |
863 | ||
6529c13d | 864 | |
9f04b9e3 | 865 | #else /* 32-bit */ |
555d97ac AF |
866 | #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ |
867 | #define MMCR0_FC 0x80000000UL /* freeze counters */ | |
868 | #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ | |
869 | #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ | |
870 | #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ | |
871 | #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ | |
872 | #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ | |
873 | #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ | |
874 | #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ | |
875 | #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ | |
876 | #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ | |
877 | #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ | |
878 | #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ | |
879 | #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ | |
880 | ||
881 | #define SPRN_MMCR1 956 | |
882 | #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ | |
883 | #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ | |
884 | #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ | |
885 | #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ | |
886 | #define SPRN_MMCR2 944 | |
887 | #define SPRN_PMC1 953 /* Performance Counter Register 1 */ | |
888 | #define SPRN_PMC2 954 /* Performance Counter Register 2 */ | |
889 | #define SPRN_PMC3 957 /* Performance Counter Register 3 */ | |
890 | #define SPRN_PMC4 958 /* Performance Counter Register 4 */ | |
891 | #define SPRN_PMC5 945 /* Performance Counter Register 5 */ | |
892 | #define SPRN_PMC6 946 /* Performance Counter Register 6 */ | |
893 | ||
894 | #define SPRN_SIAR 955 /* Sampled Instruction Address Register */ | |
9f04b9e3 | 895 | |
14cf11af PM |
896 | /* Bit definitions for MMCR0 and PMC1 / PMC2. */ |
897 | #define MMCR0_PMC1_CYCLES (1 << 7) | |
898 | #define MMCR0_PMC1_ICACHEMISS (5 << 7) | |
899 | #define MMCR0_PMC1_DTLB (6 << 7) | |
900 | #define MMCR0_PMC2_DCACHEMISS 0x6 | |
901 | #define MMCR0_PMC2_CYCLES 0x1 | |
902 | #define MMCR0_PMC2_ITLB 0x7 | |
903 | #define MMCR0_PMC2_LOADMISSTIME 0x5 | |
9f04b9e3 | 904 | #endif |
14cf11af | 905 | |
ee43eb78 BH |
906 | /* |
907 | * SPRG usage: | |
908 | * | |
909 | * All 64-bit: | |
2dd60d79 BH |
910 | * - SPRG1 stores PACA pointer except 64-bit server in |
911 | * HV mode in which case it is HSPRG0 | |
ee43eb78 BH |
912 | * |
913 | * 64-bit server: | |
98ae22e1 | 914 | * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4) |
063517be | 915 | * - SPRG2 scratch for exception vectors |
18ad51dd | 916 | * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible) |
2dd60d79 BH |
917 | * - HSPRG0 stores PACA in HV mode |
918 | * - HSPRG1 scratch for "HV" exceptions | |
ee43eb78 | 919 | * |
13363ab9 BH |
920 | * 64-bit embedded |
921 | * - SPRG0 generic exception scratch | |
922 | * - SPRG2 TLB exception stack | |
9d378dfa | 923 | * - SPRG3 critical exception scratch (user visible, sorry!) |
13363ab9 BH |
924 | * - SPRG4 unused (user visible) |
925 | * - SPRG6 TLB miss scratch (user visible, sorry !) | |
9d378dfa | 926 | * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible) |
13363ab9 BH |
927 | * - SPRG8 machine check exception scratch |
928 | * - SPRG9 debug exception scratch | |
929 | * | |
ee43eb78 BH |
930 | * All 32-bit: |
931 | * - SPRG3 current thread_info pointer | |
932 | * (virtual on BookE, physical on others) | |
933 | * | |
934 | * 32-bit classic: | |
935 | * - SPRG0 scratch for exception vectors | |
936 | * - SPRG1 scratch for exception vectors | |
937 | * - SPRG2 indicator that we are in RTAS | |
938 | * - SPRG4 (603 only) pseudo TLB LRU data | |
939 | * | |
940 | * 32-bit 40x: | |
941 | * - SPRG0 scratch for exception vectors | |
942 | * - SPRG1 scratch for exception vectors | |
943 | * - SPRG2 scratch for exception vectors | |
944 | * - SPRG4 scratch for exception vectors (not 403) | |
945 | * - SPRG5 scratch for exception vectors (not 403) | |
946 | * - SPRG6 scratch for exception vectors (not 403) | |
947 | * - SPRG7 scratch for exception vectors (not 403) | |
948 | * | |
949 | * 32-bit 440 and FSL BookE: | |
950 | * - SPRG0 scratch for exception vectors | |
951 | * - SPRG1 scratch for exception vectors (*) | |
952 | * - SPRG2 scratch for crit interrupts handler | |
953 | * - SPRG4 scratch for exception vectors | |
954 | * - SPRG5 scratch for exception vectors | |
955 | * - SPRG6 scratch for machine check handler | |
956 | * - SPRG7 scratch for exception vectors | |
957 | * - SPRG9 scratch for debug vectors (e500 only) | |
958 | * | |
959 | * Additionally, BookE separates "read" and "write" | |
960 | * of those registers. That allows to use the userspace | |
961 | * readable variant for reads, which can avoid a fault | |
962 | * with KVM type virtualization. | |
963 | * | |
ee43eb78 BH |
964 | * 32-bit 8xx: |
965 | * - SPRG0 scratch for exception vectors | |
966 | * - SPRG1 scratch for exception vectors | |
ae466bde | 967 | * - SPRG2 scratch for exception vectors |
ee43eb78 BH |
968 | * |
969 | */ | |
970 | #ifdef CONFIG_PPC64 | |
063517be | 971 | #define SPRN_SPRG_PACA SPRN_SPRG1 |
ee43eb78 BH |
972 | #else |
973 | #define SPRN_SPRG_THREAD SPRN_SPRG3 | |
974 | #endif | |
975 | ||
976 | #ifdef CONFIG_PPC_BOOK3S_64 | |
063517be | 977 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 |
2dd60d79 BH |
978 | #define SPRN_SPRG_HPACA SPRN_HSPRG0 |
979 | #define SPRN_SPRG_HSCRATCH0 SPRN_HSPRG1 | |
9d378dfa SW |
980 | #define SPRN_SPRG_VDSO_READ SPRN_USPRG3 |
981 | #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG3 | |
2dd60d79 BH |
982 | |
983 | #define GET_PACA(rX) \ | |
984 | BEGIN_FTR_SECTION_NESTED(66); \ | |
985 | mfspr rX,SPRN_SPRG_PACA; \ | |
986 | FTR_SECTION_ELSE_NESTED(66); \ | |
987 | mfspr rX,SPRN_SPRG_HPACA; \ | |
969391c5 | 988 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) |
2dd60d79 BH |
989 | |
990 | #define SET_PACA(rX) \ | |
991 | BEGIN_FTR_SECTION_NESTED(66); \ | |
992 | mtspr SPRN_SPRG_PACA,rX; \ | |
993 | FTR_SECTION_ELSE_NESTED(66); \ | |
994 | mtspr SPRN_SPRG_HPACA,rX; \ | |
969391c5 | 995 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) |
673b189a PM |
996 | |
997 | #define GET_SCRATCH0(rX) \ | |
998 | BEGIN_FTR_SECTION_NESTED(66); \ | |
999 | mfspr rX,SPRN_SPRG_SCRATCH0; \ | |
1000 | FTR_SECTION_ELSE_NESTED(66); \ | |
1001 | mfspr rX,SPRN_SPRG_HSCRATCH0; \ | |
969391c5 | 1002 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) |
673b189a PM |
1003 | |
1004 | #define SET_SCRATCH0(rX) \ | |
1005 | BEGIN_FTR_SECTION_NESTED(66); \ | |
1006 | mtspr SPRN_SPRG_SCRATCH0,rX; \ | |
1007 | FTR_SECTION_ELSE_NESTED(66); \ | |
1008 | mtspr SPRN_SPRG_HSCRATCH0,rX; \ | |
969391c5 | 1009 | ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66) |
593adf31 PM |
1010 | |
1011 | #else /* CONFIG_PPC_BOOK3S_64 */ | |
1012 | #define GET_SCRATCH0(rX) mfspr rX,SPRN_SPRG_SCRATCH0 | |
1013 | #define SET_SCRATCH0(rX) mtspr SPRN_SPRG_SCRATCH0,rX | |
1014 | ||
ee43eb78 BH |
1015 | #endif |
1016 | ||
13363ab9 BH |
1017 | #ifdef CONFIG_PPC_BOOK3E_64 |
1018 | #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 | |
8b64a9df | 1019 | #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG3 |
13363ab9 BH |
1020 | #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 |
1021 | #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 | |
1022 | #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 | |
1023 | #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 | |
5473eb1c | 1024 | #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH |
9d378dfa SW |
1025 | #define SPRN_SPRG_VDSO_READ SPRN_USPRG7 |
1026 | #define SPRN_SPRG_VDSO_WRITE SPRN_SPRG7 | |
2dd60d79 BH |
1027 | |
1028 | #define SET_PACA(rX) mtspr SPRN_SPRG_PACA,rX | |
1029 | #define GET_PACA(rX) mfspr rX,SPRN_SPRG_PACA | |
1030 | ||
13363ab9 BH |
1031 | #endif |
1032 | ||
ee43eb78 BH |
1033 | #ifdef CONFIG_PPC_BOOK3S_32 |
1034 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 | |
1035 | #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 | |
1036 | #define SPRN_SPRG_RTAS SPRN_SPRG2 | |
1037 | #define SPRN_SPRG_603_LRU SPRN_SPRG4 | |
1038 | #endif | |
1039 | ||
1040 | #ifdef CONFIG_40x | |
1041 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 | |
1042 | #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 | |
1043 | #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 | |
1044 | #define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 | |
1045 | #define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 | |
1046 | #define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 | |
1047 | #define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 | |
1048 | #endif | |
1049 | ||
1050 | #ifdef CONFIG_BOOKE | |
1051 | #define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 | |
1052 | #define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 | |
1053 | #define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 | |
1054 | #define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 | |
1055 | #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 | |
1056 | #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 | |
1057 | #define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R | |
1058 | #define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W | |
1059 | #define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R | |
1060 | #define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W | |
1325a684 AK |
1061 | #define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG1 |
1062 | #define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG1 | |
ee43eb78 BH |
1063 | #define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R |
1064 | #define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W | |
1065 | #ifdef CONFIG_E200 | |
1066 | #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R | |
1067 | #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W | |
1068 | #else | |
1069 | #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 | |
1070 | #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 | |
1071 | #endif | |
ee43eb78 BH |
1072 | #endif |
1073 | ||
1074 | #ifdef CONFIG_8xx | |
1075 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 | |
1076 | #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 | |
ae466bde | 1077 | #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 |
ee43eb78 BH |
1078 | #endif |
1079 | ||
2dd60d79 BH |
1080 | |
1081 | ||
3a2c48cf AB |
1082 | /* |
1083 | * An mtfsf instruction with the L bit set. On CPUs that support this a | |
52aed7cd | 1084 | * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. |
3a2c48cf AB |
1085 | * |
1086 | * Until binutils gets the new form of mtfsf, hardwire the instruction. | |
1087 | */ | |
1088 | #ifdef CONFIG_PPC64 | |
1089 | #define MTFSF_L(REG) \ | |
1090 | .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) | |
1091 | #else | |
1092 | #define MTFSF_L(REG) mtfsf 0xff, (REG) | |
1093 | #endif | |
1094 | ||
14cf11af PM |
1095 | /* Processor Version Register (PVR) field extraction */ |
1096 | ||
1097 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | |
1098 | #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ | |
1099 | ||
d3dbeef6 | 1100 | #define pvr_version_is(pvr) (PVR_VER(mfspr(SPRN_PVR)) == (pvr)) |
9f04b9e3 | 1101 | |
14cf11af PM |
1102 | /* |
1103 | * IBM has further subdivided the standard PowerPC 16-bit version and | |
1104 | * revision subfields of the PVR for the PowerPC 403s into the following: | |
1105 | */ | |
1106 | ||
1107 | #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ | |
1108 | #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ | |
1109 | #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ | |
1110 | #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ | |
1111 | #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ | |
1112 | #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ | |
1113 | ||
1114 | /* Processor Version Numbers */ | |
1115 | ||
1116 | #define PVR_403GA 0x00200000 | |
1117 | #define PVR_403GB 0x00200100 | |
1118 | #define PVR_403GC 0x00200200 | |
1119 | #define PVR_403GCX 0x00201400 | |
1120 | #define PVR_405GP 0x40110000 | |
e7f75ad0 | 1121 | #define PVR_476 0x11a52000 |
df777bd3 | 1122 | #define PVR_476FPE 0x7ff50000 |
14cf11af PM |
1123 | #define PVR_STB03XXX 0x40310000 |
1124 | #define PVR_NP405H 0x41410000 | |
1125 | #define PVR_NP405L 0x41610000 | |
1126 | #define PVR_601 0x00010000 | |
1127 | #define PVR_602 0x00050000 | |
1128 | #define PVR_603 0x00030000 | |
1129 | #define PVR_603e 0x00060000 | |
1130 | #define PVR_603ev 0x00070000 | |
1131 | #define PVR_603r 0x00071000 | |
1132 | #define PVR_604 0x00040000 | |
1133 | #define PVR_604e 0x00090000 | |
1134 | #define PVR_604r 0x000A0000 | |
1135 | #define PVR_620 0x00140000 | |
1136 | #define PVR_740 0x00080000 | |
1137 | #define PVR_750 PVR_740 | |
1138 | #define PVR_740P 0x10080000 | |
1139 | #define PVR_750P PVR_740P | |
1140 | #define PVR_7400 0x000C0000 | |
1141 | #define PVR_7410 0x800C0000 | |
1142 | #define PVR_7450 0x80000000 | |
1143 | #define PVR_8540 0x80200000 | |
1144 | #define PVR_8560 0x80200000 | |
ac6f1203 LY |
1145 | #define PVR_VER_E500V1 0x8020 |
1146 | #define PVR_VER_E500V2 0x8021 | |
b0b7dcbd WD |
1147 | #define PVR_VER_E500MC 0x8023 |
1148 | #define PVR_VER_E5500 0x8024 | |
71a6fa17 WD |
1149 | #define PVR_VER_E6500 0x8040 |
1150 | ||
14cf11af PM |
1151 | /* |
1152 | * For the 8xx processors, all of them report the same PVR family for | |
1153 | * the PowerPC core. The various versions of these processors must be | |
1154 | * differentiated by the version number in the Communication Processor | |
1155 | * Module (CPM). | |
1156 | */ | |
1157 | #define PVR_821 0x00500000 | |
1158 | #define PVR_823 PVR_821 | |
1159 | #define PVR_850 PVR_821 | |
1160 | #define PVR_860 PVR_821 | |
1161 | #define PVR_8240 0x00810100 | |
1162 | #define PVR_8245 0x80811014 | |
1163 | #define PVR_8260 PVR_8240 | |
1164 | ||
b4e8c8dd TS |
1165 | /* 476 Simulator seems to currently have the PVR of the 602... */ |
1166 | #define PVR_476_ISS 0x00052000 | |
1167 | ||
9f04b9e3 | 1168 | /* 64-bit processors */ |
d3dbeef6 ME |
1169 | #define PVR_NORTHSTAR 0x0033 |
1170 | #define PVR_PULSAR 0x0034 | |
1171 | #define PVR_POWER4 0x0035 | |
1172 | #define PVR_ICESTAR 0x0036 | |
1173 | #define PVR_SSTAR 0x0037 | |
1174 | #define PVR_POWER4p 0x0038 | |
1175 | #define PVR_970 0x0039 | |
1176 | #define PVR_POWER5 0x003A | |
1177 | #define PVR_POWER5p 0x003B | |
1178 | #define PVR_970FX 0x003C | |
1179 | #define PVR_POWER6 0x003E | |
1180 | #define PVR_POWER7 0x003F | |
1181 | #define PVR_630 0x0040 | |
1182 | #define PVR_630p 0x0041 | |
1183 | #define PVR_970MP 0x0044 | |
1184 | #define PVR_970GX 0x0045 | |
22d8ce88 | 1185 | #define PVR_POWER7p 0x004A |
33959f88 | 1186 | #define PVR_POWER8E 0x004B |
86c9ffcc | 1187 | #define PVR_POWER8NVL 0x004C |
33959f88 | 1188 | #define PVR_POWER8 0x004D |
d3dbeef6 ME |
1189 | #define PVR_BE 0x0070 |
1190 | #define PVR_PA6T 0x0090 | |
9f04b9e3 | 1191 | |
388cc6e1 PM |
1192 | /* "Logical" PVR values defined in PAPR, representing architecture levels */ |
1193 | #define PVR_ARCH_204 0x0f000001 | |
1194 | #define PVR_ARCH_205 0x0f000002 | |
1195 | #define PVR_ARCH_206 0x0f000003 | |
1196 | #define PVR_ARCH_206p 0x0f100003 | |
1197 | #define PVR_ARCH_207 0x0f000004 | |
1198 | ||
14cf11af PM |
1199 | /* Macros for setting and retrieving special purpose registers */ |
1200 | #ifndef __ASSEMBLY__ | |
9f04b9e3 | 1201 | #define mfmsr() ({unsigned long rval; \ |
b416c9a1 TC |
1202 | asm volatile("mfmsr %0" : "=r" (rval) : \ |
1203 | : "memory"); rval;}) | |
0866eb99 | 1204 | #ifdef CONFIG_PPC_BOOK3S_64 |
9f04b9e3 | 1205 | #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ |
4c75f84f | 1206 | : : "r" (v) : "memory") |
1c539731 | 1207 | #define mtmsr(v) __mtmsrd((v), 0) |
611b0e5c | 1208 | #define __MTMSR "mtmsrd" |
9f04b9e3 | 1209 | #else |
326ed6a9 SW |
1210 | #define mtmsr(v) asm volatile("mtmsr %0" : \ |
1211 | : "r" ((unsigned long)(v)) \ | |
1212 | : "memory") | |
611b0e5c | 1213 | #define __MTMSR "mtmsr" |
9f04b9e3 | 1214 | #endif |
14cf11af | 1215 | |
611b0e5c AB |
1216 | static inline void mtmsr_isync(unsigned long val) |
1217 | { | |
1218 | asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : : | |
1219 | "r" (val), "i" (CPU_FTR_ARCH_206) : "memory"); | |
1220 | } | |
1221 | ||
9f04b9e3 | 1222 | #define mfspr(rn) ({unsigned long rval; \ |
14cf11af PM |
1223 | asm volatile("mfspr %0," __stringify(rn) \ |
1224 | : "=r" (rval)); rval;}) | |
1458dd95 | 1225 | #ifndef mtspr |
326ed6a9 SW |
1226 | #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ |
1227 | : "r" ((unsigned long)(v)) \ | |
2fae0a52 | 1228 | : "memory") |
1458dd95 | 1229 | #endif |
14cf11af | 1230 | |
3eb5d588 AB |
1231 | extern void msr_check_and_set(unsigned long bits); |
1232 | extern bool strict_msr_control; | |
1233 | extern void __msr_check_and_clear(unsigned long bits); | |
1234 | static inline void msr_check_and_clear(unsigned long bits) | |
1235 | { | |
1236 | if (strict_msr_control) | |
1237 | __msr_check_and_clear(bits); | |
1238 | } | |
1239 | ||
8f42ab27 AK |
1240 | static inline unsigned long mfvtb (void) |
1241 | { | |
1242 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1243 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1244 | return mfspr(SPRN_VTB); | |
1245 | #endif | |
1246 | return 0; | |
1247 | } | |
1248 | ||
859deea9 | 1249 | #ifdef __powerpc64__ |
d52459ca | 1250 | #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) |
859deea9 BH |
1251 | #define mftb() ({unsigned long rval; \ |
1252 | asm volatile( \ | |
beb2dc0a | 1253 | "90: mfspr %0, %2;\n" \ |
859deea9 BH |
1254 | "97: cmpwi %0,0;\n" \ |
1255 | " beq- 90b;\n" \ | |
1256 | "99:\n" \ | |
1257 | ".section __ftr_fixup,\"a\"\n" \ | |
1258 | ".align 3\n" \ | |
1259 | "98:\n" \ | |
1260 | " .llong %1\n" \ | |
1261 | " .llong %1\n" \ | |
1262 | " .llong 97b-98b\n" \ | |
1263 | " .llong 99b-98b\n" \ | |
fac23fe4 ME |
1264 | " .llong 0\n" \ |
1265 | " .llong 0\n" \ | |
859deea9 | 1266 | ".previous" \ |
beb2dc0a SW |
1267 | : "=r" (rval) \ |
1268 | : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL)); \ | |
1269 | rval;}) | |
859deea9 | 1270 | #else |
9f04b9e3 | 1271 | #define mftb() ({unsigned long rval; \ |
beb2dc0a SW |
1272 | asm volatile("mfspr %0, %1" : \ |
1273 | "=r" (rval) : "i" (SPRN_TBRL)); rval;}) | |
859deea9 BH |
1274 | #endif /* !CONFIG_PPC_CELL */ |
1275 | ||
1276 | #else /* __powerpc64__ */ | |
1277 | ||
ae2163be LC |
1278 | #if defined(CONFIG_8xx) |
1279 | #define mftbl() ({unsigned long rval; \ | |
1280 | asm volatile("mftbl %0" : "=r" (rval)); rval;}) | |
1281 | #define mftbu() ({unsigned long rval; \ | |
1282 | asm volatile("mftbu %0" : "=r" (rval)); rval;}) | |
1283 | #else | |
9f04b9e3 | 1284 | #define mftbl() ({unsigned long rval; \ |
beb2dc0a SW |
1285 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1286 | "i" (SPRN_TBRL)); rval;}) | |
859deea9 | 1287 | #define mftbu() ({unsigned long rval; \ |
beb2dc0a SW |
1288 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1289 | "i" (SPRN_TBRU)); rval;}) | |
ae2163be | 1290 | #endif |
859deea9 | 1291 | #endif /* !__powerpc64__ */ |
9f04b9e3 PM |
1292 | |
1293 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) | |
1294 | #define mttbu(v) asm volatile("mttbu %0":: "r"(v)) | |
1295 | ||
1296 | #ifdef CONFIG_PPC32 | |
14cf11af PM |
1297 | #define mfsrin(v) ({unsigned int rval; \ |
1298 | asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ | |
1299 | rval;}) | |
9f04b9e3 | 1300 | #endif |
14cf11af PM |
1301 | |
1302 | #define proc_trap() asm volatile("trap") | |
9f04b9e3 | 1303 | |
acf620ec | 1304 | extern unsigned long current_stack_pointer(void); |
4350147a BH |
1305 | |
1306 | extern unsigned long scom970_read(unsigned int address); | |
1307 | extern void scom970_write(unsigned int address, unsigned long value); | |
1308 | ||
322b4394 AV |
1309 | struct pt_regs; |
1310 | ||
1311 | extern void ppc_save_regs(struct pt_regs *regs); | |
1312 | ||
e63dbd16 GS |
1313 | static inline void update_power8_hid0(unsigned long hid0) |
1314 | { | |
1315 | /* | |
1316 | * The HID0 update on Power8 should at the very least be | |
1317 | * preceded by a a SYNC instruction followed by an ISYNC | |
1318 | * instruction | |
1319 | */ | |
1320 | asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0)); | |
1321 | } | |
14cf11af | 1322 | #endif /* __ASSEMBLY__ */ |
14cf11af | 1323 | #endif /* __KERNEL__ */ |
9f04b9e3 | 1324 | #endif /* _ASM_POWERPC_REG_H */ |