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powerpc: Add optional smp_ops->prepare_cpu SMP callback
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CommitLineData
1da177e4 1/*
5ad57078 2 * smp.h: PowerPC-specific SMP code.
1da177e4
LT
3 *
4 * Original was a copy of sparc smp.h. Now heavily modified
5 * for PPC.
6 *
7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
5ad57078
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16#ifndef _ASM_POWERPC_SMP_H
17#define _ASM_POWERPC_SMP_H
1da177e4 18#ifdef __KERNEL__
1da177e4 19
1da177e4
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20#include <linux/threads.h>
21#include <linux/cpumask.h>
22#include <linux/kernel.h>
23d72bfd 23#include <linux/irqreturn.h>
1da177e4
LT
24
25#ifndef __ASSEMBLY__
26
5ad57078 27#ifdef CONFIG_PPC64
1da177e4 28#include <asm/paca.h>
5ad57078 29#endif
d5a7430d 30#include <asm/percpu.h>
1da177e4
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31
32extern int boot_cpuid;
5be598a6 33extern int boot_hw_cpuid;
7ac87abb 34extern int spinning_secondaries;
1da177e4
LT
35
36extern void cpu_die(void);
3eb906c6 37extern int cpu_to_chip_id(int cpu);
1da177e4
LT
38
39#ifdef CONFIG_SMP
40
17f9c8a7
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41struct smp_ops_t {
42 void (*message_pass)(int cpu, int msg);
1ece355b 43#ifdef CONFIG_PPC_SMP_MUXED_IPI
e1221c6f 44 void (*cause_ipi)(int cpu);
1ece355b 45#endif
a7f4ee1f 46 void (*probe)(void);
17f9c8a7 47 int (*kick_cpu)(int nr);
7fca9518 48 int (*prepare_cpu)(int nr);
17f9c8a7
MM
49 void (*setup_cpu)(int nr);
50 void (*bringup_done)(void);
51 void (*take_timebase)(void);
52 void (*give_timebase)(void);
53 int (*cpu_disable)(void);
54 void (*cpu_die)(unsigned int nr);
55 int (*cpu_bootable)(unsigned int nr);
56};
57
e0476371 58extern void smp_send_debugger_break(void);
fa3f82c8 59extern void start_secondary_resume(void);
cad5cef6
GKH
60extern void smp_generic_give_timebase(void);
61extern void smp_generic_take_timebase(void);
1da177e4 62
6b7487fc 63DECLARE_PER_CPU(unsigned int, cpu_pvr);
1c21a293 64
1da177e4 65#ifdef CONFIG_HOTPLUG_CPU
1c91cc57 66extern void migrate_irqs(void);
1da177e4 67int generic_cpu_disable(void);
1da177e4 68void generic_cpu_die(unsigned int cpu);
105765f4 69void generic_set_cpu_dead(unsigned int cpu);
ae5cab47 70void generic_set_cpu_up(unsigned int cpu);
fb82b839 71int generic_check_cpu_restart(unsigned int cpu);
2f4f1f81 72int is_cpu_dead(unsigned int cpu);
73#else
74#define generic_set_cpu_up(i) do { } while (0)
1da177e4
LT
75#endif
76
5ad57078 77#ifdef CONFIG_PPC64
048c8bc9 78#define raw_smp_processor_id() (local_paca->paca_index)
1da177e4 79#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
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80#else
81/* 32-bit */
82extern int smp_hw_index[];
83
84#define raw_smp_processor_id() (current_thread_info()->cpu)
85#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
41eba0ad
BH
86
87static inline int get_hard_smp_processor_id(int cpu)
88{
89 return smp_hw_index[cpu];
90}
91
92static inline void set_hard_smp_processor_id(int cpu, int phys)
93{
94 smp_hw_index[cpu] = phys;
95}
5ad57078 96#endif
1da177e4 97
cc1ba8ea
AB
98DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
99DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
100
101static inline struct cpumask *cpu_sibling_mask(int cpu)
102{
103 return per_cpu(cpu_sibling_map, cpu);
104}
105
106static inline struct cpumask *cpu_core_mask(int cpu)
107{
108 return per_cpu(cpu_core_map, cpu);
109}
110
e9efed3b 111extern int cpu_to_core_id(int cpu);
1da177e4
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112
113/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
114 *
115 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
116 * in /proc/interrupts will be wrong!!! --Troy */
117#define PPC_MSG_CALL_FUNCTION 0
118#define PPC_MSG_RESCHEDULE 1
1b67bee1 119#define PPC_MSG_TICK_BROADCAST 2
1da177e4
LT
120#define PPC_MSG_DEBUGGER_BREAK 3
121
bd7f561f
SW
122/* This is only used by the powernv kernel */
123#define PPC_MSG_RM_HOST_ACTION 4
124
23d72bfd 125/* for irq controllers that have dedicated ipis per message (4) */
25ddd738
MM
126extern int smp_request_message_ipi(int virq, int message);
127extern const char *smp_ipi_name[];
128
23d72bfd 129/* for irq controllers with only a single ipi */
23d72bfd 130extern void smp_muxed_ipi_message_pass(int cpu, int msg);
31639c77 131extern void smp_muxed_ipi_set_message(int cpu, int msg);
23d72bfd 132extern irqreturn_t smp_ipi_demux(void);
42a6202f 133extern irqreturn_t smp_ipi_demux_relaxed(void);
23d72bfd 134
1da177e4 135void smp_init_pSeries(void);
19fe0475 136void smp_init_cell(void);
5ad57078 137void smp_setup_cpu_maps(void);
1da177e4
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138
139extern int __cpu_disable(void);
140extern void __cpu_die(unsigned int cpu);
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141
142#else
143/* for UP */
78b5b626 144#define hard_smp_processor_id() get_hard_smp_processor_id(0)
5ad57078 145#define smp_setup_cpu_maps()
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PM
146static inline void inhibit_secondary_onlining(void) {}
147static inline void uninhibit_secondary_onlining(void) {}
3be7db6a
RJ
148static inline const struct cpumask *cpu_sibling_mask(int cpu)
149{
150 return cpumask_of(cpu);
151}
5ad57078 152
1da177e4
LT
153#endif /* CONFIG_SMP */
154
5ad57078 155#ifdef CONFIG_PPC64
41eba0ad
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156static inline int get_hard_smp_processor_id(int cpu)
157{
158 return paca[cpu].hw_cpu_id;
159}
160
161static inline void set_hard_smp_processor_id(int cpu, int phys)
162{
163 paca[cpu].hw_cpu_id = phys;
164}
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165#else
166/* 32-bit */
167#ifndef CONFIG_SMP
4df20460 168extern int boot_cpuid_phys;
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169static inline int get_hard_smp_processor_id(int cpu)
170{
171 return boot_cpuid_phys;
172}
173
174static inline void set_hard_smp_processor_id(int cpu, int phys)
175{
78b5b626 176 boot_cpuid_phys = phys;
41eba0ad
BH
177}
178#endif /* !CONFIG_SMP */
179#endif /* !CONFIG_PPC64 */
1da177e4 180
da665885 181#if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE))
b1923caa
BH
182extern void smp_release_cpus(void);
183#else
184static inline void smp_release_cpus(void) { };
185#endif
186
1da177e4
LT
187extern int smt_enabled_at_boot;
188
a7f4ee1f 189extern void smp_mpic_probe(void);
1da177e4 190extern void smp_mpic_setup_cpu(int cpu);
de300974 191extern int smp_generic_kick_cpu(int nr);
3cd85250
AF
192extern int smp_generic_cpu_bootable(unsigned int nr);
193
1da177e4
LT
194
195extern void smp_generic_give_timebase(void);
196extern void smp_generic_take_timebase(void);
197
198extern struct smp_ops_t *smp_ops;
199
b7d7a240 200extern void arch_send_call_function_single_ipi(int cpu);
f063ea02 201extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
b7d7a240 202
cf54dc7c
BH
203/* Definitions relative to the secondary CPU spin loop
204 * and entry point. Not all of them exist on both 32 and
205 * 64-bit but defining them all here doesn't harm
206 */
207extern void generic_secondary_smp_init(void);
2d27cfd3 208extern void generic_secondary_thread_init(void);
cf54dc7c
BH
209extern unsigned long __secondary_hold_spinloop;
210extern unsigned long __secondary_hold_acknowledge;
211extern char __secondary_hold;
6becef7e 212extern unsigned int booting_thread_hwid;
cf54dc7c 213
d0832a75 214extern void __early_start(void);
1da177e4
LT
215#endif /* __ASSEMBLY__ */
216
1da177e4 217#endif /* __KERNEL__ */
5ad57078 218#endif /* _ASM_POWERPC_SMP_H) */