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Commit | Line | Data |
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1da177e4 | 1 | /* |
5ad57078 | 2 | * smp.h: PowerPC-specific SMP code. |
1da177e4 LT |
3 | * |
4 | * Original was a copy of sparc smp.h. Now heavily modified | |
5 | * for PPC. | |
6 | * | |
7 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
8 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
5ad57078 PM |
16 | #ifndef _ASM_POWERPC_SMP_H |
17 | #define _ASM_POWERPC_SMP_H | |
1da177e4 | 18 | #ifdef __KERNEL__ |
1da177e4 | 19 | |
1da177e4 LT |
20 | #include <linux/threads.h> |
21 | #include <linux/cpumask.h> | |
22 | #include <linux/kernel.h> | |
23d72bfd | 23 | #include <linux/irqreturn.h> |
1da177e4 LT |
24 | |
25 | #ifndef __ASSEMBLY__ | |
26 | ||
5ad57078 | 27 | #ifdef CONFIG_PPC64 |
1da177e4 | 28 | #include <asm/paca.h> |
5ad57078 | 29 | #endif |
d5a7430d | 30 | #include <asm/percpu.h> |
1da177e4 LT |
31 | |
32 | extern int boot_cpuid; | |
7ac87abb | 33 | extern int spinning_secondaries; |
1da177e4 LT |
34 | |
35 | extern void cpu_die(void); | |
3eb906c6 | 36 | extern int cpu_to_chip_id(int cpu); |
1da177e4 LT |
37 | |
38 | #ifdef CONFIG_SMP | |
39 | ||
17f9c8a7 MM |
40 | struct smp_ops_t { |
41 | void (*message_pass)(int cpu, int msg); | |
1ece355b | 42 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
b866cc21 | 43 | void (*cause_ipi)(int cpu); |
1ece355b | 44 | #endif |
c64af645 | 45 | int (*cause_nmi_ipi)(int cpu); |
a7f4ee1f | 46 | void (*probe)(void); |
17f9c8a7 | 47 | int (*kick_cpu)(int nr); |
14d4ae5c | 48 | int (*prepare_cpu)(int nr); |
17f9c8a7 MM |
49 | void (*setup_cpu)(int nr); |
50 | void (*bringup_done)(void); | |
51 | void (*take_timebase)(void); | |
52 | void (*give_timebase)(void); | |
53 | int (*cpu_disable)(void); | |
54 | void (*cpu_die)(unsigned int nr); | |
55 | int (*cpu_bootable)(unsigned int nr); | |
56 | }; | |
57 | ||
2104180a NP |
58 | extern void smp_flush_nmi_ipi(u64 delay_us); |
59 | extern int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us); | |
e0476371 | 60 | extern void smp_send_debugger_break(void); |
fa3f82c8 | 61 | extern void start_secondary_resume(void); |
cad5cef6 GKH |
62 | extern void smp_generic_give_timebase(void); |
63 | extern void smp_generic_take_timebase(void); | |
1da177e4 | 64 | |
6b7487fc | 65 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
1c21a293 | 66 | |
1da177e4 | 67 | #ifdef CONFIG_HOTPLUG_CPU |
1da177e4 | 68 | int generic_cpu_disable(void); |
1da177e4 | 69 | void generic_cpu_die(unsigned int cpu); |
105765f4 | 70 | void generic_set_cpu_dead(unsigned int cpu); |
ae5cab47 | 71 | void generic_set_cpu_up(unsigned int cpu); |
fb82b839 | 72 | int generic_check_cpu_restart(unsigned int cpu); |
2f4f1f81 | 73 | int is_cpu_dead(unsigned int cpu); |
74 | #else | |
75 | #define generic_set_cpu_up(i) do { } while (0) | |
1da177e4 LT |
76 | #endif |
77 | ||
5ad57078 | 78 | #ifdef CONFIG_PPC64 |
048c8bc9 | 79 | #define raw_smp_processor_id() (local_paca->paca_index) |
1da177e4 | 80 | #define hard_smp_processor_id() (get_paca()->hw_cpu_id) |
5ad57078 PM |
81 | #else |
82 | /* 32-bit */ | |
83 | extern int smp_hw_index[]; | |
84 | ||
85 | #define raw_smp_processor_id() (current_thread_info()->cpu) | |
86 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) | |
41eba0ad BH |
87 | |
88 | static inline int get_hard_smp_processor_id(int cpu) | |
89 | { | |
90 | return smp_hw_index[cpu]; | |
91 | } | |
92 | ||
93 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
94 | { | |
95 | smp_hw_index[cpu] = phys; | |
96 | } | |
5ad57078 | 97 | #endif |
1da177e4 | 98 | |
cc1ba8ea AB |
99 | DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
100 | DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); | |
101 | ||
102 | static inline struct cpumask *cpu_sibling_mask(int cpu) | |
103 | { | |
104 | return per_cpu(cpu_sibling_map, cpu); | |
105 | } | |
106 | ||
107 | static inline struct cpumask *cpu_core_mask(int cpu) | |
108 | { | |
109 | return per_cpu(cpu_core_map, cpu); | |
110 | } | |
111 | ||
e9efed3b | 112 | extern int cpu_to_core_id(int cpu); |
1da177e4 LT |
113 | |
114 | /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. | |
115 | * | |
116 | * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up | |
117 | * in /proc/interrupts will be wrong!!! --Troy */ | |
ddd703ca NP |
118 | #define PPC_MSG_CALL_FUNCTION 0 |
119 | #define PPC_MSG_RESCHEDULE 1 | |
1b67bee1 | 120 | #define PPC_MSG_TICK_BROADCAST 2 |
ddd703ca | 121 | #define PPC_MSG_NMI_IPI 3 |
1da177e4 | 122 | |
bd7f561f SW |
123 | /* This is only used by the powernv kernel */ |
124 | #define PPC_MSG_RM_HOST_ACTION 4 | |
125 | ||
ddd703ca NP |
126 | #define NMI_IPI_ALL_OTHERS -2 |
127 | ||
128 | #ifdef CONFIG_NMI_IPI | |
129 | extern int smp_handle_nmi_ipi(struct pt_regs *regs); | |
130 | #else | |
131 | static inline int smp_handle_nmi_ipi(struct pt_regs *regs) { return 0; } | |
132 | #endif | |
133 | ||
23d72bfd | 134 | /* for irq controllers that have dedicated ipis per message (4) */ |
25ddd738 MM |
135 | extern int smp_request_message_ipi(int virq, int message); |
136 | extern const char *smp_ipi_name[]; | |
137 | ||
23d72bfd | 138 | /* for irq controllers with only a single ipi */ |
23d72bfd | 139 | extern void smp_muxed_ipi_message_pass(int cpu, int msg); |
31639c77 | 140 | extern void smp_muxed_ipi_set_message(int cpu, int msg); |
23d72bfd | 141 | extern irqreturn_t smp_ipi_demux(void); |
b87ac021 | 142 | extern irqreturn_t smp_ipi_demux_relaxed(void); |
23d72bfd | 143 | |
1da177e4 | 144 | void smp_init_pSeries(void); |
19fe0475 | 145 | void smp_init_cell(void); |
5ad57078 | 146 | void smp_setup_cpu_maps(void); |
1da177e4 LT |
147 | |
148 | extern int __cpu_disable(void); | |
149 | extern void __cpu_die(unsigned int cpu); | |
5ad57078 PM |
150 | |
151 | #else | |
152 | /* for UP */ | |
78b5b626 | 153 | #define hard_smp_processor_id() get_hard_smp_processor_id(0) |
5ad57078 | 154 | #define smp_setup_cpu_maps() |
3cc33d50 PM |
155 | static inline void inhibit_secondary_onlining(void) {} |
156 | static inline void uninhibit_secondary_onlining(void) {} | |
3be7db6a RJ |
157 | static inline const struct cpumask *cpu_sibling_mask(int cpu) |
158 | { | |
159 | return cpumask_of(cpu); | |
160 | } | |
5ad57078 | 161 | |
1da177e4 LT |
162 | #endif /* CONFIG_SMP */ |
163 | ||
5ad57078 | 164 | #ifdef CONFIG_PPC64 |
41eba0ad BH |
165 | static inline int get_hard_smp_processor_id(int cpu) |
166 | { | |
167 | return paca[cpu].hw_cpu_id; | |
168 | } | |
169 | ||
170 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
171 | { | |
172 | paca[cpu].hw_cpu_id = phys; | |
173 | } | |
5ad57078 PM |
174 | #else |
175 | /* 32-bit */ | |
176 | #ifndef CONFIG_SMP | |
4df20460 | 177 | extern int boot_cpuid_phys; |
41eba0ad BH |
178 | static inline int get_hard_smp_processor_id(int cpu) |
179 | { | |
180 | return boot_cpuid_phys; | |
181 | } | |
182 | ||
183 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
184 | { | |
78b5b626 | 185 | boot_cpuid_phys = phys; |
41eba0ad BH |
186 | } |
187 | #endif /* !CONFIG_SMP */ | |
188 | #endif /* !CONFIG_PPC64 */ | |
1da177e4 | 189 | |
da665885 | 190 | #if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)) |
b1923caa BH |
191 | extern void smp_release_cpus(void); |
192 | #else | |
193 | static inline void smp_release_cpus(void) { }; | |
194 | #endif | |
195 | ||
1da177e4 LT |
196 | extern int smt_enabled_at_boot; |
197 | ||
a7f4ee1f | 198 | extern void smp_mpic_probe(void); |
1da177e4 | 199 | extern void smp_mpic_setup_cpu(int cpu); |
de300974 | 200 | extern int smp_generic_kick_cpu(int nr); |
3cd85250 AF |
201 | extern int smp_generic_cpu_bootable(unsigned int nr); |
202 | ||
1da177e4 LT |
203 | |
204 | extern void smp_generic_give_timebase(void); | |
205 | extern void smp_generic_take_timebase(void); | |
206 | ||
207 | extern struct smp_ops_t *smp_ops; | |
208 | ||
b7d7a240 | 209 | extern void arch_send_call_function_single_ipi(int cpu); |
f063ea02 | 210 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
b7d7a240 | 211 | |
cf54dc7c BH |
212 | /* Definitions relative to the secondary CPU spin loop |
213 | * and entry point. Not all of them exist on both 32 and | |
214 | * 64-bit but defining them all here doesn't harm | |
215 | */ | |
216 | extern void generic_secondary_smp_init(void); | |
2d27cfd3 | 217 | extern void generic_secondary_thread_init(void); |
cf54dc7c BH |
218 | extern unsigned long __secondary_hold_spinloop; |
219 | extern unsigned long __secondary_hold_acknowledge; | |
220 | extern char __secondary_hold; | |
6becef7e | 221 | extern unsigned int booting_thread_hwid; |
cf54dc7c | 222 | |
d0832a75 | 223 | extern void __early_start(void); |
1da177e4 LT |
224 | #endif /* __ASSEMBLY__ */ |
225 | ||
1da177e4 | 226 | #endif /* __KERNEL__ */ |
5ad57078 | 227 | #endif /* _ASM_POWERPC_SMP_H) */ |