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1970282f SR |
1 | #ifndef _ASM_POWERPC_TLBFLUSH_H |
2 | #define _ASM_POWERPC_TLBFLUSH_H | |
e701d269 | 3 | |
1970282f SR |
4 | /* |
5 | * TLB flushing: | |
6 | * | |
7 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's | |
8 | * - flush_tlb_page(vma, vmaddr) flushes one page | |
d4e167da | 9 | * - local_flush_tlb_mm(mm, full) flushes the specified mm context on |
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10 | * the local processor |
11 | * - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor | |
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12 | * - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB |
13 | * - flush_tlb_range(vma, start, end) flushes a range of pages | |
14 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages | |
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15 | * |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
20 | */ | |
21 | #ifdef __KERNEL__ | |
22 | ||
f048aace | 23 | #ifdef CONFIG_PPC_MMU_NOHASH |
62102307 DG |
24 | /* |
25 | * TLB flushing for software loaded TLB chips | |
26 | * | |
27 | * TODO: (CONFIG_FSL_BOOKE) determine if flush_tlb_range & | |
28 | * flush_tlb_kernel_range are best implemented as tlbia vs | |
29 | * specific tlbie's | |
30 | */ | |
31 | ||
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32 | struct vm_area_struct; |
33 | struct mm_struct; | |
e701d269 | 34 | |
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35 | #define MMU_NO_CONTEXT ((unsigned int)-1) |
36 | ||
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37 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
38 | unsigned long end); | |
39 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
62102307 | 40 | |
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41 | extern void local_flush_tlb_mm(struct mm_struct *mm); |
42 | extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
62102307 | 43 | |
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44 | extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, |
45 | int tsize, int ind); | |
46 | ||
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47 | #ifdef CONFIG_SMP |
48 | extern void flush_tlb_mm(struct mm_struct *mm); | |
49 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
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50 | extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, |
51 | int tsize, int ind); | |
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52 | #else |
53 | #define flush_tlb_mm(mm) local_flush_tlb_mm(mm) | |
54 | #define flush_tlb_page(vma,addr) local_flush_tlb_page(vma,addr) | |
d4e167da | 55 | #define __flush_tlb_page(mm,addr,p,i) __local_flush_tlb_page(mm,addr,p,i) |
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56 | #endif |
57 | #define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr) | |
62102307 | 58 | |
f048aace | 59 | #elif defined(CONFIG_PPC_STD_MMU_32) |
62102307 | 60 | |
62102307 | 61 | /* |
f048aace | 62 | * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx |
62102307 | 63 | */ |
62102307 DG |
64 | extern void flush_tlb_mm(struct mm_struct *mm); |
65 | extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); | |
66 | extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr); | |
67 | extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
68 | unsigned long end); | |
69 | extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); | |
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70 | static inline void local_flush_tlb_page(struct vm_area_struct *vma, |
71 | unsigned long vmaddr) | |
df3b8611 | 72 | { |
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73 | flush_tlb_page(vma, vmaddr); |
74 | } | |
75 | static inline void local_flush_tlb_mm(struct mm_struct *mm) | |
76 | { | |
77 | flush_tlb_mm(mm); | |
df3b8611 | 78 | } |
62102307 | 79 | |
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80 | #elif defined(CONFIG_PPC_STD_MMU_64) |
81 | ||
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82 | #define MMU_NO_CONTEXT 0 |
83 | ||
62102307 | 84 | /* |
f048aace | 85 | * TLB flushing for 64-bit hash-MMU CPUs |
62102307 | 86 | */ |
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87 | |
88 | #include <linux/percpu.h> | |
89 | #include <asm/page.h> | |
90 | ||
91 | #define PPC64_TLB_BATCH_NR 192 | |
92 | ||
93 | struct ppc64_tlb_batch { | |
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94 | int active; |
95 | unsigned long index; | |
96 | struct mm_struct *mm; | |
97 | real_pte_t pte[PPC64_TLB_BATCH_NR]; | |
5524a27d | 98 | unsigned long vpn[PPC64_TLB_BATCH_NR]; |
a741e679 | 99 | unsigned int psize; |
1189be65 | 100 | int ssize; |
1970282f SR |
101 | }; |
102 | DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); | |
103 | ||
104 | extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch); | |
105 | ||
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106 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE |
107 | ||
108 | static inline void arch_enter_lazy_mmu_mode(void) | |
109 | { | |
69111bac | 110 | struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch); |
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111 | |
112 | batch->active = 1; | |
113 | } | |
114 | ||
115 | static inline void arch_leave_lazy_mmu_mode(void) | |
1970282f | 116 | { |
69111bac | 117 | struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch); |
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118 | |
119 | if (batch->index) | |
120 | __flush_tlb_pending(batch); | |
a741e679 | 121 | batch->active = 0; |
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122 | } |
123 | ||
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124 | #define arch_flush_lazy_mmu_mode() do {} while (0) |
125 | ||
126 | ||
5524a27d | 127 | extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, |
1189be65 | 128 | int ssize, int local); |
3c726f8d | 129 | extern void flush_hash_range(unsigned long number, int local); |
f1581bf1 | 130 | extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr, |
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131 | pmd_t *pmdp, unsigned int psize, int ssize, |
132 | int local); | |
1970282f | 133 | |
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134 | static inline void local_flush_tlb_mm(struct mm_struct *mm) |
135 | { | |
136 | } | |
137 | ||
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138 | static inline void flush_tlb_mm(struct mm_struct *mm) |
139 | { | |
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140 | } |
141 | ||
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142 | static inline void local_flush_tlb_page(struct vm_area_struct *vma, |
143 | unsigned long vmaddr) | |
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144 | { |
145 | } | |
146 | ||
1970282f | 147 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
62102307 | 148 | unsigned long vmaddr) |
1970282f | 149 | { |
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150 | } |
151 | ||
152 | static inline void flush_tlb_page_nohash(struct vm_area_struct *vma, | |
153 | unsigned long vmaddr) | |
154 | { | |
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155 | } |
156 | ||
157 | static inline void flush_tlb_range(struct vm_area_struct *vma, | |
62102307 | 158 | unsigned long start, unsigned long end) |
1970282f | 159 | { |
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160 | } |
161 | ||
162 | static inline void flush_tlb_kernel_range(unsigned long start, | |
62102307 | 163 | unsigned long end) |
1970282f | 164 | { |
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165 | } |
166 | ||
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167 | /* Private function for use by PCI IO mapping code */ |
168 | extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start, | |
169 | unsigned long end); | |
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170 | extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, |
171 | unsigned long addr); | |
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172 | #else |
173 | #error Unsupported MMU type | |
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174 | #endif |
175 | ||
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176 | #endif /*__KERNEL__ */ |
177 | #endif /* _ASM_POWERPC_TLBFLUSH_H */ |