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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0b05ac6e | 2 | /* |
446957ba | 3 | * Common definitions across all variants of ICP and ICS interrupt |
0b05ac6e BH |
4 | * controllers. |
5 | */ | |
6 | ||
7 | #ifndef _XICS_H | |
8 | #define _XICS_H | |
9 | ||
cd852579 ME |
10 | #include <linux/interrupt.h> |
11 | ||
0b05ac6e BH |
12 | #define XICS_IPI 2 |
13 | #define XICS_IRQ_SPURIOUS 0 | |
14 | ||
15 | /* Want a priority other than 0. Various HW issues require this. */ | |
16 | #define DEFAULT_PRIORITY 5 | |
17 | ||
18 | /* | |
a3a9f3b4 YZ |
19 | * Mark IPIs as higher priority so we can take them inside interrupts |
20 | * FIXME: still true now? | |
0b05ac6e BH |
21 | */ |
22 | #define IPI_PRIORITY 4 | |
23 | ||
24 | /* The least favored priority */ | |
25 | #define LOWEST_PRIORITY 0xFF | |
26 | ||
27 | /* The number of priorities defined above */ | |
28 | #define MAX_NUM_PRIORITIES 3 | |
29 | ||
30 | /* Native ICP */ | |
5c7c1e94 | 31 | #ifdef CONFIG_PPC_ICP_NATIVE |
0b05ac6e | 32 | extern int icp_native_init(void); |
d6a4f709 | 33 | extern void icp_native_flush_interrupt(void); |
ec13e9b6 | 34 | extern void icp_native_cause_ipi_rm(int cpu); |
5c7c1e94 BH |
35 | #else |
36 | static inline int icp_native_init(void) { return -ENODEV; } | |
37 | #endif | |
0b05ac6e BH |
38 | |
39 | /* PAPR ICP */ | |
5c7c1e94 | 40 | #ifdef CONFIG_PPC_ICP_HV |
0b05ac6e | 41 | extern int icp_hv_init(void); |
5c7c1e94 BH |
42 | #else |
43 | static inline int icp_hv_init(void) { return -ENODEV; } | |
44 | #endif | |
0b05ac6e | 45 | |
d7436188 BH |
46 | #ifdef CONFIG_PPC_POWERNV |
47 | extern int icp_opal_init(void); | |
9b256714 | 48 | extern void icp_opal_flush_interrupt(void); |
d7436188 BH |
49 | #else |
50 | static inline int icp_opal_init(void) { return -ENODEV; } | |
51 | #endif | |
52 | ||
0b05ac6e BH |
53 | /* ICP ops */ |
54 | struct icp_ops { | |
55 | unsigned int (*get_irq)(void); | |
56 | void (*eoi)(struct irq_data *d); | |
57 | void (*set_priority)(unsigned char prio); | |
58 | void (*teardown_cpu)(void); | |
59 | void (*flush_ipi)(void); | |
60 | #ifdef CONFIG_SMP | |
b866cc21 | 61 | void (*cause_ipi)(int cpu); |
0b05ac6e BH |
62 | irq_handler_t ipi_action; |
63 | #endif | |
64 | }; | |
65 | ||
66 | extern const struct icp_ops *icp_ops; | |
67 | ||
68 | /* Native ICS */ | |
69 | extern int ics_native_init(void); | |
70 | ||
71 | /* RTAS ICS */ | |
5c7c1e94 | 72 | #ifdef CONFIG_PPC_ICS_RTAS |
0b05ac6e | 73 | extern int ics_rtas_init(void); |
5c7c1e94 BH |
74 | #else |
75 | static inline int ics_rtas_init(void) { return -ENODEV; } | |
76 | #endif | |
77 | ||
78 | /* HAL ICS */ | |
79 | #ifdef CONFIG_PPC_POWERNV | |
80 | extern int ics_opal_init(void); | |
81 | #else | |
82 | static inline int ics_opal_init(void) { return -ENODEV; } | |
83 | #endif | |
0b05ac6e BH |
84 | |
85 | /* ICS instance, hooked up to chip_data of an irq */ | |
86 | struct ics { | |
87 | struct list_head link; | |
88 | int (*map)(struct ics *ics, unsigned int virq); | |
89 | void (*mask_unknown)(struct ics *ics, unsigned long vec); | |
90 | long (*get_server)(struct ics *ics, unsigned long vec); | |
5ca12376 | 91 | int (*host_match)(struct ics *ics, struct device_node *node); |
0b05ac6e BH |
92 | char data[]; |
93 | }; | |
94 | ||
95 | /* Commons */ | |
96 | extern unsigned int xics_default_server; | |
97 | extern unsigned int xics_default_distrib_server; | |
98 | extern unsigned int xics_interrupt_server_size; | |
bae1d8f1 | 99 | extern struct irq_domain *xics_host; |
0b05ac6e BH |
100 | |
101 | struct xics_cppr { | |
102 | unsigned char stack[MAX_NUM_PRIORITIES]; | |
103 | int index; | |
104 | }; | |
105 | ||
106 | DECLARE_PER_CPU(struct xics_cppr, xics_cppr); | |
107 | ||
108 | static inline void xics_push_cppr(unsigned int vec) | |
109 | { | |
69111bac | 110 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
111 | |
112 | if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1)) | |
113 | return; | |
114 | ||
115 | if (vec == XICS_IPI) | |
116 | os_cppr->stack[++os_cppr->index] = IPI_PRIORITY; | |
117 | else | |
118 | os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY; | |
119 | } | |
120 | ||
121 | static inline unsigned char xics_pop_cppr(void) | |
122 | { | |
69111bac | 123 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
124 | |
125 | if (WARN_ON(os_cppr->index < 1)) | |
126 | return LOWEST_PRIORITY; | |
127 | ||
128 | return os_cppr->stack[--os_cppr->index]; | |
129 | } | |
130 | ||
131 | static inline void xics_set_base_cppr(unsigned char cppr) | |
132 | { | |
69111bac | 133 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
134 | |
135 | /* we only really want to set the priority when there's | |
136 | * just one cppr value on the stack | |
137 | */ | |
138 | WARN_ON(os_cppr->index != 0); | |
139 | ||
140 | os_cppr->stack[0] = cppr; | |
141 | } | |
142 | ||
143 | static inline unsigned char xics_cppr_top(void) | |
144 | { | |
69111bac | 145 | struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr); |
0b05ac6e BH |
146 | |
147 | return os_cppr->stack[os_cppr->index]; | |
148 | } | |
149 | ||
150 | DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message); | |
151 | ||
152 | extern void xics_init(void); | |
153 | extern void xics_setup_cpu(void); | |
154 | extern void xics_update_irq_servers(void); | |
155 | extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join); | |
156 | extern void xics_mask_unknown_vec(unsigned int vec); | |
157 | extern irqreturn_t xics_ipi_dispatch(int cpu); | |
a7f4ee1f | 158 | extern void xics_smp_probe(void); |
0b05ac6e BH |
159 | extern void xics_register_ics(struct ics *ics); |
160 | extern void xics_teardown_cpu(void); | |
161 | extern void xics_kexec_teardown_cpu(int secondary); | |
162 | extern void xics_migrate_irqs_away(void); | |
137436c9 | 163 | extern void icp_native_eoi(struct irq_data *d); |
880a3d6a BH |
164 | extern int xics_set_irq_type(struct irq_data *d, unsigned int flow_type); |
165 | extern int xics_retrigger(struct irq_data *data); | |
0b05ac6e BH |
166 | #ifdef CONFIG_SMP |
167 | extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |
168 | unsigned int strict_check); | |
169 | #else | |
170 | #define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server) | |
171 | #endif | |
172 | ||
173 | ||
174 | #endif /* _XICS_H */ |