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KVM: PPC: Book3S HV: Implement timebase offset for guests
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / include / uapi / asm / kvm.h
CommitLineData
bbf45ba5
HB		 1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
dd135ebb
CB		 20#ifndef __LINUX_KVM_POWERPC_H
21#define __LINUX_KVM_POWERPC_H
22
9f2cd967 23#include <linux/types.h>
bbf45ba5 24
54738c09
DG		 25/* Select powerpc specific features in <linux/kvm.h> */
26#define __KVM_HAVE_SPAPR_TCE
371fefd6 27#define __KVM_HAVE_PPC_SMT
de9ba2f3 28#define __KVM_HAVE_IRQCHIP
5efdb4be 29#define __KVM_HAVE_IRQ_LINE
54738c09 30
bbf45ba5
HB		 31struct kvm_regs {
32 __u64 pc;
33 __u64 cr;
34 __u64 ctr;
35 __u64 lr;
36 __u64 xer;
37 __u64 msr;
38 __u64 srr0;
39 __u64 srr1;
40 __u64 pid;
41
42 __u64 sprg0;
43 __u64 sprg1;
44 __u64 sprg2;
45 __u64 sprg3;
46 __u64 sprg4;
47 __u64 sprg5;
48 __u64 sprg6;
49 __u64 sprg7;
50
51 __u64 gpr[32];
52};
53
5ce941ee
SW		 54#define KVM_SREGS_E_IMPL_NONE 0
55#define KVM_SREGS_E_IMPL_FSL 1
56
57#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
58
59/*
60 * Feature bits indicate which sections of the sregs struct are valid,
61 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
62 * corresponding to unset feature bits will not be modified. This allows
63 * restoring a checkpoint made without that feature, while keeping the
64 * default values of the new registers.
65 *
66 * KVM_SREGS_E_BASE contains:
67 * CSRR0/1 (refers to SRR2/3 on 40x)
68 * ESR
69 * DEAR
70 * MCSR
71 * TSR
72 * TCR
73 * DEC
74 * TB
75 * VRSAVE (USPRG0)
76 */
77#define KVM_SREGS_E_BASE (1 << 0)
78
79/*
80 * KVM_SREGS_E_ARCH206 contains:
81 *
82 * PIR
83 * MCSRR0/1
84 * DECAR
85 * IVPR
86 */
87#define KVM_SREGS_E_ARCH206 (1 << 1)
88
89/*
90 * Contains EPCR, plus the upper half of 64-bit registers
91 * that are 32-bit on 32-bit implementations.
92 */
93#define KVM_SREGS_E_64 (1 << 2)
94
95#define KVM_SREGS_E_SPRG8 (1 << 3)
96#define KVM_SREGS_E_MCIVPR (1 << 4)
97
98/*
99 * IVORs are used -- contains IVOR0-15, plus additional IVORs
100 * in combination with an appropriate feature bit.
101 */
102#define KVM_SREGS_E_IVOR (1 << 5)
103
104/*
105 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
106 * Also TLBnPS if MMUCFG[MAVN] = 1.
107 */
108#define KVM_SREGS_E_ARCH206_MMU (1 << 6)
109
110/* DBSR, DBCR, IAC, DAC, DVC */
111#define KVM_SREGS_E_DEBUG (1 << 7)
112
113/* Enhanced debug -- DSRR0/1, SPRG9 */
114#define KVM_SREGS_E_ED (1 << 8)
115
116/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
117#define KVM_SREGS_E_SPE (1 << 9)
118
324b3e63
AG		 119/*
120 * DEPRECATED! USE ONE_REG FOR THIS ONE!
121 * External Proxy (EXP) -- EPR
122 */
5ce941ee
SW		 123#define KVM_SREGS_EXP (1 << 10)
124
125/* External PID (E.PD) -- EPSC/EPLC */
126#define KVM_SREGS_E_PD (1 << 11)
127
128/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
129#define KVM_SREGS_E_PC (1 << 12)
130
131/* Page table (E.PT) -- EPTCFG */
132#define KVM_SREGS_E_PT (1 << 13)
133
134/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
135#define KVM_SREGS_E_PM (1 << 14)
136
137/*
138 * Special updates:
139 *
140 * Some registers may change even while a vcpu is not running.
141 * To avoid losing these changes, by default these registers are
142 * not updated by KVM_SET_SREGS. To force an update, set the bit
143 * in u.e.update_special corresponding to the register to be updated.
144 *
145 * The update_special field is zero on return from KVM_GET_SREGS.
146 *
147 * When restoring a checkpoint, the caller can set update_special
148 * to 0xffffffff to ensure that everything is restored, even new features
149 * that the caller doesn't know about.
150 */
151#define KVM_SREGS_E_UPDATE_MCSR (1 << 0)
152#define KVM_SREGS_E_UPDATE_TSR (1 << 1)
153#define KVM_SREGS_E_UPDATE_DEC (1 << 2)
154#define KVM_SREGS_E_UPDATE_DBSR (1 << 3)
155
156/*
157 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
158 * previous KVM_GET_REGS.
159 *
160 * Unless otherwise indicated, setting any register with KVM_SET_SREGS
161 * directly sets its value. It does not trigger any special semantics such
162 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct
163 * just received from KVM_GET_SREGS is always a no-op.
164 */
bbf45ba5 165struct kvm_sregs {
ec3c11aa 166 __u32 pvr;
e15a1137
AG		 167 union {
168 struct {
169 __u64 sdr1;
170 struct {
171 struct {
172 __u64 slbe;
173 __u64 slbv;
174 } slb[64];
175 } ppc64;
176 struct {
177 __u32 sr[16];
da69dee0
AG		 178 __u64 ibat[8];
179 __u64 dbat[8];
e15a1137
AG		 180 } ppc32;
181 } s;
5ce941ee
SW		 182 struct {
183 union {
184 struct { /* KVM_SREGS_E_IMPL_FSL */
185 __u32 features; /* KVM_SREGS_E_FSL_ */
186 __u32 svr;
187 __u64 mcar;
188 __u32 hid0;
189
190 /* KVM_SREGS_E_FSL_PIDn */
191 __u32 pid1, pid2;
192 } fsl;
193 __u8 pad[256];
194 } impl;
195
196 __u32 features; /* KVM_SREGS_E_ */
197 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */
198 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */
199 __u32 pir; /* read-only */
200 __u64 sprg8;
201 __u64 sprg9; /* E.ED */
202 __u64 csrr0;
203 __u64 dsrr0; /* E.ED */
204 __u64 mcsrr0;
205 __u32 csrr1;
206 __u32 dsrr1; /* E.ED */
207 __u32 mcsrr1;
208 __u32 esr;
209 __u64 dear;
210 __u64 ivpr;
211 __u64 mcivpr;
212 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */
213
214 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */
215 __u32 tcr;
216 __u32 decar;
217 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */
218
219 /*
220 * Userspace can read TB directly, but the
221 * value reported here is consistent with "dec".
222 *
223 * Read-only.
224 */
225 __u64 tb;
226
227 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */
228 __u32 dbcr[3];
6df8d3fc
BB		 229 /*
230 * iac/dac registers are 64bit wide, while this API
231 * interface provides only lower 32 bits on 64 bit
232 * processors. ONE_REG interface is added for 64bit
233 * iac/dac registers.
234 */
5ce941ee
SW		 235 __u32 iac[4];
236 __u32 dac[2];
237 __u32 dvc[2];
238 __u8 num_iac; /* read-only */
239 __u8 num_dac; /* read-only */
240 __u8 num_dvc; /* read-only */
241 __u8 pad;
242
243 __u32 epr; /* EXP */
244 __u32 vrsave; /* a.k.a. USPRG0 */
245 __u32 epcr; /* KVM_SREGS_E_64 */
246
247 __u32 mas0;
248 __u32 mas1;
249 __u64 mas2;
250 __u64 mas7_3;
251 __u32 mas4;
252 __u32 mas6;
253
254 __u32 ivor_low[16]; /* IVOR0-15 */
255 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */
256
257 __u32 mmucfg; /* read-only */
258 __u32 eptcfg; /* E.PT, read-only */
259 __u32 tlbcfg[4];/* read-only */
260 __u32 tlbps[4]; /* read-only */
261
262 __u32 eplc, epsc; /* E.PD */
263 } e;
e15a1137
AG		 264 __u8 pad[1020];
265 } u;
bbf45ba5
HB		 266};
267
268struct kvm_fpu {
269 __u64 fpr[32];
270};
dd135ebb 271
d0bfb940
JK		 272struct kvm_debug_exit_arch {
273};
274
275/* for KVM_SET_GUEST_DEBUG */
276struct kvm_guest_debug_arch {
092d62ee
BB		 277 struct {
278 /* H/W breakpoint/watchpoint address */
279 __u64 addr;
280 /*
281 * Type denotes h/w breakpoint, read watchpoint, write
282 * watchpoint or watchpoint (both read and write).
283 */
284#define KVMPPC_DEBUG_NONE 0x0
285#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
286#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
287#define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
288 __u32 type;
289 __u32 reserved;
290 } bp[16];
d0bfb940
JK		 291};
292
092d62ee
BB		 293/* Debug related defines */
294/*
295 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
296 * and upper 16 bits are architecture specific. Architecture specific defines
297 * that ioctl is for setting hardware breakpoint or software breakpoint.
298 */
299#define KVM_GUESTDBG_USE_SW_BP 0x00010000
300#define KVM_GUESTDBG_USE_HW_BP 0x00020000
301
b9e5dc8d
CB		 302/* definition of registers in kvm_run */
303struct kvm_sync_regs {
304};
305
18978768
AG		 306#define KVM_INTERRUPT_SET -1U
307#define KVM_INTERRUPT_UNSET -2U
17bd1580 308#define KVM_INTERRUPT_SET_LEVEL -3U
18978768 309
af8f38b3
AG		 310#define KVM_CPU_440 1
311#define KVM_CPU_E500V2 2
312#define KVM_CPU_3S_32 3
313#define KVM_CPU_3S_64 4
73196cd3 314#define KVM_CPU_E500MC 5
af8f38b3 315
54738c09
DG		 316/* for KVM_CAP_SPAPR_TCE */
317struct kvm_create_spapr_tce {
318 __u64 liobn;
319 __u32 window_size;
320};
321
aa04b4cc
PM		 322/* for KVM_ALLOCATE_RMA */
323struct kvm_allocate_rma {
324 __u64 rma_size;
325};
326
8e591cb7
ME		 327/* for KVM_CAP_PPC_RTAS */
328struct kvm_rtas_token_args {
329 char name[120];
330 __u64 token; /* Use a token of 0 to undefine a mapping */
331};
332
dc83b8bc
SW		 333struct kvm_book3e_206_tlb_entry {
334 __u32 mas8;
335 __u32 mas1;
336 __u64 mas2;
337 __u64 mas7_3;
338};
339
340struct kvm_book3e_206_tlb_params {
341 /*
342 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
343 *
344 * - The number of ways of TLB0 must be a power of two between 2 and
345 * 16.
346 * - TLB1 must be fully associative.
347 * - The size of TLB0 must be a multiple of the number of ways, and
348 * the number of sets must be a power of two.
349 * - The size of TLB1 may not exceed 64 entries.
350 * - TLB0 supports 4 KiB pages.
351 * - The page sizes supported by TLB1 are as indicated by
352 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
353 * as returned by KVM_GET_SREGS.
354 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
355 * and tlb_ways[] must be zero.
356 *
357 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
358 *
359 * KVM will adjust TLBnCFG based on the sizes configured here,
360 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
361 * set to zero.
362 */
363 __u32 tlb_sizes[4];
364 __u32 tlb_ways[4];
365 __u32 reserved[8];
366};
367
a2932923
PM		 368/* For KVM_PPC_GET_HTAB_FD */
369struct kvm_get_htab_fd {
370 __u64 flags;
371 __u64 start_index;
372 __u64 reserved[2];
373};
374
375/* Values for kvm_get_htab_fd.flags */
376#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1)
377#define KVM_GET_HTAB_WRITE ((__u64)0x2)
378
379/*
380 * Data read on the file descriptor is formatted as a series of
381 * records, each consisting of a header followed by a series of
382 * `n_valid' HPTEs (16 bytes each), which are all valid. Following
383 * those valid HPTEs there are `n_invalid' invalid HPTEs, which
384 * are not represented explicitly in the stream. The same format
385 * is used for writing.
386 */
387struct kvm_get_htab_header {
388 __u32 index;
389 __u16 n_valid;
390 __u16 n_invalid;
391};
392
8b78645c
PM		 393/* Per-vcpu XICS interrupt controller state */
394#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
395
396#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
397#define KVM_REG_PPC_ICP_CPPR_MASK 0xff
398#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
399#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
400#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
401#define KVM_REG_PPC_ICP_MFRR_MASK 0xff
402#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
403#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
404
5df554ad
SW		 405/* Device control API: PPC-specific devices */
406#define KVM_DEV_MPIC_GRP_MISC 1
407#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
408
409#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
410#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
411
412/* One-Reg API: PPC-specific registers */
1022fc3d 413#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
6df8d3fc
BB		 414#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
415#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
416#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
417#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
418#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
419#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
a136a8bd
PM		 420#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
421#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
422#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
423#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
424#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
425#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
426#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
427#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
428
429#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
430#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
431#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
3b783474
MN		 432#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
433#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
434#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
435#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
436#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
a136a8bd
PM		 437
438#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
439#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
440#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
441#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
442#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
443#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
444#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
445#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
1022fc3d 446
a8bd19ef
PM		 447/* 32 floating-point registers */
448#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
449#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n))
450#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
451
452/* 32 VMX/Altivec vector registers */
453#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
454#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n))
455#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
456
457/* 32 double-width FP registers for VSX */
458/* High-order halves overlap with FP regs */
459#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
460#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n))
461#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
462
463/* FP and vector status/control registers */
464#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
465#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
466
55b665b0
PM		 467/* Virtual processor areas */
468/* For SLB & DTL, address in high (first) half, length in low half */
469#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
470#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
471#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
472
352df1de 473#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
324b3e63 474#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
352df1de 475
78accda4
BB		 476/* Timer Status Register OR/CLEAR interface */
477#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
478#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
479#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
480#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
8c32a2ea
BB		 481
482/* Debugging: Special instruction for software breakpoint */
483#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
484
a85d2aa2
MC		 485/* MMU registers */
486#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
487#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
488#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
489#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
490#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
491#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
492#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
493/*
494 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
495 * KVM_CAP_SW_TLB ioctl
496 */
497#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
498#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
499#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
500#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
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MC		 501#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
502#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
503#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
504#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
9a6061d7 505#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
a85d2aa2 506
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PM		 507/* Timebase offset */
508#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c)
509
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MN		 510/* POWER8 registers */
511#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
512#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
513#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
514#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
515#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
516#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
517#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
518#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
519#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
520#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
521#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
522#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
523#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
524#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
525#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
526#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
527#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
528#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
529#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
530#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
531#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
532#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
533#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
534
535/* Transactional Memory checkpointed state:
536 * This is all GPRs, all VSX regs and a subset of SPRs
537 */
538#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000)
539/* TM GPRs */
540#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
541#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n))
542#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
543/* TM VSX */
544#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
545#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n))
546#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
547/* TM SPRS */
548#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
549#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
550#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
551#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
552#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
553#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
554#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
555#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
556#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
557#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
558
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PM		 559/* PPC64 eXternal Interrupt Controller Specification */
560#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
561
562/* Layout of 64-bit source attribute values */
563#define KVM_XICS_DESTINATION_SHIFT 0
564#define KVM_XICS_DESTINATION_MASK 0xffffffffULL
565#define KVM_XICS_PRIORITY_SHIFT 32
566#define KVM_XICS_PRIORITY_MASK 0xff
567#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
568#define KVM_XICS_MASKED (1ULL << 41)
569#define KVM_XICS_PENDING (1ULL << 42)
570
bbf45ba5 571#endif /* __LINUX_KVM_POWERPC_H */
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