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1da177e4 LT |
1 | /* align.c - handle alignment exceptions for the Power PC. |
2 | * | |
3 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
4 | * Copyright (c) 1998-1999 TiVo, Inc. | |
5 | * PowerPC 403GCX modifications. | |
6 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
7 | * PowerPC 403GCX/405GP modifications. | |
8 | * Copyright (c) 2001-2002 PPC64 team, IBM Corp | |
9 | * 64-bit and Power4 support | |
5daf9071 BH |
10 | * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp |
11 | * <benh@kernel.crashing.org> | |
12 | * Merge ppc32 and ppc64 implementations | |
1da177e4 LT |
13 | * |
14 | * This program is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License | |
16 | * as published by the Free Software Foundation; either version | |
17 | * 2 of the License, or (at your option) any later version. | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/mm.h> | |
22 | #include <asm/processor.h> | |
7c0f6ba6 | 23 | #include <linux/uaccess.h> |
1da177e4 LT |
24 | #include <asm/cache.h> |
25 | #include <asm/cputable.h> | |
80947e7c | 26 | #include <asm/emulated_ops.h> |
ae3a197e | 27 | #include <asm/switch_to.h> |
ddca156a | 28 | #include <asm/disassemble.h> |
b92a226e | 29 | #include <asm/cpu_has_feature.h> |
1da177e4 LT |
30 | |
31 | struct aligninfo { | |
32 | unsigned char len; | |
33 | unsigned char flags; | |
34 | }; | |
35 | ||
1da177e4 LT |
36 | |
37 | #define INVALID { 0, 0 } | |
38 | ||
fab5db97 PM |
39 | /* Bits in the flags field */ |
40 | #define LD 0 /* load */ | |
41 | #define ST 1 /* store */ | |
c6d4267e | 42 | #define SE 2 /* sign-extend value, or FP ld/st as word */ |
fab5db97 PM |
43 | #define F 4 /* to/from fp regs */ |
44 | #define U 8 /* update index register */ | |
45 | #define M 0x10 /* multiple load/store */ | |
46 | #define SW 0x20 /* byte swap */ | |
47 | #define S 0x40 /* single-precision fp or... */ | |
48 | #define SX 0x40 /* ... byte count in XER */ | |
5daf9071 | 49 | #define HARD 0x80 /* string, stwcx. */ |
26caeb2e KG |
50 | #define E4 0x40 /* SPE endianness is word */ |
51 | #define E8 0x80 /* SPE endianness is double word */ | |
cd6f37be | 52 | #define SPLT 0x80 /* VSX SPLAT load */ |
1da177e4 | 53 | |
fab5db97 | 54 | /* DSISR bits reported for a DCBZ instruction: */ |
1da177e4 LT |
55 | #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */ |
56 | ||
57 | /* | |
58 | * The PowerPC stores certain bits of the instruction that caused the | |
59 | * alignment exception in the DSISR register. This array maps those | |
60 | * bits to information about the operand length and what the | |
61 | * instruction would do. | |
62 | */ | |
63 | static struct aligninfo aligninfo[128] = { | |
64 | { 4, LD }, /* 00 0 0000: lwz / lwarx */ | |
65 | INVALID, /* 00 0 0001 */ | |
66 | { 4, ST }, /* 00 0 0010: stw */ | |
67 | INVALID, /* 00 0 0011 */ | |
68 | { 2, LD }, /* 00 0 0100: lhz */ | |
69 | { 2, LD+SE }, /* 00 0 0101: lha */ | |
70 | { 2, ST }, /* 00 0 0110: sth */ | |
71 | { 4, LD+M }, /* 00 0 0111: lmw */ | |
5daf9071 | 72 | { 4, LD+F+S }, /* 00 0 1000: lfs */ |
1da177e4 | 73 | { 8, LD+F }, /* 00 0 1001: lfd */ |
5daf9071 | 74 | { 4, ST+F+S }, /* 00 0 1010: stfs */ |
1da177e4 | 75 | { 8, ST+F }, /* 00 0 1011: stfd */ |
f83319d7 | 76 | { 16, LD }, /* 00 0 1100: lq */ |
5daf9071 | 77 | { 8, LD }, /* 00 0 1101: ld/ldu/lwa */ |
1da177e4 | 78 | INVALID, /* 00 0 1110 */ |
5daf9071 | 79 | { 8, ST }, /* 00 0 1111: std/stdu */ |
1da177e4 LT |
80 | { 4, LD+U }, /* 00 1 0000: lwzu */ |
81 | INVALID, /* 00 1 0001 */ | |
82 | { 4, ST+U }, /* 00 1 0010: stwu */ | |
83 | INVALID, /* 00 1 0011 */ | |
84 | { 2, LD+U }, /* 00 1 0100: lhzu */ | |
85 | { 2, LD+SE+U }, /* 00 1 0101: lhau */ | |
86 | { 2, ST+U }, /* 00 1 0110: sthu */ | |
87 | { 4, ST+M }, /* 00 1 0111: stmw */ | |
5daf9071 | 88 | { 4, LD+F+S+U }, /* 00 1 1000: lfsu */ |
1da177e4 | 89 | { 8, LD+F+U }, /* 00 1 1001: lfdu */ |
5daf9071 | 90 | { 4, ST+F+S+U }, /* 00 1 1010: stfsu */ |
1da177e4 | 91 | { 8, ST+F+U }, /* 00 1 1011: stfdu */ |
c6d4267e | 92 | { 16, LD+F }, /* 00 1 1100: lfdp */ |
1da177e4 | 93 | INVALID, /* 00 1 1101 */ |
c6d4267e | 94 | { 16, ST+F }, /* 00 1 1110: stfdp */ |
1da177e4 LT |
95 | INVALID, /* 00 1 1111 */ |
96 | { 8, LD }, /* 01 0 0000: ldx */ | |
97 | INVALID, /* 01 0 0001 */ | |
98 | { 8, ST }, /* 01 0 0010: stdx */ | |
99 | INVALID, /* 01 0 0011 */ | |
100 | INVALID, /* 01 0 0100 */ | |
101 | { 4, LD+SE }, /* 01 0 0101: lwax */ | |
102 | INVALID, /* 01 0 0110 */ | |
103 | INVALID, /* 01 0 0111 */ | |
5daf9071 BH |
104 | { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */ |
105 | { 4, LD+M+HARD }, /* 01 0 1001: lswi */ | |
106 | { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */ | |
107 | { 4, ST+M+HARD }, /* 01 0 1011: stswi */ | |
1da177e4 LT |
108 | INVALID, /* 01 0 1100 */ |
109 | { 8, LD+U }, /* 01 0 1101: ldu */ | |
110 | INVALID, /* 01 0 1110 */ | |
111 | { 8, ST+U }, /* 01 0 1111: stdu */ | |
112 | { 8, LD+U }, /* 01 1 0000: ldux */ | |
113 | INVALID, /* 01 1 0001 */ | |
114 | { 8, ST+U }, /* 01 1 0010: stdux */ | |
115 | INVALID, /* 01 1 0011 */ | |
116 | INVALID, /* 01 1 0100 */ | |
117 | { 4, LD+SE+U }, /* 01 1 0101: lwaux */ | |
118 | INVALID, /* 01 1 0110 */ | |
119 | INVALID, /* 01 1 0111 */ | |
120 | INVALID, /* 01 1 1000 */ | |
121 | INVALID, /* 01 1 1001 */ | |
122 | INVALID, /* 01 1 1010 */ | |
123 | INVALID, /* 01 1 1011 */ | |
124 | INVALID, /* 01 1 1100 */ | |
125 | INVALID, /* 01 1 1101 */ | |
126 | INVALID, /* 01 1 1110 */ | |
127 | INVALID, /* 01 1 1111 */ | |
128 | INVALID, /* 10 0 0000 */ | |
129 | INVALID, /* 10 0 0001 */ | |
5daf9071 | 130 | INVALID, /* 10 0 0010: stwcx. */ |
1da177e4 LT |
131 | INVALID, /* 10 0 0011 */ |
132 | INVALID, /* 10 0 0100 */ | |
133 | INVALID, /* 10 0 0101 */ | |
134 | INVALID, /* 10 0 0110 */ | |
135 | INVALID, /* 10 0 0111 */ | |
136 | { 4, LD+SW }, /* 10 0 1000: lwbrx */ | |
137 | INVALID, /* 10 0 1001 */ | |
138 | { 4, ST+SW }, /* 10 0 1010: stwbrx */ | |
139 | INVALID, /* 10 0 1011 */ | |
140 | { 2, LD+SW }, /* 10 0 1100: lhbrx */ | |
141 | { 4, LD+SE }, /* 10 0 1101 lwa */ | |
142 | { 2, ST+SW }, /* 10 0 1110: sthbrx */ | |
f83319d7 | 143 | { 16, ST }, /* 10 0 1111: stq */ |
1da177e4 LT |
144 | INVALID, /* 10 1 0000 */ |
145 | INVALID, /* 10 1 0001 */ | |
146 | INVALID, /* 10 1 0010 */ | |
147 | INVALID, /* 10 1 0011 */ | |
148 | INVALID, /* 10 1 0100 */ | |
149 | INVALID, /* 10 1 0101 */ | |
150 | INVALID, /* 10 1 0110 */ | |
151 | INVALID, /* 10 1 0111 */ | |
152 | INVALID, /* 10 1 1000 */ | |
153 | INVALID, /* 10 1 1001 */ | |
154 | INVALID, /* 10 1 1010 */ | |
155 | INVALID, /* 10 1 1011 */ | |
156 | INVALID, /* 10 1 1100 */ | |
157 | INVALID, /* 10 1 1101 */ | |
158 | INVALID, /* 10 1 1110 */ | |
5daf9071 | 159 | { 0, ST+HARD }, /* 10 1 1111: dcbz */ |
1da177e4 LT |
160 | { 4, LD }, /* 11 0 0000: lwzx */ |
161 | INVALID, /* 11 0 0001 */ | |
162 | { 4, ST }, /* 11 0 0010: stwx */ | |
163 | INVALID, /* 11 0 0011 */ | |
164 | { 2, LD }, /* 11 0 0100: lhzx */ | |
165 | { 2, LD+SE }, /* 11 0 0101: lhax */ | |
166 | { 2, ST }, /* 11 0 0110: sthx */ | |
167 | INVALID, /* 11 0 0111 */ | |
5daf9071 | 168 | { 4, LD+F+S }, /* 11 0 1000: lfsx */ |
1da177e4 | 169 | { 8, LD+F }, /* 11 0 1001: lfdx */ |
5daf9071 | 170 | { 4, ST+F+S }, /* 11 0 1010: stfsx */ |
1da177e4 | 171 | { 8, ST+F }, /* 11 0 1011: stfdx */ |
c6d4267e PM |
172 | { 16, LD+F }, /* 11 0 1100: lfdpx */ |
173 | { 4, LD+F+SE }, /* 11 0 1101: lfiwax */ | |
174 | { 16, ST+F }, /* 11 0 1110: stfdpx */ | |
175 | { 4, ST+F }, /* 11 0 1111: stfiwx */ | |
1da177e4 LT |
176 | { 4, LD+U }, /* 11 1 0000: lwzux */ |
177 | INVALID, /* 11 1 0001 */ | |
178 | { 4, ST+U }, /* 11 1 0010: stwux */ | |
179 | INVALID, /* 11 1 0011 */ | |
180 | { 2, LD+U }, /* 11 1 0100: lhzux */ | |
181 | { 2, LD+SE+U }, /* 11 1 0101: lhaux */ | |
182 | { 2, ST+U }, /* 11 1 0110: sthux */ | |
183 | INVALID, /* 11 1 0111 */ | |
5daf9071 | 184 | { 4, LD+F+S+U }, /* 11 1 1000: lfsux */ |
1da177e4 | 185 | { 8, LD+F+U }, /* 11 1 1001: lfdux */ |
5daf9071 | 186 | { 4, ST+F+S+U }, /* 11 1 1010: stfsux */ |
1da177e4 LT |
187 | { 8, ST+F+U }, /* 11 1 1011: stfdux */ |
188 | INVALID, /* 11 1 1100 */ | |
545bba18 | 189 | { 4, LD+F }, /* 11 1 1101: lfiwzx */ |
1da177e4 LT |
190 | INVALID, /* 11 1 1110 */ |
191 | INVALID, /* 11 1 1111 */ | |
192 | }; | |
193 | ||
5daf9071 BH |
194 | /* |
195 | * The dcbz (data cache block zero) instruction | |
196 | * gives an alignment fault if used on non-cacheable | |
197 | * memory. We handle the fault mainly for the | |
198 | * case when we are running with the cache disabled | |
199 | * for debugging. | |
200 | */ | |
201 | static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr) | |
202 | { | |
203 | long __user *p; | |
204 | int i, size; | |
205 | ||
206 | #ifdef __powerpc64__ | |
e2827fe5 | 207 | size = ppc64_caches.l1d.block_size; |
5daf9071 BH |
208 | #else |
209 | size = L1_CACHE_BYTES; | |
210 | #endif | |
211 | p = (long __user *) (regs->dar & -size); | |
212 | if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size)) | |
213 | return -EFAULT; | |
214 | for (i = 0; i < size / sizeof(long); ++i) | |
e4ee3891 | 215 | if (__put_user_inatomic(0, p+i)) |
5daf9071 BH |
216 | return -EFAULT; |
217 | return 1; | |
218 | } | |
219 | ||
220 | /* | |
221 | * Emulate load & store multiple instructions | |
222 | * On 64-bit machines, these instructions only affect/use the | |
223 | * bottom 4 bytes of each register, and the loads clear the | |
224 | * top 4 bytes of the affected register. | |
225 | */ | |
075f6311 | 226 | #ifdef __BIG_ENDIAN__ |
5daf9071 BH |
227 | #ifdef CONFIG_PPC64 |
228 | #define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4) | |
229 | #else | |
230 | #define REG_BYTE(rp, i) *((u8 *)(rp) + (i)) | |
231 | #endif | |
a9650e9b | 232 | #else |
075f6311 TM |
233 | #define REG_BYTE(rp, i) (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3)))) |
234 | #endif | |
5daf9071 | 235 | |
fab5db97 PM |
236 | #define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz)) |
237 | ||
5daf9071 BH |
238 | static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr, |
239 | unsigned int reg, unsigned int nb, | |
fab5db97 PM |
240 | unsigned int flags, unsigned int instr, |
241 | unsigned long swiz) | |
5daf9071 BH |
242 | { |
243 | unsigned long *rptr; | |
fab5db97 PM |
244 | unsigned int nb0, i, bswiz; |
245 | unsigned long p; | |
5daf9071 BH |
246 | |
247 | /* | |
248 | * We do not try to emulate 8 bytes multiple as they aren't really | |
249 | * available in our operating environments and we don't try to | |
250 | * emulate multiples operations in kernel land as they should never | |
251 | * be used/generated there at least not on unaligned boundaries | |
252 | */ | |
253 | if (unlikely((nb > 4) || !user_mode(regs))) | |
254 | return 0; | |
255 | ||
256 | /* lmw, stmw, lswi/x, stswi/x */ | |
257 | nb0 = 0; | |
258 | if (flags & HARD) { | |
259 | if (flags & SX) { | |
260 | nb = regs->xer & 127; | |
261 | if (nb == 0) | |
262 | return 1; | |
263 | } else { | |
fab5db97 PM |
264 | unsigned long pc = regs->nip ^ (swiz & 4); |
265 | ||
e4ee3891 BH |
266 | if (__get_user_inatomic(instr, |
267 | (unsigned int __user *)pc)) | |
5daf9071 | 268 | return -EFAULT; |
fab5db97 PM |
269 | if (swiz == 0 && (flags & SW)) |
270 | instr = cpu_to_le32(instr); | |
5daf9071 BH |
271 | nb = (instr >> 11) & 0x1f; |
272 | if (nb == 0) | |
273 | nb = 32; | |
1da177e4 | 274 | } |
5daf9071 BH |
275 | if (nb + reg * 4 > 128) { |
276 | nb0 = nb + reg * 4 - 128; | |
277 | nb = 128 - reg * 4; | |
278 | } | |
075f6311 TM |
279 | #ifdef __LITTLE_ENDIAN__ |
280 | /* | |
281 | * String instructions are endian neutral but the code | |
282 | * below is not. Force byte swapping on so that the | |
283 | * effects of swizzling are undone in the load/store | |
284 | * loops below. | |
285 | */ | |
286 | flags ^= SW; | |
287 | #endif | |
5daf9071 BH |
288 | } else { |
289 | /* lwm, stmw */ | |
290 | nb = (32 - reg) * 4; | |
1da177e4 | 291 | } |
5daf9071 BH |
292 | |
293 | if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0)) | |
294 | return -EFAULT; /* bad address */ | |
295 | ||
296 | rptr = ®s->gpr[reg]; | |
fab5db97 PM |
297 | p = (unsigned long) addr; |
298 | bswiz = (flags & SW)? 3: 0; | |
299 | ||
300 | if (!(flags & ST)) { | |
5daf9071 BH |
301 | /* |
302 | * This zeroes the top 4 bytes of the affected registers | |
303 | * in 64-bit mode, and also zeroes out any remaining | |
304 | * bytes of the last register for lsw*. | |
305 | */ | |
306 | memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long)); | |
307 | if (nb0 > 0) | |
308 | memset(®s->gpr[0], 0, | |
309 | ((nb0 + 3) / 4) * sizeof(unsigned long)); | |
310 | ||
fab5db97 | 311 | for (i = 0; i < nb; ++i, ++p) |
e4ee3891 BH |
312 | if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz), |
313 | SWIZ_PTR(p))) | |
5daf9071 BH |
314 | return -EFAULT; |
315 | if (nb0 > 0) { | |
316 | rptr = ®s->gpr[0]; | |
317 | addr += nb; | |
fab5db97 | 318 | for (i = 0; i < nb0; ++i, ++p) |
e4ee3891 BH |
319 | if (__get_user_inatomic(REG_BYTE(rptr, |
320 | i ^ bswiz), | |
321 | SWIZ_PTR(p))) | |
5daf9071 BH |
322 | return -EFAULT; |
323 | } | |
324 | ||
325 | } else { | |
fab5db97 | 326 | for (i = 0; i < nb; ++i, ++p) |
e4ee3891 BH |
327 | if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz), |
328 | SWIZ_PTR(p))) | |
5daf9071 BH |
329 | return -EFAULT; |
330 | if (nb0 > 0) { | |
331 | rptr = ®s->gpr[0]; | |
332 | addr += nb; | |
fab5db97 | 333 | for (i = 0; i < nb0; ++i, ++p) |
e4ee3891 BH |
334 | if (__put_user_inatomic(REG_BYTE(rptr, |
335 | i ^ bswiz), | |
336 | SWIZ_PTR(p))) | |
5daf9071 BH |
337 | return -EFAULT; |
338 | } | |
339 | } | |
340 | return 1; | |
1da177e4 LT |
341 | } |
342 | ||
c6d4267e PM |
343 | /* |
344 | * Emulate floating-point pair loads and stores. | |
345 | * Only POWER6 has these instructions, and it does true little-endian, | |
346 | * so we don't need the address swizzling. | |
347 | */ | |
b887ec62 MN |
348 | static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg, |
349 | unsigned int flags) | |
c6d4267e | 350 | { |
553631e2 MN |
351 | char *ptr0 = (char *) ¤t->thread.TS_FPR(reg); |
352 | char *ptr1 = (char *) ¤t->thread.TS_FPR(reg+1); | |
353 | int i, ret, sw = 0; | |
c6d4267e | 354 | |
c6d4267e PM |
355 | if (reg & 1) |
356 | return 0; /* invalid form: FRS/FRT must be even */ | |
553631e2 MN |
357 | if (flags & SW) |
358 | sw = 7; | |
359 | ret = 0; | |
360 | for (i = 0; i < 8; ++i) { | |
361 | if (!(flags & ST)) { | |
362 | ret |= __get_user(ptr0[i^sw], addr + i); | |
363 | ret |= __get_user(ptr1[i^sw], addr + i + 8); | |
364 | } else { | |
365 | ret |= __put_user(ptr0[i^sw], addr + i); | |
366 | ret |= __put_user(ptr1[i^sw], addr + i + 8); | |
c6d4267e PM |
367 | } |
368 | } | |
369 | if (ret) | |
370 | return -EFAULT; | |
371 | return 1; /* exception handled and fixed up */ | |
372 | } | |
373 | ||
f83319d7 AB |
374 | #ifdef CONFIG_PPC64 |
375 | static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr, | |
376 | unsigned int reg, unsigned int flags) | |
377 | { | |
378 | char *ptr0 = (char *)®s->gpr[reg]; | |
379 | char *ptr1 = (char *)®s->gpr[reg+1]; | |
380 | int i, ret, sw = 0; | |
381 | ||
382 | if (reg & 1) | |
383 | return 0; /* invalid form: GPR must be even */ | |
384 | if (flags & SW) | |
385 | sw = 7; | |
386 | ret = 0; | |
387 | for (i = 0; i < 8; ++i) { | |
388 | if (!(flags & ST)) { | |
389 | ret |= __get_user(ptr0[i^sw], addr + i); | |
390 | ret |= __get_user(ptr1[i^sw], addr + i + 8); | |
391 | } else { | |
392 | ret |= __put_user(ptr0[i^sw], addr + i); | |
393 | ret |= __put_user(ptr1[i^sw], addr + i + 8); | |
394 | } | |
395 | } | |
396 | if (ret) | |
397 | return -EFAULT; | |
398 | return 1; /* exception handled and fixed up */ | |
399 | } | |
400 | #endif /* CONFIG_PPC64 */ | |
401 | ||
26caeb2e KG |
402 | #ifdef CONFIG_SPE |
403 | ||
404 | static struct aligninfo spe_aligninfo[32] = { | |
405 | { 8, LD+E8 }, /* 0 00 00: evldd[x] */ | |
406 | { 8, LD+E4 }, /* 0 00 01: evldw[x] */ | |
407 | { 8, LD }, /* 0 00 10: evldh[x] */ | |
408 | INVALID, /* 0 00 11 */ | |
409 | { 2, LD }, /* 0 01 00: evlhhesplat[x] */ | |
410 | INVALID, /* 0 01 01 */ | |
411 | { 2, LD }, /* 0 01 10: evlhhousplat[x] */ | |
412 | { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */ | |
413 | { 4, LD }, /* 0 10 00: evlwhe[x] */ | |
414 | INVALID, /* 0 10 01 */ | |
415 | { 4, LD }, /* 0 10 10: evlwhou[x] */ | |
416 | { 4, LD+SE }, /* 0 10 11: evlwhos[x] */ | |
417 | { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */ | |
418 | INVALID, /* 0 11 01 */ | |
419 | { 4, LD }, /* 0 11 10: evlwhsplat[x] */ | |
420 | INVALID, /* 0 11 11 */ | |
421 | ||
422 | { 8, ST+E8 }, /* 1 00 00: evstdd[x] */ | |
423 | { 8, ST+E4 }, /* 1 00 01: evstdw[x] */ | |
424 | { 8, ST }, /* 1 00 10: evstdh[x] */ | |
425 | INVALID, /* 1 00 11 */ | |
426 | INVALID, /* 1 01 00 */ | |
427 | INVALID, /* 1 01 01 */ | |
428 | INVALID, /* 1 01 10 */ | |
429 | INVALID, /* 1 01 11 */ | |
430 | { 4, ST }, /* 1 10 00: evstwhe[x] */ | |
431 | INVALID, /* 1 10 01 */ | |
432 | { 4, ST }, /* 1 10 10: evstwho[x] */ | |
433 | INVALID, /* 1 10 11 */ | |
434 | { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */ | |
435 | INVALID, /* 1 11 01 */ | |
436 | { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */ | |
437 | INVALID, /* 1 11 11 */ | |
438 | }; | |
439 | ||
440 | #define EVLDD 0x00 | |
441 | #define EVLDW 0x01 | |
442 | #define EVLDH 0x02 | |
443 | #define EVLHHESPLAT 0x04 | |
444 | #define EVLHHOUSPLAT 0x06 | |
445 | #define EVLHHOSSPLAT 0x07 | |
446 | #define EVLWHE 0x08 | |
447 | #define EVLWHOU 0x0A | |
448 | #define EVLWHOS 0x0B | |
449 | #define EVLWWSPLAT 0x0C | |
450 | #define EVLWHSPLAT 0x0E | |
451 | #define EVSTDD 0x10 | |
452 | #define EVSTDW 0x11 | |
453 | #define EVSTDH 0x12 | |
454 | #define EVSTWHE 0x18 | |
455 | #define EVSTWHO 0x1A | |
456 | #define EVSTWWE 0x1C | |
457 | #define EVSTWWO 0x1E | |
458 | ||
459 | /* | |
460 | * Emulate SPE loads and stores. | |
461 | * Only Book-E has these instructions, and it does true little-endian, | |
462 | * so we don't need the address swizzling. | |
463 | */ | |
464 | static int emulate_spe(struct pt_regs *regs, unsigned int reg, | |
465 | unsigned int instr) | |
466 | { | |
f626190d | 467 | int ret; |
26caeb2e KG |
468 | union { |
469 | u64 ll; | |
470 | u32 w[2]; | |
471 | u16 h[4]; | |
472 | u8 v[8]; | |
473 | } data, temp; | |
474 | unsigned char __user *p, *addr; | |
475 | unsigned long *evr = ¤t->thread.evr[reg]; | |
476 | unsigned int nb, flags; | |
477 | ||
478 | instr = (instr >> 1) & 0x1f; | |
479 | ||
480 | /* DAR has the operand effective address */ | |
481 | addr = (unsigned char __user *)regs->dar; | |
482 | ||
483 | nb = spe_aligninfo[instr].len; | |
484 | flags = spe_aligninfo[instr].flags; | |
485 | ||
486 | /* Verify the address of the operand */ | |
487 | if (unlikely(user_mode(regs) && | |
488 | !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ), | |
489 | addr, nb))) | |
490 | return -EFAULT; | |
491 | ||
492 | /* userland only */ | |
493 | if (unlikely(!user_mode(regs))) | |
494 | return 0; | |
495 | ||
496 | flush_spe_to_thread(current); | |
497 | ||
498 | /* If we are loading, get the data from user space, else | |
499 | * get it from register values | |
500 | */ | |
501 | if (flags & ST) { | |
502 | data.ll = 0; | |
503 | switch (instr) { | |
504 | case EVSTDD: | |
505 | case EVSTDW: | |
506 | case EVSTDH: | |
507 | data.w[0] = *evr; | |
508 | data.w[1] = regs->gpr[reg]; | |
509 | break; | |
510 | case EVSTWHE: | |
511 | data.h[2] = *evr >> 16; | |
512 | data.h[3] = regs->gpr[reg] >> 16; | |
513 | break; | |
514 | case EVSTWHO: | |
515 | data.h[2] = *evr & 0xffff; | |
516 | data.h[3] = regs->gpr[reg] & 0xffff; | |
517 | break; | |
518 | case EVSTWWE: | |
519 | data.w[1] = *evr; | |
520 | break; | |
521 | case EVSTWWO: | |
522 | data.w[1] = regs->gpr[reg]; | |
523 | break; | |
524 | default: | |
525 | return -EINVAL; | |
526 | } | |
527 | } else { | |
528 | temp.ll = data.ll = 0; | |
529 | ret = 0; | |
530 | p = addr; | |
531 | ||
532 | switch (nb) { | |
533 | case 8: | |
534 | ret |= __get_user_inatomic(temp.v[0], p++); | |
535 | ret |= __get_user_inatomic(temp.v[1], p++); | |
536 | ret |= __get_user_inatomic(temp.v[2], p++); | |
537 | ret |= __get_user_inatomic(temp.v[3], p++); | |
538 | case 4: | |
539 | ret |= __get_user_inatomic(temp.v[4], p++); | |
540 | ret |= __get_user_inatomic(temp.v[5], p++); | |
541 | case 2: | |
542 | ret |= __get_user_inatomic(temp.v[6], p++); | |
543 | ret |= __get_user_inatomic(temp.v[7], p++); | |
544 | if (unlikely(ret)) | |
545 | return -EFAULT; | |
546 | } | |
547 | ||
548 | switch (instr) { | |
549 | case EVLDD: | |
550 | case EVLDW: | |
551 | case EVLDH: | |
552 | data.ll = temp.ll; | |
553 | break; | |
554 | case EVLHHESPLAT: | |
555 | data.h[0] = temp.h[3]; | |
556 | data.h[2] = temp.h[3]; | |
557 | break; | |
558 | case EVLHHOUSPLAT: | |
559 | case EVLHHOSSPLAT: | |
560 | data.h[1] = temp.h[3]; | |
561 | data.h[3] = temp.h[3]; | |
562 | break; | |
563 | case EVLWHE: | |
564 | data.h[0] = temp.h[2]; | |
565 | data.h[2] = temp.h[3]; | |
566 | break; | |
567 | case EVLWHOU: | |
568 | case EVLWHOS: | |
569 | data.h[1] = temp.h[2]; | |
570 | data.h[3] = temp.h[3]; | |
571 | break; | |
572 | case EVLWWSPLAT: | |
573 | data.w[0] = temp.w[1]; | |
574 | data.w[1] = temp.w[1]; | |
575 | break; | |
576 | case EVLWHSPLAT: | |
577 | data.h[0] = temp.h[2]; | |
578 | data.h[1] = temp.h[2]; | |
579 | data.h[2] = temp.h[3]; | |
580 | data.h[3] = temp.h[3]; | |
581 | break; | |
582 | default: | |
583 | return -EINVAL; | |
584 | } | |
585 | } | |
586 | ||
587 | if (flags & SW) { | |
588 | switch (flags & 0xf0) { | |
589 | case E8: | |
f626190d | 590 | data.ll = swab64(data.ll); |
26caeb2e KG |
591 | break; |
592 | case E4: | |
f626190d AB |
593 | data.w[0] = swab32(data.w[0]); |
594 | data.w[1] = swab32(data.w[1]); | |
26caeb2e KG |
595 | break; |
596 | /* Its half word endian */ | |
597 | default: | |
f626190d AB |
598 | data.h[0] = swab16(data.h[0]); |
599 | data.h[1] = swab16(data.h[1]); | |
600 | data.h[2] = swab16(data.h[2]); | |
601 | data.h[3] = swab16(data.h[3]); | |
26caeb2e KG |
602 | break; |
603 | } | |
604 | } | |
605 | ||
606 | if (flags & SE) { | |
607 | data.w[0] = (s16)data.h[1]; | |
608 | data.w[1] = (s16)data.h[3]; | |
609 | } | |
610 | ||
611 | /* Store result to memory or update registers */ | |
612 | if (flags & ST) { | |
613 | ret = 0; | |
614 | p = addr; | |
615 | switch (nb) { | |
616 | case 8: | |
617 | ret |= __put_user_inatomic(data.v[0], p++); | |
618 | ret |= __put_user_inatomic(data.v[1], p++); | |
619 | ret |= __put_user_inatomic(data.v[2], p++); | |
620 | ret |= __put_user_inatomic(data.v[3], p++); | |
621 | case 4: | |
622 | ret |= __put_user_inatomic(data.v[4], p++); | |
623 | ret |= __put_user_inatomic(data.v[5], p++); | |
624 | case 2: | |
625 | ret |= __put_user_inatomic(data.v[6], p++); | |
626 | ret |= __put_user_inatomic(data.v[7], p++); | |
627 | } | |
628 | if (unlikely(ret)) | |
629 | return -EFAULT; | |
630 | } else { | |
631 | *evr = data.w[0]; | |
632 | regs->gpr[reg] = data.w[1]; | |
633 | } | |
634 | ||
635 | return 1; | |
636 | } | |
637 | #endif /* CONFIG_SPE */ | |
5daf9071 | 638 | |
52055d07 | 639 | #ifdef CONFIG_VSX |
cd6f37be MN |
640 | /* |
641 | * Emulate VSX instructions... | |
642 | */ | |
643 | static int emulate_vsx(unsigned char __user *addr, unsigned int reg, | |
644 | unsigned int areg, struct pt_regs *regs, | |
bb7f20b1 NC |
645 | unsigned int flags, unsigned int length, |
646 | unsigned int elsize) | |
cd6f37be | 647 | { |
26456dcf | 648 | char *ptr; |
bb7f20b1 | 649 | unsigned long *lptr; |
78fbc824 | 650 | int ret = 0; |
bb7f20b1 NC |
651 | int sw = 0; |
652 | int i, j; | |
cd6f37be | 653 | |
5c2e0823 AB |
654 | /* userland only */ |
655 | if (unlikely(!user_mode(regs))) | |
656 | return 0; | |
657 | ||
cd6f37be MN |
658 | flush_vsx_to_thread(current); |
659 | ||
26456dcf | 660 | if (reg < 32) |
3ad26e5c | 661 | ptr = (char *) ¤t->thread.fp_state.fpr[reg][0]; |
26456dcf | 662 | else |
de79f7b9 | 663 | ptr = (char *) ¤t->thread.vr_state.vr[reg - 32]; |
26456dcf | 664 | |
bb7f20b1 NC |
665 | lptr = (unsigned long *) ptr; |
666 | ||
52055d07 AB |
667 | #ifdef __LITTLE_ENDIAN__ |
668 | if (flags & SW) { | |
669 | elsize = length; | |
670 | sw = length-1; | |
671 | } else { | |
672 | /* | |
673 | * The elements are BE ordered, even in LE mode, so process | |
674 | * them in reverse order. | |
675 | */ | |
676 | addr += length - elsize; | |
677 | ||
678 | /* 8 byte memory accesses go in the top 8 bytes of the VR */ | |
679 | if (length == 8) | |
680 | ptr += 8; | |
681 | } | |
682 | #else | |
bb7f20b1 NC |
683 | if (flags & SW) |
684 | sw = elsize-1; | |
52055d07 | 685 | #endif |
bb7f20b1 NC |
686 | |
687 | for (j = 0; j < length; j += elsize) { | |
688 | for (i = 0; i < elsize; ++i) { | |
689 | if (flags & ST) | |
690 | ret |= __put_user(ptr[i^sw], addr + i); | |
691 | else | |
692 | ret |= __get_user(ptr[i^sw], addr + i); | |
cd6f37be | 693 | } |
bb7f20b1 | 694 | ptr += elsize; |
52055d07 AB |
695 | #ifdef __LITTLE_ENDIAN__ |
696 | addr -= elsize; | |
697 | #else | |
bb7f20b1 | 698 | addr += elsize; |
52055d07 | 699 | #endif |
cd6f37be | 700 | } |
bb7f20b1 | 701 | |
52055d07 AB |
702 | #ifdef __BIG_ENDIAN__ |
703 | #define VSX_HI 0 | |
704 | #define VSX_LO 1 | |
705 | #else | |
706 | #define VSX_HI 1 | |
707 | #define VSX_LO 0 | |
708 | #endif | |
709 | ||
bb7f20b1 NC |
710 | if (!ret) { |
711 | if (flags & U) | |
712 | regs->gpr[areg] = regs->dar; | |
713 | ||
714 | /* Splat load copies the same data to top and bottom 8 bytes */ | |
715 | if (flags & SPLT) | |
52055d07 AB |
716 | lptr[VSX_LO] = lptr[VSX_HI]; |
717 | /* For 8 byte loads, zero the low 8 bytes */ | |
bb7f20b1 | 718 | else if (!(flags & ST) && (8 == length)) |
52055d07 | 719 | lptr[VSX_LO] = 0; |
bb7f20b1 | 720 | } else |
cd6f37be | 721 | return -EFAULT; |
bb7f20b1 | 722 | |
cd6f37be MN |
723 | return 1; |
724 | } | |
725 | #endif | |
726 | ||
5daf9071 BH |
727 | /* |
728 | * Called on alignment exception. Attempts to fixup | |
729 | * | |
730 | * Return 1 on success | |
731 | * Return 0 if unable to handle the interrupt | |
732 | * Return -EFAULT if data address is bad | |
733 | */ | |
734 | ||
735 | int fix_alignment(struct pt_regs *regs) | |
1da177e4 | 736 | { |
cd6f37be | 737 | unsigned int instr, nb, flags, instruction = 0; |
5daf9071 BH |
738 | unsigned int reg, areg; |
739 | unsigned int dsisr; | |
1da177e4 | 740 | unsigned char __user *addr; |
fab5db97 | 741 | unsigned long p, swiz; |
835e206a AB |
742 | int ret, i; |
743 | union data { | |
5daf9071 | 744 | u64 ll; |
1da177e4 LT |
745 | double dd; |
746 | unsigned char v[8]; | |
747 | struct { | |
835e206a AB |
748 | #ifdef __LITTLE_ENDIAN__ |
749 | int low32; | |
750 | unsigned hi32; | |
751 | #else | |
1da177e4 LT |
752 | unsigned hi32; |
753 | int low32; | |
835e206a | 754 | #endif |
1da177e4 LT |
755 | } x32; |
756 | struct { | |
835e206a AB |
757 | #ifdef __LITTLE_ENDIAN__ |
758 | short low16; | |
759 | unsigned char hi48[6]; | |
760 | #else | |
1da177e4 LT |
761 | unsigned char hi48[6]; |
762 | short low16; | |
835e206a | 763 | #endif |
1da177e4 LT |
764 | } x16; |
765 | } data; | |
766 | ||
767 | /* | |
5daf9071 BH |
768 | * We require a complete register set, if not, then our assembly |
769 | * is broken | |
1da177e4 | 770 | */ |
5daf9071 | 771 | CHECK_FULL_REGS(regs); |
1da177e4 LT |
772 | |
773 | dsisr = regs->dsisr; | |
774 | ||
5daf9071 BH |
775 | /* Some processors don't provide us with a DSISR we can use here, |
776 | * let's make one up from the instruction | |
777 | */ | |
1da177e4 | 778 | if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) { |
fab5db97 PM |
779 | unsigned long pc = regs->nip; |
780 | ||
781 | if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE)) | |
782 | pc ^= 4; | |
e4ee3891 BH |
783 | if (unlikely(__get_user_inatomic(instr, |
784 | (unsigned int __user *)pc))) | |
5daf9071 | 785 | return -EFAULT; |
fab5db97 PM |
786 | if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE)) |
787 | instr = cpu_to_le32(instr); | |
788 | dsisr = make_dsisr(instr); | |
cd6f37be | 789 | instruction = instr; |
1da177e4 LT |
790 | } |
791 | ||
792 | /* extract the operation and registers from the dsisr */ | |
793 | reg = (dsisr >> 5) & 0x1f; /* source/dest register */ | |
794 | areg = dsisr & 0x1f; /* register to update */ | |
26caeb2e KG |
795 | |
796 | #ifdef CONFIG_SPE | |
80947e7c | 797 | if ((instr >> 26) == 0x4) { |
eecff81d | 798 | PPC_WARN_ALIGNMENT(spe, regs); |
26caeb2e | 799 | return emulate_spe(regs, reg, instr); |
80947e7c | 800 | } |
26caeb2e KG |
801 | #endif |
802 | ||
1da177e4 LT |
803 | instr = (dsisr >> 10) & 0x7f; |
804 | instr |= (dsisr >> 13) & 0x60; | |
805 | ||
806 | /* Lookup the operation in our table */ | |
807 | nb = aligninfo[instr].len; | |
808 | flags = aligninfo[instr].flags; | |
809 | ||
48fe9e94 PM |
810 | /* |
811 | * Handle some cases which give overlaps in the DSISR values. | |
812 | */ | |
813 | if (IS_XFORM(instruction)) { | |
814 | switch (get_xop(instruction)) { | |
815 | case 532: /* ldbrx */ | |
816 | nb = 8; | |
817 | flags = LD+SW; | |
818 | break; | |
819 | case 660: /* stdbrx */ | |
820 | nb = 8; | |
821 | flags = ST+SW; | |
822 | break; | |
823 | case 20: /* lwarx */ | |
824 | case 84: /* ldarx */ | |
825 | case 116: /* lharx */ | |
826 | case 276: /* lqarx */ | |
827 | return 0; /* not emulated ever */ | |
828 | } | |
230aef7a AB |
829 | } |
830 | ||
fab5db97 PM |
831 | /* Byteswap little endian loads and stores */ |
832 | swiz = 0; | |
835e206a | 833 | if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) { |
fab5db97 | 834 | flags ^= SW; |
835e206a | 835 | #ifdef __BIG_ENDIAN__ |
fab5db97 PM |
836 | /* |
837 | * So-called "PowerPC little endian" mode works by | |
838 | * swizzling addresses rather than by actually doing | |
839 | * any byte-swapping. To emulate this, we XOR each | |
840 | * byte address with 7. We also byte-swap, because | |
841 | * the processor's address swizzling depends on the | |
842 | * operand size (it xors the address with 7 for bytes, | |
843 | * 6 for halfwords, 4 for words, 0 for doublewords) but | |
844 | * we will xor with 7 and load/store each byte separately. | |
845 | */ | |
846 | if (cpu_has_feature(CPU_FTR_PPC_LE)) | |
847 | swiz = 7; | |
835e206a | 848 | #endif |
fab5db97 PM |
849 | } |
850 | ||
1da177e4 LT |
851 | /* DAR has the operand effective address */ |
852 | addr = (unsigned char __user *)regs->dar; | |
853 | ||
cd6f37be MN |
854 | #ifdef CONFIG_VSX |
855 | if ((instruction & 0xfc00003e) == 0x7c000018) { | |
bb7f20b1 NC |
856 | unsigned int elsize; |
857 | ||
858 | /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */ | |
cd6f37be MN |
859 | reg |= (instruction & 0x1) << 5; |
860 | /* Simple inline decoder instead of a table */ | |
bb7f20b1 NC |
861 | /* VSX has only 8 and 16 byte memory accesses */ |
862 | nb = 8; | |
cd6f37be MN |
863 | if (instruction & 0x200) |
864 | nb = 16; | |
bb7f20b1 NC |
865 | |
866 | /* Vector stores in little-endian mode swap individual | |
867 | elements, so process them separately */ | |
868 | elsize = 4; | |
869 | if (instruction & 0x80) | |
870 | elsize = 8; | |
871 | ||
cd6f37be | 872 | flags = 0; |
835e206a | 873 | if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) |
bb7f20b1 | 874 | flags |= SW; |
cd6f37be MN |
875 | if (instruction & 0x100) |
876 | flags |= ST; | |
877 | if (instruction & 0x040) | |
878 | flags |= U; | |
879 | /* splat load needs a special decoder */ | |
880 | if ((instruction & 0x400) == 0){ | |
881 | flags |= SPLT; | |
882 | nb = 8; | |
883 | } | |
eecff81d | 884 | PPC_WARN_ALIGNMENT(vsx, regs); |
bb7f20b1 | 885 | return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize); |
cd6f37be MN |
886 | } |
887 | #endif | |
ae26b36f CS |
888 | |
889 | /* | |
890 | * ISA 3.0 (such as P9) copy, copy_first, paste and paste_last alignment | |
891 | * check. | |
892 | * | |
893 | * Send a SIGBUS to the process that caused the fault. | |
894 | * | |
895 | * We do not emulate these because paste may contain additional metadata | |
896 | * when pasting to a co-processor. Furthermore, paste_last is the | |
897 | * synchronisation point for preceding copy/paste sequences. | |
898 | */ | |
899 | if ((instruction & 0xfc0006fe) == PPC_INST_COPY) | |
900 | return -EIO; | |
901 | ||
5daf9071 BH |
902 | /* A size of 0 indicates an instruction we don't support, with |
903 | * the exception of DCBZ which is handled as a special case here | |
1da177e4 | 904 | */ |
80947e7c | 905 | if (instr == DCBZ) { |
eecff81d | 906 | PPC_WARN_ALIGNMENT(dcbz, regs); |
5daf9071 | 907 | return emulate_dcbz(regs, addr); |
80947e7c | 908 | } |
5daf9071 BH |
909 | if (unlikely(nb == 0)) |
910 | return 0; | |
911 | ||
912 | /* Load/Store Multiple instructions are handled in their own | |
913 | * function | |
914 | */ | |
80947e7c | 915 | if (flags & M) { |
eecff81d | 916 | PPC_WARN_ALIGNMENT(multiple, regs); |
fab5db97 PM |
917 | return emulate_multiple(regs, addr, reg, nb, |
918 | flags, instr, swiz); | |
80947e7c | 919 | } |
1da177e4 LT |
920 | |
921 | /* Verify the address of the operand */ | |
5daf9071 BH |
922 | if (unlikely(user_mode(regs) && |
923 | !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ), | |
924 | addr, nb))) | |
925 | return -EFAULT; | |
1da177e4 LT |
926 | |
927 | /* Force the fprs into the save area so we can reference them */ | |
928 | if (flags & F) { | |
5daf9071 BH |
929 | /* userland only */ |
930 | if (unlikely(!user_mode(regs))) | |
1da177e4 LT |
931 | return 0; |
932 | flush_fp_to_thread(current); | |
933 | } | |
5daf9071 | 934 | |
6f791bef | 935 | if (nb == 16) { |
f83319d7 AB |
936 | if (flags & F) { |
937 | /* Special case for 16-byte FP loads and stores */ | |
938 | PPC_WARN_ALIGNMENT(fp_pair, regs); | |
939 | return emulate_fp_pair(addr, reg, flags); | |
940 | } else { | |
941 | #ifdef CONFIG_PPC64 | |
942 | /* Special case for 16-byte loads and stores */ | |
943 | PPC_WARN_ALIGNMENT(lq_stq, regs); | |
944 | return emulate_lq_stq(regs, addr, reg, flags); | |
945 | #else | |
946 | return 0; | |
947 | #endif | |
948 | } | |
80947e7c GU |
949 | } |
950 | ||
eecff81d | 951 | PPC_WARN_ALIGNMENT(unaligned, regs); |
c6d4267e | 952 | |
5daf9071 BH |
953 | /* If we are loading, get the data from user space, else |
954 | * get it from register values | |
955 | */ | |
fab5db97 | 956 | if (!(flags & ST)) { |
835e206a AB |
957 | unsigned int start = 0; |
958 | ||
1da177e4 | 959 | switch (nb) { |
1da177e4 | 960 | case 4: |
835e206a AB |
961 | start = offsetof(union data, x32.low32); |
962 | break; | |
1da177e4 | 963 | case 2: |
835e206a AB |
964 | start = offsetof(union data, x16.low16); |
965 | break; | |
1da177e4 | 966 | } |
835e206a AB |
967 | |
968 | data.ll = 0; | |
969 | ret = 0; | |
970 | p = (unsigned long)addr; | |
971 | ||
972 | for (i = 0; i < nb; i++) | |
973 | ret |= __get_user_inatomic(data.v[start + i], | |
974 | SWIZ_PTR(p++)); | |
975 | ||
976 | if (unlikely(ret)) | |
977 | return -EFAULT; | |
978 | ||
fab5db97 | 979 | } else if (flags & F) { |
de79f7b9 | 980 | data.ll = current->thread.TS_FPR(reg); |
fab5db97 PM |
981 | if (flags & S) { |
982 | /* Single-precision FP store requires conversion... */ | |
983 | #ifdef CONFIG_PPC_FPU | |
984 | preempt_disable(); | |
985 | enable_kernel_fp(); | |
c3244964 | 986 | cvt_df(&data.dd, (float *)&data.x32.low32); |
dc4fbba1 | 987 | disable_kernel_fp(); |
fab5db97 PM |
988 | preempt_enable(); |
989 | #else | |
990 | return 0; | |
991 | #endif | |
992 | } | |
993 | } else | |
5daf9071 BH |
994 | data.ll = regs->gpr[reg]; |
995 | ||
fab5db97 PM |
996 | if (flags & SW) { |
997 | switch (nb) { | |
998 | case 8: | |
f626190d | 999 | data.ll = swab64(data.ll); |
fab5db97 PM |
1000 | break; |
1001 | case 4: | |
f626190d | 1002 | data.x32.low32 = swab32(data.x32.low32); |
fab5db97 PM |
1003 | break; |
1004 | case 2: | |
f626190d | 1005 | data.x16.low16 = swab16(data.x16.low16); |
fab5db97 PM |
1006 | break; |
1007 | } | |
1008 | } | |
1009 | ||
1010 | /* Perform other misc operations like sign extension | |
5daf9071 BH |
1011 | * or floating point single precision conversion |
1012 | */ | |
fab5db97 | 1013 | switch (flags & ~(U|SW)) { |
c6d4267e PM |
1014 | case LD+SE: /* sign extending integer loads */ |
1015 | case LD+F+SE: /* sign extend for lfiwax */ | |
1da177e4 LT |
1016 | if ( nb == 2 ) |
1017 | data.ll = data.x16.low16; | |
1018 | else /* nb must be 4 */ | |
1019 | data.ll = data.x32.low32; | |
5daf9071 | 1020 | break; |
5daf9071 | 1021 | |
fab5db97 | 1022 | /* Single-precision FP load requires conversion... */ |
5daf9071 BH |
1023 | case LD+F+S: |
1024 | #ifdef CONFIG_PPC_FPU | |
1025 | preempt_disable(); | |
1026 | enable_kernel_fp(); | |
c3244964 | 1027 | cvt_fd((float *)&data.x32.low32, &data.dd); |
dc4fbba1 | 1028 | disable_kernel_fp(); |
5daf9071 BH |
1029 | preempt_enable(); |
1030 | #else | |
1031 | return 0; | |
5daf9071 BH |
1032 | #endif |
1033 | break; | |
1da177e4 | 1034 | } |
5daf9071 BH |
1035 | |
1036 | /* Store result to memory or update registers */ | |
1da177e4 | 1037 | if (flags & ST) { |
835e206a AB |
1038 | unsigned int start = 0; |
1039 | ||
1da177e4 | 1040 | switch (nb) { |
1da177e4 | 1041 | case 4: |
835e206a AB |
1042 | start = offsetof(union data, x32.low32); |
1043 | break; | |
1da177e4 | 1044 | case 2: |
835e206a AB |
1045 | start = offsetof(union data, x16.low16); |
1046 | break; | |
1da177e4 | 1047 | } |
835e206a AB |
1048 | |
1049 | ret = 0; | |
1050 | p = (unsigned long)addr; | |
1051 | ||
1052 | for (i = 0; i < nb; i++) | |
1053 | ret |= __put_user_inatomic(data.v[start + i], | |
1054 | SWIZ_PTR(p++)); | |
1055 | ||
5daf9071 | 1056 | if (unlikely(ret)) |
1da177e4 | 1057 | return -EFAULT; |
5daf9071 | 1058 | } else if (flags & F) |
de79f7b9 | 1059 | current->thread.TS_FPR(reg) = data.ll; |
5daf9071 BH |
1060 | else |
1061 | regs->gpr[reg] = data.ll; | |
1062 | ||
1da177e4 | 1063 | /* Update RA as needed */ |
5daf9071 | 1064 | if (flags & U) |
1da177e4 | 1065 | regs->gpr[areg] = regs->dar; |
1da177e4 LT |
1066 | |
1067 | return 1; | |
1068 | } |